Analysis & Synthesis report for DE1_i2sound
Thu Sep 28 19:55:00 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |DE1_i2sound|I2C_AV_Config:u1|mSetup_ST
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: PLL:u0|altpll:altpll_component
 12. Parameter Settings for User Entity Instance: I2C_AV_Config:u1
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Sep 28 19:55:00 2006         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE1_i2sound                                   ;
; Top-level Entity Name              ; DE1_i2sound                                   ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 106                                           ;
; Total registers                    ; 68                                            ;
; Total pins                         ; 283                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0                                             ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C20F484C7       ;                    ;
; Top-level entity name                                              ; DE1_i2sound        ; DE1_i2sound        ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                      ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                  ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------+
; DE1_i2sound.v                    ; yes             ; User Verilog HDL File  ; C:/DE1/DE1_i2sound/DE1_i2sound.v                              ;
; I2C_AV_Config.v                  ; yes             ; User Verilog HDL File  ; C:/DE1/DE1_i2sound/I2C_AV_Config.v                            ;
; I2C_Controller.v                 ; yes             ; User Verilog HDL File  ; C:/DE1/DE1_i2sound/I2C_Controller.v                           ;
; PLL.v                            ; yes             ; User Verilog HDL File  ; C:/DE1/DE1_i2sound/PLL.v                                      ;
; altpll.tdf                       ; yes             ; Megafunction           ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf        ;
; aglobal60.inc                    ; yes             ; Other                  ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc     ;
; stratix_pll.inc                  ; yes             ; Other                  ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc   ;
; stratixii_pll.inc                ; yes             ; Other                  ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc                ; yes             ; Other                  ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------+


+------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                  ;
+---------------------------------------------+--------------------------------+
; Resource                                    ; Usage                          ;
+---------------------------------------------+--------------------------------+
; Estimated Total logic elements              ; 106                            ;
; Total combinational functions               ; 106                            ;
; Logic element usage by number of LUT inputs ;                                ;
;     -- 4 input functions                    ; 54                             ;
;     -- 3 input functions                    ; 17                             ;
;     -- <=2 input functions                  ; 35                             ;
;         -- Combinational cells for routing  ; 0                              ;
; Logic elements by mode                      ;                                ;
;     -- normal mode                          ; 80                             ;
;     -- arithmetic mode                      ; 26                             ;
; Total registers                             ; 68                             ;
; I/O pins                                    ; 283                            ;
; Total PLLs                                  ; 1                              ;
; Maximum fan-out node                        ; I2C_AV_Config:u1|mI2C_CTRL_CLK ;
; Maximum fan-out                             ; 46                             ;
; Total fan-out                               ; 578                            ;
; Average fan-out                             ; 1.26                           ;
+---------------------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                  ;
+---------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------+
; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                             ;
+---------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------+
; |DE1_i2sound                    ; 106 (10)          ; 68 (7)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 283  ; 0            ; |DE1_i2sound                                    ;
;    |I2C_AV_Config:u1|           ; 96 (53)           ; 61 (37)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_i2sound|I2C_AV_Config:u1                   ;
;       |I2C_Controller:u0|       ; 43 (43)           ; 24 (24)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_i2sound|I2C_AV_Config:u1|I2C_Controller:u0 ;
;    |PLL:u0|                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_i2sound|PLL:u0                             ;
;       |altpll:altpll_component| ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_i2sound|PLL:u0|altpll:altpll_component     ;
+---------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------+
; State Machine - |DE1_i2sound|I2C_AV_Config:u1|mSetup_ST   ;
+--------------+--------------+--------------+--------------+
; Name         ; mSetup_ST.00 ; mSetup_ST.10 ; mSetup_ST.01 ;
+--------------+--------------+--------------+--------------+
; mSetup_ST.00 ; 0            ; 0            ; 0            ;
; mSetup_ST.01 ; 1            ; 0            ; 1            ;
; mSetup_ST.10 ; 1            ; 1            ; 0            ;
+--------------+--------------+--------------+--------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 68    ;
; Number of registers using Synchronous Clear  ; 16    ;
; Number of registers using Synchronous Load   ; 13    ;
; Number of registers using Asynchronous Clear ; 37    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 28    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------+
; Inverted Register Statistics                               ;
+--------------------------------------------------+---------+
; Inverted Register                                ; Fan out ;
+--------------------------------------------------+---------+
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] ; 19      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2] ; 15      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] ; 19      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] ; 13      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4] ; 11      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5] ; 12      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SCLK          ; 2       ;
; I2C_AV_Config:u1|I2C_Controller:u0|END           ; 5       ;
; I2C_AV_Config:u1|I2C_Controller:u0|SDO           ; 4       ;
; Total number of inverted registers = 9           ;         ;
+--------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 16:1               ; 7 bits    ; 70 LEs        ; 56 LEs               ; 14 LEs                 ; Yes        ; |DE1_i2sound|I2C_AV_Config:u1|mI2C_DATA[6] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+


+-----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL:u0|altpll:altpll_component ;
+-------------------------------+-------------+-------------------------------+
; Parameter Name                ; Value       ; Type                          ;
+-------------------------------+-------------+-------------------------------+
; OPERATION_MODE                ; NORMAL      ; Untyped                       ;
; PLL_TYPE                      ; FAST        ; Untyped                       ;
; QUALIFY_CONF_DONE             ; OFF         ; Untyped                       ;
; COMPENSATE_CLOCK              ; CLK0        ; Untyped                       ;
; SCAN_CHAIN                    ; LONG        ; Untyped                       ;
; PRIMARY_CLOCK                 ; INCLK0      ; Untyped                       ;
; INCLK0_INPUT_FREQUENCY        ; 37037       ; Integer                       ;
; INCLK1_INPUT_FREQUENCY        ; 0           ; Untyped                       ;
; GATE_LOCK_SIGNAL              ; NO          ; Untyped                       ;
; GATE_LOCK_COUNTER             ; 0           ; Untyped                       ;
; LOCK_HIGH                     ; 1           ; Untyped                       ;
; LOCK_LOW                      ; 1           ; Untyped                       ;
; VALID_LOCK_MULTIPLIER         ; 1           ; Untyped                       ;
; INVALID_LOCK_MULTIPLIER       ; 5           ; Untyped                       ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF         ; Untyped                       ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF         ; Untyped                       ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF         ; Untyped                       ;
; SKIP_VCO                      ; OFF         ; Untyped                       ;
; SWITCH_OVER_COUNTER           ; 0           ; Untyped                       ;
; SWITCH_OVER_TYPE              ; AUTO        ; Untyped                       ;
; FEEDBACK_SOURCE               ; EXTCLK0     ; Untyped                       ;
; BANDWIDTH                     ; 0           ; Untyped                       ;
; BANDWIDTH_TYPE                ; AUTO        ; Untyped                       ;
; SPREAD_FREQUENCY              ; 0           ; Untyped                       ;
; DOWN_SPREAD                   ; 0           ; Untyped                       ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF         ; Untyped                       ;
; CLK5_MULTIPLY_BY              ; 1           ; Untyped                       ;
; CLK4_MULTIPLY_BY              ; 1           ; Untyped                       ;
; CLK3_MULTIPLY_BY              ; 1           ; Untyped                       ;
; CLK2_MULTIPLY_BY              ; 1           ; Untyped                       ;
; CLK1_MULTIPLY_BY              ; 1           ; Untyped                       ;
; CLK0_MULTIPLY_BY              ; 92          ; Integer                       ;
; CLK5_DIVIDE_BY                ; 1           ; Untyped                       ;
; CLK4_DIVIDE_BY                ; 1           ; Untyped                       ;
; CLK3_DIVIDE_BY                ; 1           ; Untyped                       ;
; CLK2_DIVIDE_BY                ; 1           ; Untyped                       ;
; CLK1_DIVIDE_BY                ; 1           ; Untyped                       ;
; CLK0_DIVIDE_BY                ; 135         ; Integer                       ;
; CLK5_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK4_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK3_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK2_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK1_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK0_PHASE_SHIFT              ; 0           ; Untyped                       ;
; CLK5_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK4_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK3_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK2_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK1_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK0_TIME_DELAY               ; 0           ; Untyped                       ;
; CLK5_DUTY_CYCLE               ; 50          ; Untyped                       ;
; CLK4_DUTY_CYCLE               ; 50          ; Untyped                       ;
; CLK3_DUTY_CYCLE               ; 50          ; Untyped                       ;
; CLK2_DUTY_CYCLE               ; 50          ; Untyped                       ;
; CLK1_DUTY_CYCLE               ; 50          ; Untyped                       ;
; CLK0_DUTY_CYCLE               ; 50          ; Integer                       ;
; EXTCLK3_MULTIPLY_BY           ; 1           ; Untyped                       ;
; EXTCLK2_MULTIPLY_BY           ; 1           ; Untyped                       ;
; EXTCLK1_MULTIPLY_BY           ; 1           ; Untyped                       ;
; EXTCLK0_MULTIPLY_BY           ; 1           ; Untyped                       ;
; EXTCLK3_DIVIDE_BY             ; 1           ; Untyped                       ;
; EXTCLK2_DIVIDE_BY             ; 1           ; Untyped                       ;
; EXTCLK1_DIVIDE_BY             ; 1           ; Untyped                       ;
; EXTCLK0_DIVIDE_BY             ; 1           ; Untyped                       ;
; EXTCLK3_PHASE_SHIFT           ; 0           ; Untyped                       ;
; EXTCLK2_PHASE_SHIFT           ; 0           ; Untyped                       ;
; EXTCLK1_PHASE_SHIFT           ; 0           ; Untyped                       ;
; EXTCLK0_PHASE_SHIFT           ; 0           ; Untyped                       ;
; EXTCLK3_TIME_DELAY            ; 0           ; Untyped                       ;
; EXTCLK2_TIME_DELAY            ; 0           ; Untyped                       ;
; EXTCLK1_TIME_DELAY            ; 0           ; Untyped                       ;
; EXTCLK0_TIME_DELAY            ; 0           ; Untyped                       ;
; EXTCLK3_DUTY_CYCLE            ; 50          ; Untyped                       ;
; EXTCLK2_DUTY_CYCLE            ; 50          ; Untyped                       ;
; EXTCLK1_DUTY_CYCLE            ; 50          ; Untyped                       ;
; EXTCLK0_DUTY_CYCLE            ; 50          ; Untyped                       ;
; VCO_MULTIPLY_BY               ; 0           ; Untyped                       ;
; VCO_DIVIDE_BY                 ; 0           ; Untyped                       ;
; SCLKOUT0_PHASE_SHIFT          ; 0           ; Untyped                       ;
; SCLKOUT1_PHASE_SHIFT          ; 0           ; Untyped                       ;
; VCO_MIN                       ; 0           ; Untyped                       ;
; VCO_MAX                       ; 0           ; Untyped                       ;
; VCO_CENTER                    ; 0           ; Untyped                       ;
; PFD_MIN                       ; 0           ; Untyped                       ;
; PFD_MAX                       ; 0           ; Untyped                       ;
; M_INITIAL                     ; 0           ; Untyped                       ;
; M                             ; 0           ; Untyped                       ;
; N                             ; 1           ; Untyped                       ;
; M2                            ; 1           ; Untyped                       ;
; N2                            ; 1           ; Untyped                       ;
; SS                            ; 1           ; Untyped                       ;
; C0_HIGH                       ; 0           ; Untyped                       ;
; C1_HIGH                       ; 0           ; Untyped                       ;
; C2_HIGH                       ; 0           ; Untyped                       ;
; C3_HIGH                       ; 0           ; Untyped                       ;
; C4_HIGH                       ; 0           ; Untyped                       ;
; C5_HIGH                       ; 0           ; Untyped                       ;
; C0_LOW                        ; 0           ; Untyped                       ;
; C1_LOW                        ; 0           ; Untyped                       ;
; C2_LOW                        ; 0           ; Untyped                       ;
; C3_LOW                        ; 0           ; Untyped                       ;
; C4_LOW                        ; 0           ; Untyped                       ;
; C5_LOW                        ; 0           ; Untyped                       ;
; C0_INITIAL                    ; 0           ; Untyped                       ;
; C1_INITIAL                    ; 0           ; Untyped                       ;
; C2_INITIAL                    ; 0           ; Untyped                       ;
; C3_INITIAL                    ; 0           ; Untyped                       ;
; C4_INITIAL                    ; 0           ; Untyped                       ;
; C5_INITIAL                    ; 0           ; Untyped                       ;
; C0_MODE                       ; BYPASS      ; Untyped                       ;
; C1_MODE                       ; BYPASS      ; Untyped                       ;
; C2_MODE                       ; BYPASS      ; Untyped                       ;
; C3_MODE                       ; BYPASS      ; Untyped                       ;
; C4_MODE                       ; BYPASS      ; Untyped                       ;
; C5_MODE                       ; BYPASS      ; Untyped                       ;
; C0_PH                         ; 0           ; Untyped                       ;
; C1_PH                         ; 0           ; Untyped                       ;
; C2_PH                         ; 0           ; Untyped                       ;
; C3_PH                         ; 0           ; Untyped                       ;
; C4_PH                         ; 0           ; Untyped                       ;
; C5_PH                         ; 0           ; Untyped                       ;
; L0_HIGH                       ; 1           ; Untyped                       ;
; L1_HIGH                       ; 1           ; Untyped                       ;
; G0_HIGH                       ; 1           ; Untyped                       ;
; G1_HIGH                       ; 1           ; Untyped                       ;
; G2_HIGH                       ; 1           ; Untyped                       ;
; G3_HIGH                       ; 1           ; Untyped                       ;
; E0_HIGH                       ; 1           ; Untyped                       ;
; E1_HIGH                       ; 1           ; Untyped                       ;
; E2_HIGH                       ; 1           ; Untyped                       ;
; E3_HIGH                       ; 1           ; Untyped                       ;
; L0_LOW                        ; 1           ; Untyped                       ;
; L1_LOW                        ; 1           ; Untyped                       ;
; G0_LOW                        ; 1           ; Untyped                       ;
; G1_LOW                        ; 1           ; Untyped                       ;
; G2_LOW                        ; 1           ; Untyped                       ;
; G3_LOW                        ; 1           ; Untyped                       ;
; E0_LOW                        ; 1           ; Untyped                       ;
; E1_LOW                        ; 1           ; Untyped                       ;
; E2_LOW                        ; 1           ; Untyped                       ;
; E3_LOW                        ; 1           ; Untyped                       ;
; L0_INITIAL                    ; 1           ; Untyped                       ;
; L1_INITIAL                    ; 1           ; Untyped                       ;
; G0_INITIAL                    ; 1           ; Untyped                       ;
; G1_INITIAL                    ; 1           ; Untyped                       ;
; G2_INITIAL                    ; 1           ; Untyped                       ;
; G3_INITIAL                    ; 1           ; Untyped                       ;
; E0_INITIAL                    ; 1           ; Untyped                       ;
; E1_INITIAL                    ; 1           ; Untyped                       ;
; E2_INITIAL                    ; 1           ; Untyped                       ;
; E3_INITIAL                    ; 1           ; Untyped                       ;
; L0_MODE                       ; BYPASS      ; Untyped                       ;
; L1_MODE                       ; BYPASS      ; Untyped                       ;
; G0_MODE                       ; BYPASS      ; Untyped                       ;
; G1_MODE                       ; BYPASS      ; Untyped                       ;
; G2_MODE                       ; BYPASS      ; Untyped                       ;
; G3_MODE                       ; BYPASS      ; Untyped                       ;
; E0_MODE                       ; BYPASS      ; Untyped                       ;
; E1_MODE                       ; BYPASS      ; Untyped                       ;
; E2_MODE                       ; BYPASS      ; Untyped                       ;
; E3_MODE                       ; BYPASS      ; Untyped                       ;
; L0_PH                         ; 0           ; Untyped                       ;
; L1_PH                         ; 0           ; Untyped                       ;
; G0_PH                         ; 0           ; Untyped                       ;
; G1_PH                         ; 0           ; Untyped                       ;
; G2_PH                         ; 0           ; Untyped                       ;
; G3_PH                         ; 0           ; Untyped                       ;
; E0_PH                         ; 0           ; Untyped                       ;
; E1_PH                         ; 0           ; Untyped                       ;
; E2_PH                         ; 0           ; Untyped                       ;
; E3_PH                         ; 0           ; Untyped                       ;
; M_PH                          ; 0           ; Untyped                       ;
; C1_USE_CASC_IN                ; 0           ; Untyped                       ;
; C2_USE_CASC_IN                ; 0           ; Untyped                       ;
; C3_USE_CASC_IN                ; 0           ; Untyped                       ;
; C4_USE_CASC_IN                ; 0           ; Untyped                       ;
; C5_USE_CASC_IN                ; 0           ; Untyped                       ;
; CLK0_COUNTER                  ; G0          ; Untyped                       ;
; CLK1_COUNTER                  ; G0          ; Untyped                       ;
; CLK2_COUNTER                  ; G0          ; Untyped                       ;
; CLK3_COUNTER                  ; G0          ; Untyped                       ;
; CLK4_COUNTER                  ; G0          ; Untyped                       ;
; CLK5_COUNTER                  ; G0          ; Untyped                       ;
; L0_TIME_DELAY                 ; 0           ; Untyped                       ;
; L1_TIME_DELAY                 ; 0           ; Untyped                       ;
; G0_TIME_DELAY                 ; 0           ; Untyped                       ;
; G1_TIME_DELAY                 ; 0           ; Untyped                       ;
; G2_TIME_DELAY                 ; 0           ; Untyped                       ;
; G3_TIME_DELAY                 ; 0           ; Untyped                       ;
; E0_TIME_DELAY                 ; 0           ; Untyped                       ;
; E1_TIME_DELAY                 ; 0           ; Untyped                       ;
; E2_TIME_DELAY                 ; 0           ; Untyped                       ;
; E3_TIME_DELAY                 ; 0           ; Untyped                       ;
; M_TIME_DELAY                  ; 0           ; Untyped                       ;
; N_TIME_DELAY                  ; 0           ; Untyped                       ;
; EXTCLK3_COUNTER               ; E3          ; Untyped                       ;
; EXTCLK2_COUNTER               ; E2          ; Untyped                       ;
; EXTCLK1_COUNTER               ; E1          ; Untyped                       ;
; EXTCLK0_COUNTER               ; E0          ; Untyped                       ;
; ENABLE0_COUNTER               ; L0          ; Untyped                       ;
; ENABLE1_COUNTER               ; L0          ; Untyped                       ;
; CHARGE_PUMP_CURRENT           ; 2           ; Untyped                       ;
; LOOP_FILTER_R                 ;  1.000000   ; Untyped                       ;
; LOOP_FILTER_C                 ; 5           ; Untyped                       ;
; VCO_POST_SCALE                ; 0           ; Untyped                       ;
; CLK2_OUTPUT_FREQUENCY         ; 0           ; Untyped                       ;
; CLK1_OUTPUT_FREQUENCY         ; 0           ; Untyped                       ;
; CLK0_OUTPUT_FREQUENCY         ; 0           ; Untyped                       ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II  ; Untyped                       ;
; PORT_CLKENA0                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKENA1                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKENA2                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKENA3                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKENA4                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKENA5                  ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLKENA0               ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLKENA1               ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLKENA2               ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLKENA3               ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLK0                  ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLK1                  ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLK2                  ; PORT_UNUSED ; Untyped                       ;
; PORT_EXTCLK3                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKBAD0                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKBAD1                  ; PORT_UNUSED ; Untyped                       ;
; PORT_CLK0                     ; PORT_USED   ; Untyped                       ;
; PORT_CLK1                     ; PORT_UNUSED ; Untyped                       ;
; PORT_CLK2                     ; PORT_UNUSED ; Untyped                       ;
; PORT_CLK3                     ; PORT_UNUSED ; Untyped                       ;
; PORT_CLK4                     ; PORT_UNUSED ; Untyped                       ;
; PORT_CLK5                     ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANDATA                 ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANDATAOUT              ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANDONE                 ; PORT_UNUSED ; Untyped                       ;
; PORT_SCLKOUT1                 ; PORT_UNUSED ; Untyped                       ;
; PORT_SCLKOUT0                 ; PORT_UNUSED ; Untyped                       ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKLOSS                  ; PORT_UNUSED ; Untyped                       ;
; PORT_INCLK1                   ; PORT_UNUSED ; Untyped                       ;
; PORT_INCLK0                   ; PORT_USED   ; Untyped                       ;
; PORT_FBIN                     ; PORT_UNUSED ; Untyped                       ;
; PORT_PLLENA                   ; PORT_UNUSED ; Untyped                       ;
; PORT_CLKSWITCH                ; PORT_UNUSED ; Untyped                       ;
; PORT_ARESET                   ; PORT_UNUSED ; Untyped                       ;
; PORT_PFDENA                   ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANCLK                  ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANACLR                 ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANREAD                 ; PORT_UNUSED ; Untyped                       ;
; PORT_SCANWRITE                ; PORT_UNUSED ; Untyped                       ;
; PORT_ENABLE0                  ; PORT_UNUSED ; Untyped                       ;
; PORT_ENABLE1                  ; PORT_UNUSED ; Untyped                       ;
; PORT_LOCKED                   ; PORT_UNUSED ; Untyped                       ;
; M_TEST_SOURCE                 ; 5           ; Untyped                       ;
; C0_TEST_SOURCE                ; 5           ; Untyped                       ;
; C1_TEST_SOURCE                ; 5           ; Untyped                       ;
; C2_TEST_SOURCE                ; 5           ; Untyped                       ;
; C3_TEST_SOURCE                ; 5           ; Untyped                       ;
; C4_TEST_SOURCE                ; 5           ; Untyped                       ;
; C5_TEST_SOURCE                ; 5           ; Untyped                       ;
; DEVICE_FAMILY                 ; Cyclone II  ; Untyped                       ;
; AUTO_CARRY_CHAINS             ; ON          ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS          ; OFF         ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS           ; ON          ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS        ; OFF         ; IGNORE_CASCADE                ;
+-------------------------------+-------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u1 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; CLK_Freq       ; 50000000 ; Integer                           ;
; I2C_Freq       ; 20000    ; Integer                           ;
; LUT_SIZE       ; 11       ; Integer                           ;
; Dummy_DATA     ; 0        ; Integer                           ;
; SET_LIN_L      ; 1        ; Integer                           ;
; SET_LIN_R      ; 2        ; Integer                           ;
; SET_HEAD_L     ; 3        ; Integer                           ;
; SET_HEAD_R     ; 4        ; Integer                           ;
; A_PATH_CTRL    ; 5        ; Integer                           ;
; D_PATH_CTRL    ; 6        ; Integer                           ;
; POWER_ON       ; 7        ; Integer                           ;
; SET_FORMAT     ; 8        ; Integer                           ;
; SAMPLE_CTRL    ; 9        ; Integer                           ;
; SET_ACTIVE     ; 10       ; Integer                           ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Sep 28 19:54:57 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE1_i2sound -c DE1_i2sound
Info: Found 1 design units, including 1 entities, in source file DE1_i2sound.v
    Info: Found entity 1: DE1_i2sound
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file PLL.v
    Info: Found entity 1: PLL
Info: Elaborating entity "DE1_i2sound" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at DE1_i2sound.v(247): truncated value with size 32 to match size of target (7)
Warning (10034): Output port "UART_TXD" at DE1_i2sound.v(145) has no driver
Warning (10034): Output port "DRAM_ADDR[11]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[10]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[9]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[8]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[7]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[6]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[5]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[4]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[3]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[2]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[1]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_ADDR[0]" at DE1_i2sound.v(149) has no driver
Warning (10034): Output port "DRAM_LDQM" at DE1_i2sound.v(150) has no driver
Warning (10034): Output port "DRAM_UDQM" at DE1_i2sound.v(151) has no driver
Warning (10034): Output port "DRAM_WE_N" at DE1_i2sound.v(152) has no driver
Warning (10034): Output port "DRAM_CAS_N" at DE1_i2sound.v(153) has no driver
Warning (10034): Output port "DRAM_RAS_N" at DE1_i2sound.v(154) has no driver
Warning (10034): Output port "DRAM_CS_N" at DE1_i2sound.v(155) has no driver
Warning (10034): Output port "DRAM_BA_0" at DE1_i2sound.v(156) has no driver
Warning (10034): Output port "DRAM_BA_1" at DE1_i2sound.v(157) has no driver
Warning (10034): Output port "DRAM_CLK" at DE1_i2sound.v(158) has no driver
Warning (10034): Output port "DRAM_CKE" at DE1_i2sound.v(159) has no driver
Warning (10034): Output port "FL_ADDR[21]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[20]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[19]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[18]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[17]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[16]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[15]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[14]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[13]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[12]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[11]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[10]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[9]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[8]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[7]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[6]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[5]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[4]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[3]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[2]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[1]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_ADDR[0]" at DE1_i2sound.v(162) has no driver
Warning (10034): Output port "FL_WE_N" at DE1_i2sound.v(163) has no driver
Warning (10034): Output port "FL_RST_N" at DE1_i2sound.v(164) has no driver
Warning (10034): Output port "FL_OE_N" at DE1_i2sound.v(165) has no driver
Warning (10034): Output port "FL_CE_N" at DE1_i2sound.v(166) has no driver
Warning (10034): Output port "SRAM_ADDR[17]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[16]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[15]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[14]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[13]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[12]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[11]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[10]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[9]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[8]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[7]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[6]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[5]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[4]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[3]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[2]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[1]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_ADDR[0]" at DE1_i2sound.v(169) has no driver
Warning (10034): Output port "SRAM_UB_N" at DE1_i2sound.v(170) has no driver
Warning (10034): Output port "SRAM_LB_N" at DE1_i2sound.v(171) has no driver
Warning (10034): Output port "SRAM_WE_N" at DE1_i2sound.v(172) has no driver
Warning (10034): Output port "SRAM_CE_N" at DE1_i2sound.v(173) has no driver
Warning (10034): Output port "SRAM_OE_N" at DE1_i2sound.v(174) has no driver
Warning (10034): Output port "SD_CLK" at DE1_i2sound.v(179) has no driver
Warning (10034): Output port "TDO" at DE1_i2sound.v(190) has no driver
Warning (10034): Output port "VGA_HS" at DE1_i2sound.v(192) has no driver
Warning (10034): Output port "VGA_VS" at DE1_i2sound.v(193) has no driver
Warning (10034): Output port "VGA_R[3]" at DE1_i2sound.v(194) has no driver
Warning (10034): Output port "VGA_R[2]" at DE1_i2sound.v(194) has no driver
Warning (10034): Output port "VGA_R[1]" at DE1_i2sound.v(194) has no driver
Warning (10034): Output port "VGA_R[0]" at DE1_i2sound.v(194) has no driver
Warning (10034): Output port "VGA_G[3]" at DE1_i2sound.v(195) has no driver
Warning (10034): Output port "VGA_G[2]" at DE1_i2sound.v(195) has no driver
Warning (10034): Output port "VGA_G[1]" at DE1_i2sound.v(195) has no driver
Warning (10034): Output port "VGA_G[0]" at DE1_i2sound.v(195) has no driver
Warning (10034): Output port "VGA_B[3]" at DE1_i2sound.v(196) has no driver
Warning (10034): Output port "VGA_B[2]" at DE1_i2sound.v(196) has no driver
Warning (10034): Output port "VGA_B[1]" at DE1_i2sound.v(196) has no driver
Warning (10034): Output port "VGA_B[0]" at DE1_i2sound.v(196) has no driver
Warning (10034): Output port "AUD_DACDAT" at DE1_i2sound.v(201) has no driver
Info: Elaborating entity "PLL" for hierarchy "PLL:u0"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "PLL:u0|altpll:altpll_component"
Info: Elaborated megafunction instantiation "PLL:u0|altpll:altpll_component"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u1"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(103): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u1|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[22]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u1|mI2C_DATA[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_AV_Config:u1|mI2C_DATA[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[20]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u1|mI2C_DATA[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[18]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u1|I2C_Controller:u0|SD[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_AV_Config:u1|I2C_Controller:u0|SD[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[20]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u1|I2C_Controller:u0|SD[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[18]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[8]" with stuck data_in port to stuck value GND
Info: State machine "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST"
Info: Encoding result for state machine "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.00"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.10"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.01"
    Info: State "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST.00" uses code string "000"
    Info: State "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST.01" uses code string "101"
    Info: State "|DE1_i2sound|I2C_AV_Config:u1|mSetup_ST.10" uses code string "110"
Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_ADCLRCK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_BCLK" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_DACLRCK~1 that it feeds
Warning: Removed fan-in from always-disabled I/O buffer I2C_SDAT~4 to tri-state bus I2C_SDAT~1
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "AUD_DACLRCK~2"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "HEX0[0]" stuck at GND
    Warning: Pin "HEX0[1]" stuck at GND
    Warning: Pin "HEX0[2]" stuck at GND
    Warning: Pin "HEX0[3]" stuck at GND
    Warning: Pin "HEX0[4]" stuck at GND
    Warning: Pin "HEX0[5]" stuck at GND
    Warning: Pin "HEX0[6]" stuck at GND
    Warning: Pin "HEX1[0]" stuck at GND
    Warning: Pin "HEX1[1]" stuck at GND
    Warning: Pin "HEX1[2]" stuck at GND
    Warning: Pin "HEX1[3]" stuck at GND
    Warning: Pin "HEX1[4]" stuck at GND
    Warning: Pin "HEX1[5]" stuck at GND
    Warning: Pin "HEX1[6]" stuck at GND
    Warning: Pin "HEX2[0]" stuck at GND
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at GND
    Warning: Pin "HEX2[4]" stuck at GND
    Warning: Pin "HEX2[5]" stuck at GND
    Warning: Pin "HEX2[6]" stuck at GND
    Warning: Pin "HEX3[0]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at GND
    Warning: Pin "HEX3[4]" stuck at GND
    Warning: Pin "HEX3[5]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "LEDR[0]" stuck at VCC
    Warning: Pin "LEDR[1]" stuck at VCC
    Warning: Pin "LEDR[2]" stuck at VCC
    Warning: Pin "LEDR[3]" stuck at VCC
    Warning: Pin "LEDR[4]" stuck at VCC
    Warning: Pin "LEDR[5]" stuck at VCC
    Warning: Pin "LEDR[6]" stuck at VCC
    Warning: Pin "LEDR[7]" stuck at VCC
    Warning: Pin "LEDR[8]" stuck at VCC
    Warning: Pin "LEDR[9]" stuck at VCC
    Warning: Pin "UART_TXD" stuck at GND
    Warning: Pin "DRAM_ADDR[0]" stuck at GND
    Warning: Pin "DRAM_ADDR[1]" stuck at GND
    Warning: Pin "DRAM_ADDR[2]" stuck at GND
    Warning: Pin "DRAM_ADDR[3]" stuck at GND
    Warning: Pin "DRAM_ADDR[4]" stuck at GND
    Warning: Pin "DRAM_ADDR[5]" stuck at GND
    Warning: Pin "DRAM_ADDR[6]" stuck at GND
    Warning: Pin "DRAM_ADDR[7]" stuck at GND
    Warning: Pin "DRAM_ADDR[8]" stuck at GND
    Warning: Pin "DRAM_ADDR[9]" stuck at GND
    Warning: Pin "DRAM_ADDR[10]" stuck at GND
    Warning: Pin "DRAM_ADDR[11]" stuck at GND
    Warning: Pin "DRAM_LDQM" stuck at GND
    Warning: Pin "DRAM_UDQM" stuck at GND
    Warning: Pin "DRAM_WE_N" stuck at GND
    Warning: Pin "DRAM_CAS_N" stuck at GND
    Warning: Pin "DRAM_RAS_N" stuck at GND
    Warning: Pin "DRAM_CS_N" stuck at GND
    Warning: Pin "DRAM_BA_0" stuck at GND
    Warning: Pin "DRAM_BA_1" stuck at GND
    Warning: Pin "DRAM_CLK" stuck at GND
    Warning: Pin "DRAM_CKE" stuck at GND
    Warning: Pin "FL_ADDR[0]" stuck at GND
    Warning: Pin "FL_ADDR[1]" stuck at GND
    Warning: Pin "FL_ADDR[2]" stuck at GND
    Warning: Pin "FL_ADDR[3]" stuck at GND
    Warning: Pin "FL_ADDR[4]" stuck at GND
    Warning: Pin "FL_ADDR[5]" stuck at GND
    Warning: Pin "FL_ADDR[6]" stuck at GND
    Warning: Pin "FL_ADDR[7]" stuck at GND
    Warning: Pin "FL_ADDR[8]" stuck at GND
    Warning: Pin "FL_ADDR[9]" stuck at GND
    Warning: Pin "FL_ADDR[10]" stuck at GND
    Warning: Pin "FL_ADDR[11]" stuck at GND
    Warning: Pin "FL_ADDR[12]" stuck at GND
    Warning: Pin "FL_ADDR[13]" stuck at GND
    Warning: Pin "FL_ADDR[14]" stuck at GND
    Warning: Pin "FL_ADDR[15]" stuck at GND
    Warning: Pin "FL_ADDR[16]" stuck at GND
    Warning: Pin "FL_ADDR[17]" stuck at GND
    Warning: Pin "FL_ADDR[18]" stuck at GND
    Warning: Pin "FL_ADDR[19]" stuck at GND
    Warning: Pin "FL_ADDR[20]" stuck at GND
    Warning: Pin "FL_ADDR[21]" stuck at GND
    Warning: Pin "FL_WE_N" stuck at GND
    Warning: Pin "FL_RST_N" stuck at GND
    Warning: Pin "FL_OE_N" stuck at GND
    Warning: Pin "FL_CE_N" stuck at GND
    Warning: Pin "SRAM_ADDR[0]" stuck at GND
    Warning: Pin "SRAM_ADDR[1]" stuck at GND
    Warning: Pin "SRAM_ADDR[2]" stuck at GND
    Warning: Pin "SRAM_ADDR[3]" stuck at GND
    Warning: Pin "SRAM_ADDR[4]" stuck at GND
    Warning: Pin "SRAM_ADDR[5]" stuck at GND
    Warning: Pin "SRAM_ADDR[6]" stuck at GND
    Warning: Pin "SRAM_ADDR[7]" stuck at GND
    Warning: Pin "SRAM_ADDR[8]" stuck at GND
    Warning: Pin "SRAM_ADDR[9]" stuck at GND
    Warning: Pin "SRAM_ADDR[10]" stuck at GND
    Warning: Pin "SRAM_ADDR[11]" stuck at GND
    Warning: Pin "SRAM_ADDR[12]" stuck at GND
    Warning: Pin "SRAM_ADDR[13]" stuck at GND
    Warning: Pin "SRAM_ADDR[14]" stuck at GND
    Warning: Pin "SRAM_ADDR[15]" stuck at GND
    Warning: Pin "SRAM_ADDR[16]" stuck at GND
    Warning: Pin "SRAM_ADDR[17]" stuck at GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_WE_N" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SRAM_OE_N" stuck at GND
    Warning: Pin "SD_CLK" stuck at GND
    Warning: Pin "TDO" stuck at GND
    Warning: Pin "VGA_HS" stuck at GND
    Warning: Pin "VGA_VS" stuck at GND
    Warning: Pin "VGA_R[0]" stuck at GND
    Warning: Pin "VGA_R[1]" stuck at GND
    Warning: Pin "VGA_R[2]" stuck at GND
    Warning: Pin "VGA_R[3]" stuck at GND
    Warning: Pin "VGA_G[0]" stuck at GND
    Warning: Pin "VGA_G[1]" stuck at GND
    Warning: Pin "VGA_G[2]" stuck at GND
    Warning: Pin "VGA_G[3]" stuck at GND
    Warning: Pin "VGA_B[0]" stuck at GND
    Warning: Pin "VGA_B[1]" stuck at GND
    Warning: Pin "VGA_B[2]" stuck at GND
    Warning: Pin "VGA_B[3]" stuck at GND
    Warning: Pin "AUD_DACDAT" stuck at GND
Warning: Design contains 23 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLOCK_24[0]"
    Warning: No output dependent on input pin "CLOCK_24[1]"
    Warning: No output dependent on input pin "CLOCK_27[1]"
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
    Warning: No output dependent on input pin "SW[0]"
    Warning: No output dependent on input pin "SW[1]"
    Warning: No output dependent on input pin "SW[2]"
    Warning: No output dependent on input pin "SW[3]"
    Warning: No output dependent on input pin "SW[4]"
    Warning: No output dependent on input pin "SW[5]"
    Warning: No output dependent on input pin "SW[6]"
    Warning: No output dependent on input pin "SW[7]"
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "UART_RXD"
    Warning: No output dependent on input pin "TDI"
    Warning: No output dependent on input pin "TCK"
    Warning: No output dependent on input pin "TCS"
    Warning: No output dependent on input pin "PS2_DAT"
    Warning: No output dependent on input pin "PS2_CLK"
Info: Implemented 402 device resources after synthesis - the final resource count might be different
    Info: Implemented 27 input pins
    Info: Implemented 137 output pins
    Info: Implemented 119 bidirectional pins
    Info: Implemented 118 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 278 warnings
    Info: Processing ended: Thu Sep 28 19:55:00 2006
    Info: Elapsed time: 00:00:03


