Analysis & Synthesis report for DE1_USB_API
Wed Sep 13 15:43:10 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |DE1_USB_API|I2C_AV_Config:u10|mSetup_ST
  9. State Machine - |DE1_USB_API|CMD_Decode:u5|mFL_ST
 10. State Machine - |DE1_USB_API|CMD_Decode:u5|mPS2_ST
 11. State Machine - |DE1_USB_API|CMD_Decode:u5|mSDR_ST
 12. State Machine - |DE1_USB_API|CMD_Decode:u5|mSR_ST
 13. State Machine - |DE1_USB_API|ps2_keyboard:u4|m1_state
 14. State Machine - |DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST
 15. State Machine - |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST
 16. State Machine - |DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST
 17. General Register Statistics
 18. Inverted Register Statistics
 19. Multiplexer Restructuring Statistics (Restructuring Performed)
 20. Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated
 21. Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1
 22. Parameter Settings for User Entity Instance: Multi_Flash:u2|Flash_Controller:u1
 23. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1
 24. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component
 25. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1
 26. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|command:command1
 27. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1
 28. Parameter Settings for User Entity Instance: ps2_keyboard:u4
 29. Parameter Settings for User Entity Instance: CMD_Decode:u5
 30. Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component
 31. Parameter Settings for User Entity Instance: VGA_Controller:u8
 32. Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9
 33. Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component
 34. Parameter Settings for User Entity Instance: I2C_AV_Config:u10
 35. Parameter Settings for User Entity Instance: AUDIO_DAC:u11
 36. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Sep 13 15:43:10 2006         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE1_USB_API                                   ;
; Top-level Entity Name              ; DE1_USB_API                                   ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 1881                                          ;
; Total registers                    ; 1005                                          ;
; Total pins                         ; 283                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 208,000                                       ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 2                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C20F484C7       ;                    ;
; Top-level entity name                                              ; DE1_USB_API        ; DE1_USB_API        ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                      ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; VGA_Controller/Img_RAM.v         ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/VGA_Controller/Img_RAM.v               ;
; VGA_Controller/VGA_OSD_RAM.v     ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/VGA_Controller/VGA_OSD_RAM.v           ;
; VGA_Controller/VGA_Controller.v  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/VGA_Controller/VGA_Controller.v        ;
; Multi_Sdram/command.v            ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/command.v                  ;
; Multi_Sdram/control_interface.v  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/control_interface.v        ;
; Multi_Sdram/Multi_Sdram.v        ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/Multi_Sdram.v              ;
; Multi_Sdram/PLL1.v               ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/PLL1.v                     ;
; Multi_Sdram/sdr_data_path.v      ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/sdr_data_path.v            ;
; Multi_Sdram/Sdram_Controller.v   ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/Sdram_Controller.v         ;
; Multi_Sdram/Sdram_Multiplexer.v  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/Sdram_Multiplexer.v        ;
; Multi_Flash/Flash_Controller.v   ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Flash/Flash_Controller.v         ;
; Multi_Flash/Flash_Multiplexer.v  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Flash/Flash_Multiplexer.v        ;
; Multi_Flash/Multi_Flash.v        ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Flash/Multi_Flash.v              ;
; AUDIO_DAC.v                      ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/AUDIO_DAC.v                            ;
; CLK_LOCK.v                       ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/CLK_LOCK.v                             ;
; CMD_Decode.v                     ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/CMD_Decode.v                           ;
; DE1_USB_API.v                    ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/DE1_USB_API.v                          ;
; Flash_Command.h                  ; yes             ; User File                    ; C:/DE1/DE1_USB_API_v1_0/HW/Flash_Command.h                        ;
; I2C_AV_Config.v                  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/I2C_AV_Config.v                        ;
; I2C_Controller.v                 ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/I2C_Controller.v                       ;
; Multi_Sram.v                     ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sram.v                           ;
; ps2_keyboard.v                   ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/ps2_keyboard.v                         ;
; Reset_Delay.v                    ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/Reset_Delay.v                          ;
; RS232_Command.h                  ; yes             ; User File                    ; C:/DE1/DE1_USB_API_v1_0/HW/RS232_Command.h                        ;
; SEG7_LUT.v                       ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/SEG7_LUT.v                             ;
; USB_JTAG.v                       ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/USB_JTAG.v                             ;
; VGA_Audio_PLL.v                  ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/VGA_Audio_PLL.v                        ;
; SEG7_LUT_4.v                     ; yes             ; User Verilog HDL File        ; C:/DE1/DE1_USB_API_v1_0/HW/SEG7_LUT_4.v                           ;
; Multi_Sdram/Sdram_Params.h       ; yes             ; Other                        ; C:/DE1/DE1_USB_API_v1_0/HW/Multi_Sdram/Sdram_Params.h             ;
; VGA_Controller/VGA_Param.h       ; yes             ; Other                        ; C:/DE1/DE1_USB_API_v1_0/HW/VGA_Controller/VGA_Param.h             ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf            ;
; aglobal60.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc         ;
; stratix_pll.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc     ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc        ;
; altsyncram.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_f7o1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/DE1/DE1_USB_API_v1_0/HW/db/altsyncram_f7o1.tdf                 ;
; db/altsyncram_e132.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/DE1/DE1_USB_API_v1_0/HW/db/altsyncram_e132.tdf                 ;
; db/decode_qpa.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/DE1/DE1_USB_API_v1_0/HW/db/decode_qpa.tdf                      ;
; db/mux_akb.tdf                   ; yes             ; Auto-Generated Megafunction  ; C:/DE1/DE1_USB_API_v1_0/HW/db/mux_akb.tdf                         ;
; db/mux_3kb.tdf                   ; yes             ; Auto-Generated Megafunction  ; C:/DE1/DE1_USB_API_v1_0/HW/db/mux_3kb.tdf                         ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Estimated Total logic elements              ; 1,881    ;
; Total combinational functions               ; 1881     ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 1024     ;
;     -- 3 input functions                    ; 369      ;
;     -- <=2 input functions                  ; 488      ;
;         -- Combinational cells for routing  ; 0        ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 1528     ;
;     -- arithmetic mode                      ; 353      ;
; Total registers                             ; 1005     ;
; I/O pins                                    ; 283      ;
; Total memory bits                           ; 208000   ;
; Total PLLs                                  ; 2        ;
; Maximum fan-out node                        ; CLOCK_50 ;
; Maximum fan-out                             ; 560      ;
; Total fan-out                               ; 10435    ;
; Average fan-out                             ; 3.24     ;
+---------------------------------------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                          ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                        ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                   ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DE1_USB_API                                                      ; 1881 (6)          ; 1005 (0)     ; 208000      ; 51   ; 0            ; 0       ; 0         ; 283  ; 0            ; |DE1_USB_API                                                                                                                                          ;
;    |AUDIO_DAC:u11|                                                ; 172 (172)         ; 95 (95)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|AUDIO_DAC:u11                                                                                                                            ;
;    |CLK_LOCK:p0|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|CLK_LOCK:p0                                                                                                                              ;
;       |CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component| ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component                                                                    ;
;    |CMD_Decode:u5|                                                ; 167 (167)         ; 316 (316)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|CMD_Decode:u5                                                                                                                            ;
;    |I2C_AV_Config:u10|                                            ; 86 (44)           ; 57 (35)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|I2C_AV_Config:u10                                                                                                                        ;
;       |I2C_Controller:u0|                                         ; 42 (42)           ; 22 (22)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|I2C_AV_Config:u10|I2C_Controller:u0                                                                                                      ;
;    |Multi_Flash:u2|                                               ; 168 (0)           ; 112 (0)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Flash:u2                                                                                                                           ;
;       |Flash_Controller:u1|                                       ; 110 (110)         ; 99 (99)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1                                                                                                       ;
;       |Flash_Multiplexer:u0|                                      ; 58 (58)           ; 13 (13)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0                                                                                                      ;
;    |Multi_Sdram:u3|                                               ; 231 (0)           ; 217 (0)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3                                                                                                                           ;
;       |Sdram_Controller:u1|                                       ; 184 (60)          ; 212 (70)     ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1                                                                                                       ;
;          |PLL1:sdram_pll1|                                        ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1                                                                                       ;
;             |altpll:altpll_component|                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component                                                               ;
;          |command:command1|                                       ; 61 (61)           ; 48 (48)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1                                                                                      ;
;          |control_interface:control1|                             ; 63 (63)           ; 62 (62)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1                                                                            ;
;          |sdr_data_path:data_path1|                               ; 0 (0)             ; 32 (32)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1                                                                              ;
;       |Sdram_Multiplexer:u0|                                      ; 47 (47)           ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0                                                                                                      ;
;    |Multi_Sram:u6|                                                ; 38 (38)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Multi_Sram:u6                                                                                                                            ;
;    |Reset_Delay:d0|                                               ; 28 (28)           ; 21 (21)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|Reset_Delay:d0                                                                                                                           ;
;    |SEG7_LUT_4:u0|                                                ; 28 (0)            ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|SEG7_LUT_4:u0                                                                                                                            ;
;       |SEG7_LUT:u0|                                               ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u0                                                                                                                ;
;       |SEG7_LUT:u1|                                               ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u1                                                                                                                ;
;       |SEG7_LUT:u2|                                               ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u2                                                                                                                ;
;       |SEG7_LUT:u3|                                               ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u3                                                                                                                ;
;    |USB_JTAG:u1|                                                  ; 17 (3)            ; 37 (13)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|USB_JTAG:u1                                                                                                                              ;
;       |JTAG_REC:u0|                                               ; 5 (5)             ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|USB_JTAG:u1|JTAG_REC:u0                                                                                                                  ;
;       |JTAG_TRANS:u1|                                             ; 9 (9)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|USB_JTAG:u1|JTAG_TRANS:u1                                                                                                                ;
;    |VGA_Audio_PLL:p1|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_Audio_PLL:p1                                                                                                                         ;
;       |altpll:altpll_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_Audio_PLL:p1|altpll:altpll_component                                                                                                 ;
;    |VGA_Controller:u8|                                            ; 237 (237)         ; 73 (73)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_Controller:u8                                                                                                                        ;
;    |VGA_OSD_RAM:u9|                                               ; 435 (74)          ; 20 (8)       ; 208000      ; 51   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9                                                                                                                           ;
;       |Img_RAM:u0|                                                ; 361 (0)           ; 12 (0)       ; 208000      ; 51   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0                                                                                                                ;
;          |altsyncram:altsyncram_component|                        ; 361 (0)           ; 12 (0)       ; 208000      ; 51   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component                                                                                ;
;             |altsyncram_f7o1:auto_generated|                      ; 361 (0)           ; 12 (0)       ; 208000      ; 51   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated                                                 ;
;                |altsyncram_e132:altsyncram1|                      ; 361 (0)           ; 12 (12)      ; 208000      ; 51   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1                     ;
;                   |decode_qpa:decode_a|                           ; 61 (61)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a ;
;                   |mux_akb:mux5|                                  ; 300 (300)         ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_akb:mux5        ;
;    |ps2_keyboard:u4|                                              ; 268 (268)         ; 57 (57)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE1_USB_API|ps2_keyboard:u4                                                                                                                          ;
+-------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+
; Name                                                                                                                            ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF          ;
+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+
; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ALTSYNCRAM ; M4K  ; True Dual Port ; 26000        ; 8            ; 208000       ; 1            ; 208000 ; Img_DATA.hex ;
+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+


+-----------------------------------------------------------+
; State Machine - |DE1_USB_API|I2C_AV_Config:u10|mSetup_ST  ;
+--------------+--------------+--------------+--------------+
; Name         ; mSetup_ST.00 ; mSetup_ST.10 ; mSetup_ST.01 ;
+--------------+--------------+--------------+--------------+
; mSetup_ST.00 ; 0            ; 0            ; 0            ;
; mSetup_ST.01 ; 1            ; 0            ; 1            ;
; mSetup_ST.10 ; 1            ; 1            ; 0            ;
+--------------+--------------+--------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE1_USB_API|CMD_Decode:u5|mFL_ST                                                                  ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; Name       ; mFL_ST.111 ; mFL_ST.001 ; mFL_ST.010 ; mFL_ST.011 ; mFL_ST.100 ; mFL_ST.101 ; mFL_ST.110 ; mFL_ST.000 ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; mFL_ST.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ;
; mFL_ST.110 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 1          ;
; mFL_ST.101 ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 1          ;
; mFL_ST.100 ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 1          ;
; mFL_ST.011 ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 1          ;
; mFL_ST.010 ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; mFL_ST.001 ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; mFL_ST.111 ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+


+----------------------------------------------------+
; State Machine - |DE1_USB_API|CMD_Decode:u5|mPS2_ST ;
+-------------+--------------------------------------+
; Name        ; mPS2_ST.001                          ;
+-------------+--------------------------------------+
; mPS2_ST.000 ; 0                                    ;
; mPS2_ST.001 ; 1                                    ;
+-------------+--------------------------------------+


+-------------------------------------------------------------------------------------------------+
; State Machine - |DE1_USB_API|CMD_Decode:u5|mSDR_ST                                              ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; mSDR_ST.101 ; mSDR_ST.001 ; mSDR_ST.010 ; mSDR_ST.011 ; mSDR_ST.100 ; mSDR_ST.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; mSDR_ST.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; mSDR_ST.100 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; mSDR_ST.011 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; mSDR_ST.010 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; mSDR_ST.001 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; mSDR_ST.101 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


+------------------------------------------------------------------------------------------+
; State Machine - |DE1_USB_API|CMD_Decode:u5|mSR_ST                                        ;
+------------+------------+------------+------------+------------+------------+------------+
; Name       ; mSR_ST.101 ; mSR_ST.001 ; mSR_ST.010 ; mSR_ST.011 ; mSR_ST.100 ; mSR_ST.000 ;
+------------+------------+------------+------------+------------+------------+------------+
; mSR_ST.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ;
; mSR_ST.100 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1          ;
; mSR_ST.011 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1          ;
; mSR_ST.010 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1          ;
; mSR_ST.001 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1          ;
; mSR_ST.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE1_USB_API|ps2_keyboard:u4|m1_state                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------------------------+--------------------------------------+------------------------------------+-----------------------------------+----------------------+----------------------------+----------------------------+---------------------------------+---------------------------------+---------------------------+-----------------------------------+----------------------+----------------------+----------------------------------+------------------------------+----------------------+
; Name                                 ; m1_state.m1_tx_error_no_keyboard_ack ; m1_state.m1_rx_falling_edge_marker ; m1_state.m1_rx_rising_edge_marker ; m1_state.m1_rx_clk_l ; m1_state.m1_tx_reset_timer ; m1_state.m1_tx_force_clk_l ; m1_state.m1_tx_first_wait_clk_h ; m1_state.m1_tx_first_wait_clk_l ; m1_state.m1_tx_wait_clk_h ; m1_state.m1_tx_rising_edge_marker ; m1_state.m1_tx_clk_h ; m1_state.m1_tx_clk_l ; m1_state.m1_tx_wait_keyboard_ack ; m1_state.m1_tx_done_recovery ; m1_state.m1_rx_clk_h ;
+--------------------------------------+--------------------------------------+------------------------------------+-----------------------------------+----------------------+----------------------------+----------------------------+---------------------------------+---------------------------------+---------------------------+-----------------------------------+----------------------+----------------------+----------------------------------+------------------------------+----------------------+
; m1_state.m1_rx_clk_h                 ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 0                    ;
; m1_state.m1_tx_done_recovery         ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 1                            ; 1                    ;
; m1_state.m1_tx_wait_keyboard_ack     ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 1                                ; 0                            ; 1                    ;
; m1_state.m1_tx_clk_l                 ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 1                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_clk_h                 ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 1                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_rising_edge_marker    ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 1                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_wait_clk_h            ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 1                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_first_wait_clk_l      ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 1                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_first_wait_clk_h      ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 1                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_force_clk_l           ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 1                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_reset_timer           ; 0                                    ; 0                                  ; 0                                 ; 0                    ; 1                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_rx_clk_l                 ; 0                                    ; 0                                  ; 0                                 ; 1                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_rx_rising_edge_marker    ; 0                                    ; 0                                  ; 1                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_rx_falling_edge_marker   ; 0                                    ; 1                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
; m1_state.m1_tx_error_no_keyboard_ack ; 1                                    ; 0                                  ; 0                                 ; 0                    ; 0                          ; 0                          ; 0                               ; 0                               ; 0                         ; 0                                 ; 0                    ; 0                    ; 0                                ; 0                            ; 1                    ;
+--------------------------------------+--------------------------------------+------------------------------------+-----------------------------------+----------------------+----------------------------+----------------------------+---------------------------------+---------------------------------+---------------------------+-----------------------------------+----------------------+----------------------+----------------------------------+------------------------------+----------------------+


+---------------------------------------------------------------------+
; State Machine - |DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST ;
+-------+-------+-------+-------+-------------------------------------+
; Name  ; ST.11 ; ST.01 ; ST.10 ; ST.00                               ;
+-------+-------+-------+-------+-------------------------------------+
; ST.00 ; 0     ; 0     ; 0     ; 0                                   ;
; ST.10 ; 0     ; 0     ; 1     ; 1                                   ;
; ST.01 ; 0     ; 1     ; 0     ; 1                                   ;
; ST.11 ; 1     ; 0     ; 0     ; 1                                   ;
+-------+-------+-------+-------+-------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST                                                                                                       ;
+---------------+---------+-----------+----------+-------+-------+-----------+-----------+-------+-------+-------+---------------+---------------+---------------+---------+
; Name          ; ST.READ ; ST.P4_PRG ; ST.RESET ; ST.P1 ; ST.P2 ; ST.P3_PRG ; ST.P3_DEV ; ST.P3 ; ST.P4 ; ST.P5 ; ST.P6_BLK_ERA ; ST.P6_SEC_ERA ; ST.P6_CHP_ERA ; ST.IDEL ;
+---------------+---------+-----------+----------+-------+-------+-----------+-----------+-------+-------+-------+---------------+---------------+---------------+---------+
; ST.IDEL       ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 0       ;
; ST.P6_CHP_ERA ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 1             ; 1       ;
; ST.P6_SEC_ERA ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 1             ; 0             ; 1       ;
; ST.P6_BLK_ERA ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 1             ; 0             ; 0             ; 1       ;
; ST.P5         ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 1     ; 0             ; 0             ; 0             ; 1       ;
; ST.P4         ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 1     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P3         ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 1     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P3_DEV     ; 0       ; 0         ; 0        ; 0     ; 0     ; 0         ; 1         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P3_PRG     ; 0       ; 0         ; 0        ; 0     ; 0     ; 1         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P2         ; 0       ; 0         ; 0        ; 0     ; 1     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P1         ; 0       ; 0         ; 0        ; 1     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.RESET      ; 0       ; 0         ; 1        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.P4_PRG     ; 0       ; 1         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
; ST.READ       ; 1       ; 0         ; 0        ; 0     ; 0     ; 0         ; 0         ; 0     ; 0     ; 0     ; 0             ; 0             ; 0             ; 1       ;
+---------------+---------+-----------+----------+-------+-------+-----------+-----------+-------+-------+-------+---------------+---------------+---------------+---------+


+---------------------------------------------------------------------+
; State Machine - |DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST ;
+-------+-------+-------+-------+-------------------------------------+
; Name  ; ST.11 ; ST.01 ; ST.10 ; ST.00                               ;
+-------+-------+-------+-------+-------------------------------------+
; ST.00 ; 0     ; 0     ; 0     ; 0                                   ;
; ST.10 ; 0     ; 0     ; 1     ; 1                                   ;
; ST.01 ; 0     ; 1     ; 0     ; 1                                   ;
; ST.11 ; 1     ; 0     ; 0     ; 1                                   ;
+-------+-------+-------+-------+-------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1005  ;
; Number of registers using Synchronous Clear  ; 194   ;
; Number of registers using Synchronous Load   ; 35    ;
; Number of registers using Asynchronous Clear ; 646   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 570   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------+
; Inverted Register Statistics                                ;
+---------------------------------------------------+---------+
; Inverted Register                                 ; Fan out ;
+---------------------------------------------------+---------+
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0] ; 18      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2] ; 15      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3] ; 18      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1] ; 13      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4] ; 11      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5] ; 12      ;
; I2C_AV_Config:u10|I2C_Controller:u0|SCLK          ; 2       ;
; I2C_AV_Config:u10|I2C_Controller:u0|END           ; 5       ;
; I2C_AV_Config:u10|I2C_Controller:u0|SDO           ; 4       ;
; Total number of inverted registers = 9            ;         ;
+---------------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
; 3:1                ; 22 bits   ; 44 LEs        ; 44 LEs               ; 0 LEs                  ; Yes        ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|r_ADDR[17]                          ;
; 3:1                ; 11 bits   ; 22 LEs        ; 11 LEs               ; 11 LEs                 ; Yes        ; |DE1_USB_API|VGA_Controller:u8|Cur_Color_B[7]                                       ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE1_USB_API|ps2_keyboard:u4|q[2]                                                   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE1_USB_API|ps2_keyboard:u4|bit_count[0]                                           ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |DE1_USB_API|ps2_keyboard:u4|rx_ascii[2]                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[0]              ;
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[3] ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_done       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[8]              ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[5]              ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done            ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |DE1_USB_API|CMD_Decode:u5|oSR_TXD_DATA[2]                                          ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |DE1_USB_API|CMD_Decode:u5|oSDR_TXD_DATA[2]                                         ;
; 256:1              ; 3 bits    ; 510 LEs       ; 6 LEs                ; 504 LEs                ; Yes        ; |DE1_USB_API|CMD_Decode:u5|sel_SR                                                   ;
; 515:1              ; 2 bits    ; 686 LEs       ; 4 LEs                ; 682 LEs                ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|CMD[0]                              ;
; 516:1              ; 9 bits    ; 3096 LEs      ; 18 LEs               ; 3078 LEs               ; Yes        ; |DE1_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|ST[8]                               ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; No         ; |DE1_USB_API|Multi_Sram:u6|SRAM_ADDR[11]                                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~52                               ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~48                               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE1_USB_API|CMD_Decode:u5|mPS2_ST~4                                                ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|Selector31                          ;
; 5:1                ; 3 bits    ; 9 LEs         ; 9 LEs                ; 0 LEs                  ; No         ; |DE1_USB_API|mVGA_R[8]                                                              ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~57                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                            ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                             ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Flash:u2|Flash_Controller:u1 ;
+----------------+--------+-------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                  ;
+----------------+--------+-------------------------------------------------------+
; CMD_READ       ; 000    ; Binary                                                ;
; CMD_WRITE      ; 001    ; Binary                                                ;
; CMD_BLK_ERA    ; 010    ; Binary                                                ;
; CMD_SEC_ERA    ; 011    ; Binary                                                ;
; CMD_CHP_ERA    ; 100    ; Binary                                                ;
; CMD_ENTRY_ID   ; 101    ; Binary                                                ;
; CMD_RESET      ; 110    ; Binary                                                ;
; PER_READ       ; 1      ; Integer                                               ;
; PER_WRITE      ; 5      ; Integer                                               ;
; PER_BLK_ERA    ; 160000 ; Integer                                               ;
; PER_SEC_ERA    ; 160000 ; Integer                                               ;
; PER_CHP_ERA    ; 640000 ; Integer                                               ;
; PER_ENTRY_ID   ; 4      ; Integer                                               ;
; PER_RESET      ; 1      ; Integer                                               ;
; IDEL           ; 0      ; Integer                                               ;
; P1             ; 1      ; Integer                                               ;
; P2             ; 2      ; Integer                                               ;
; P3             ; 3      ; Integer                                               ;
; P4             ; 4      ; Integer                                               ;
; P5             ; 5      ; Integer                                               ;
; P3_PRG         ; 6      ; Integer                                               ;
; P3_DEV         ; 7      ; Integer                                               ;
; P4_PRG         ; 8      ; Integer                                               ;
; P6_BLK_ERA     ; 9      ; Integer                                               ;
; P6_SEC_ERA     ; 10     ; Integer                                               ;
; P6_CHP_ERA     ; 11     ; Integer                                               ;
; READ           ; 12     ; Integer                                               ;
; RESET          ; 13     ; Integer                                               ;
; CLK_Divide     ; 8      ; Integer                                               ;
+----------------+--------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1 ;
+----------------+-------+--------------------------------------------------------+
; Parameter Name ; Value ; Type                                                   ;
+----------------+-------+--------------------------------------------------------+
; INIT_PER       ; 24000 ; Integer                                                ;
; REF_PER        ; 1024  ; Integer                                                ;
; SC_CL          ; 3     ; Integer                                                ;
; SC_RCD         ; 3     ; Integer                                                ;
; SC_RRD         ; 7     ; Integer                                                ;
; SC_PM          ; 1     ; Integer                                                ;
; SC_BL          ; 1     ; Integer                                                ;
; SDR_BL         ; 111   ; Binary                                                 ;
; SDR_BT         ; 0     ; Binary                                                 ;
; SDR_CL         ; 011   ; Binary                                                 ;
+----------------+-------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component ;
+-------------------------------+-------------------+---------------------------------------------------------------------+
; Parameter Name                ; Value             ; Type                                                                ;
+-------------------------------+-------------------+---------------------------------------------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                                                             ;
; PLL_TYPE                      ; FAST              ; Untyped                                                             ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                                             ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                                             ;
; SCAN_CHAIN                    ; LONG              ; Untyped                                                             ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                                             ;
; INCLK0_INPUT_FREQUENCY        ; 20000             ; Integer                                                             ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                                             ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                                             ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                                             ;
; LOCK_HIGH                     ; 1                 ; Untyped                                                             ;
; LOCK_LOW                      ; 1                 ; Untyped                                                             ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                                             ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                                             ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                                             ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                                             ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                                             ;
; SKIP_VCO                      ; OFF               ; Untyped                                                             ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                                             ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                                             ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                                             ;
; BANDWIDTH                     ; 0                 ; Untyped                                                             ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                                             ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                                                             ;
; DOWN_SPREAD                   ; 0                 ; Untyped                                                             ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                                             ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                                             ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                                             ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                                             ;
; CLK2_MULTIPLY_BY              ; 1                 ; Integer                                                             ;
; CLK1_MULTIPLY_BY              ; 1                 ; Untyped                                                             ;
; CLK0_MULTIPLY_BY              ; 1                 ; Integer                                                             ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                                             ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                                             ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                                             ;
; CLK2_DIVIDE_BY                ; 1                 ; Integer                                                             ;
; CLK1_DIVIDE_BY                ; 1                 ; Untyped                                                             ;
; CLK0_DIVIDE_BY                ; 1                 ; Integer                                                             ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                                             ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                                                             ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                                             ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                                             ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                                             ;
; CLK2_DUTY_CYCLE               ; 50                ; Integer                                                             ;
; CLK1_DUTY_CYCLE               ; 50                ; Untyped                                                             ;
; CLK0_DUTY_CYCLE               ; 50                ; Integer                                                             ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                                             ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                                             ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                                             ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                                             ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                                             ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                                             ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                                             ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                                             ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                                             ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                                             ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                                             ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                                             ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                                             ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                                             ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                                             ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                                             ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                                             ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                                             ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                                             ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                                             ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                                             ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                                             ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                                             ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                                             ;
; VCO_MIN                       ; 0                 ; Untyped                                                             ;
; VCO_MAX                       ; 0                 ; Untyped                                                             ;
; VCO_CENTER                    ; 0                 ; Untyped                                                             ;
; PFD_MIN                       ; 0                 ; Untyped                                                             ;
; PFD_MAX                       ; 0                 ; Untyped                                                             ;
; M_INITIAL                     ; 0                 ; Untyped                                                             ;
; M                             ; 0                 ; Untyped                                                             ;
; N                             ; 1                 ; Untyped                                                             ;
; M2                            ; 1                 ; Untyped                                                             ;
; N2                            ; 1                 ; Untyped                                                             ;
; SS                            ; 1                 ; Untyped                                                             ;
; C0_HIGH                       ; 0                 ; Untyped                                                             ;
; C1_HIGH                       ; 0                 ; Untyped                                                             ;
; C2_HIGH                       ; 0                 ; Untyped                                                             ;
; C3_HIGH                       ; 0                 ; Untyped                                                             ;
; C4_HIGH                       ; 0                 ; Untyped                                                             ;
; C5_HIGH                       ; 0                 ; Untyped                                                             ;
; C0_LOW                        ; 0                 ; Untyped                                                             ;
; C1_LOW                        ; 0                 ; Untyped                                                             ;
; C2_LOW                        ; 0                 ; Untyped                                                             ;
; C3_LOW                        ; 0                 ; Untyped                                                             ;
; C4_LOW                        ; 0                 ; Untyped                                                             ;
; C5_LOW                        ; 0                 ; Untyped                                                             ;
; C0_INITIAL                    ; 0                 ; Untyped                                                             ;
; C1_INITIAL                    ; 0                 ; Untyped                                                             ;
; C2_INITIAL                    ; 0                 ; Untyped                                                             ;
; C3_INITIAL                    ; 0                 ; Untyped                                                             ;
; C4_INITIAL                    ; 0                 ; Untyped                                                             ;
; C5_INITIAL                    ; 0                 ; Untyped                                                             ;
; C0_MODE                       ; BYPASS            ; Untyped                                                             ;
; C1_MODE                       ; BYPASS            ; Untyped                                                             ;
; C2_MODE                       ; BYPASS            ; Untyped                                                             ;
; C3_MODE                       ; BYPASS            ; Untyped                                                             ;
; C4_MODE                       ; BYPASS            ; Untyped                                                             ;
; C5_MODE                       ; BYPASS            ; Untyped                                                             ;
; C0_PH                         ; 0                 ; Untyped                                                             ;
; C1_PH                         ; 0                 ; Untyped                                                             ;
; C2_PH                         ; 0                 ; Untyped                                                             ;
; C3_PH                         ; 0                 ; Untyped                                                             ;
; C4_PH                         ; 0                 ; Untyped                                                             ;
; C5_PH                         ; 0                 ; Untyped                                                             ;
; L0_HIGH                       ; 1                 ; Untyped                                                             ;
; L1_HIGH                       ; 1                 ; Untyped                                                             ;
; G0_HIGH                       ; 1                 ; Untyped                                                             ;
; G1_HIGH                       ; 1                 ; Untyped                                                             ;
; G2_HIGH                       ; 1                 ; Untyped                                                             ;
; G3_HIGH                       ; 1                 ; Untyped                                                             ;
; E0_HIGH                       ; 1                 ; Untyped                                                             ;
; E1_HIGH                       ; 1                 ; Untyped                                                             ;
; E2_HIGH                       ; 1                 ; Untyped                                                             ;
; E3_HIGH                       ; 1                 ; Untyped                                                             ;
; L0_LOW                        ; 1                 ; Untyped                                                             ;
; L1_LOW                        ; 1                 ; Untyped                                                             ;
; G0_LOW                        ; 1                 ; Untyped                                                             ;
; G1_LOW                        ; 1                 ; Untyped                                                             ;
; G2_LOW                        ; 1                 ; Untyped                                                             ;
; G3_LOW                        ; 1                 ; Untyped                                                             ;
; E0_LOW                        ; 1                 ; Untyped                                                             ;
; E1_LOW                        ; 1                 ; Untyped                                                             ;
; E2_LOW                        ; 1                 ; Untyped                                                             ;
; E3_LOW                        ; 1                 ; Untyped                                                             ;
; L0_INITIAL                    ; 1                 ; Untyped                                                             ;
; L1_INITIAL                    ; 1                 ; Untyped                                                             ;
; G0_INITIAL                    ; 1                 ; Untyped                                                             ;
; G1_INITIAL                    ; 1                 ; Untyped                                                             ;
; G2_INITIAL                    ; 1                 ; Untyped                                                             ;
; G3_INITIAL                    ; 1                 ; Untyped                                                             ;
; E0_INITIAL                    ; 1                 ; Untyped                                                             ;
; E1_INITIAL                    ; 1                 ; Untyped                                                             ;
; E2_INITIAL                    ; 1                 ; Untyped                                                             ;
; E3_INITIAL                    ; 1                 ; Untyped                                                             ;
; L0_MODE                       ; BYPASS            ; Untyped                                                             ;
; L1_MODE                       ; BYPASS            ; Untyped                                                             ;
; G0_MODE                       ; BYPASS            ; Untyped                                                             ;
; G1_MODE                       ; BYPASS            ; Untyped                                                             ;
; G2_MODE                       ; BYPASS            ; Untyped                                                             ;
; G3_MODE                       ; BYPASS            ; Untyped                                                             ;
; E0_MODE                       ; BYPASS            ; Untyped                                                             ;
; E1_MODE                       ; BYPASS            ; Untyped                                                             ;
; E2_MODE                       ; BYPASS            ; Untyped                                                             ;
; E3_MODE                       ; BYPASS            ; Untyped                                                             ;
; L0_PH                         ; 0                 ; Untyped                                                             ;
; L1_PH                         ; 0                 ; Untyped                                                             ;
; G0_PH                         ; 0                 ; Untyped                                                             ;
; G1_PH                         ; 0                 ; Untyped                                                             ;
; G2_PH                         ; 0                 ; Untyped                                                             ;
; G3_PH                         ; 0                 ; Untyped                                                             ;
; E0_PH                         ; 0                 ; Untyped                                                             ;
; E1_PH                         ; 0                 ; Untyped                                                             ;
; E2_PH                         ; 0                 ; Untyped                                                             ;
; E3_PH                         ; 0                 ; Untyped                                                             ;
; M_PH                          ; 0                 ; Untyped                                                             ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                                                             ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                                                             ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                                                             ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                                                             ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                                                             ;
; CLK0_COUNTER                  ; G0                ; Untyped                                                             ;
; CLK1_COUNTER                  ; G0                ; Untyped                                                             ;
; CLK2_COUNTER                  ; G0                ; Untyped                                                             ;
; CLK3_COUNTER                  ; G0                ; Untyped                                                             ;
; CLK4_COUNTER                  ; G0                ; Untyped                                                             ;
; CLK5_COUNTER                  ; G0                ; Untyped                                                             ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                                                             ;
; M_TIME_DELAY                  ; 0                 ; Untyped                                                             ;
; N_TIME_DELAY                  ; 0                 ; Untyped                                                             ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                                                             ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                                                             ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                                                             ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                                                             ;
; ENABLE0_COUNTER               ; L0                ; Untyped                                                             ;
; ENABLE1_COUNTER               ; L0                ; Untyped                                                             ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                                             ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                                             ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                                                             ;
; VCO_POST_SCALE                ; 0                 ; Untyped                                                             ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                             ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                             ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                             ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                                                             ;
; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                                             ;
; PORT_LOCKED                   ; PORT_CONNECTIVITY ; Untyped                                                             ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                                                             ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                                                             ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                                                             ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                                          ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                                                        ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                                                        ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                                                      ;
+-------------------------------+-------------------+---------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1 ;
+----------------+-------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------+
; INIT_PER       ; 24000 ; Integer                                                                           ;
; REF_PER        ; 1024  ; Integer                                                                           ;
; SC_CL          ; 3     ; Integer                                                                           ;
; SC_RCD         ; 3     ; Integer                                                                           ;
; SC_RRD         ; 7     ; Integer                                                                           ;
; SC_PM          ; 1     ; Integer                                                                           ;
; SC_BL          ; 1     ; Integer                                                                           ;
; SDR_BL         ; 111   ; Binary                                                                            ;
; SDR_BT         ; 0     ; Binary                                                                            ;
; SDR_CL         ; 011   ; Binary                                                                            ;
+----------------+-------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|command:command1 ;
+----------------+-------+-------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                    ;
+----------------+-------+-------------------------------------------------------------------------+
; INIT_PER       ; 24000 ; Integer                                                                 ;
; REF_PER        ; 1024  ; Integer                                                                 ;
; SC_CL          ; 3     ; Integer                                                                 ;
; SC_RCD         ; 3     ; Integer                                                                 ;
; SC_RRD         ; 7     ; Integer                                                                 ;
; SC_PM          ; 1     ; Integer                                                                 ;
; SC_BL          ; 1     ; Integer                                                                 ;
; SDR_BL         ; 111   ; Binary                                                                  ;
; SDR_BT         ; 0     ; Binary                                                                  ;
; SDR_CL         ; 011   ; Binary                                                                  ;
+----------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1 ;
+----------------+-------+---------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                            ;
+----------------+-------+---------------------------------------------------------------------------------+
; INIT_PER       ; 24000 ; Integer                                                                         ;
; REF_PER        ; 1024  ; Integer                                                                         ;
; SC_CL          ; 3     ; Integer                                                                         ;
; SC_RCD         ; 3     ; Integer                                                                         ;
; SC_RRD         ; 7     ; Integer                                                                         ;
; SC_PM          ; 1     ; Integer                                                                         ;
; SC_BL          ; 1     ; Integer                                                                         ;
; SDR_BL         ; 111   ; Binary                                                                          ;
; SDR_BT         ; 0     ; Binary                                                                          ;
; SDR_CL         ; 011   ; Binary                                                                          ;
+----------------+-------+---------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ps2_keyboard:u4 ;
+-----------------------------+-------+------------------------+
; Parameter Name              ; Value ; Type                   ;
+-----------------------------+-------+------------------------+
; TIMER_60USEC_VALUE_PP       ; 2950  ; Integer                ;
; TIMER_60USEC_BITS_PP        ; 12    ; Integer                ;
; TIMER_5USEC_VALUE_PP        ; 186   ; Integer                ;
; TIMER_5USEC_BITS_PP         ; 8     ; Integer                ;
; TRAP_SHIFT_KEYS_PP          ; 0     ; Integer                ;
; m1_rx_clk_h                 ; 1     ; Integer                ;
; m1_rx_clk_l                 ; 0     ; Integer                ;
; m1_rx_falling_edge_marker   ; 13    ; Integer                ;
; m1_rx_rising_edge_marker    ; 14    ; Integer                ;
; m1_tx_force_clk_l           ; 3     ; Integer                ;
; m1_tx_first_wait_clk_h      ; 10    ; Integer                ;
; m1_tx_first_wait_clk_l      ; 11    ; Integer                ;
; m1_tx_reset_timer           ; 12    ; Integer                ;
; m1_tx_wait_clk_h            ; 2     ; Integer                ;
; m1_tx_clk_h                 ; 4     ; Integer                ;
; m1_tx_clk_l                 ; 5     ; Integer                ;
; m1_tx_wait_keyboard_ack     ; 6     ; Integer                ;
; m1_tx_done_recovery         ; 7     ; Integer                ;
; m1_tx_error_no_keyboard_ack ; 8     ; Integer                ;
; m1_tx_rising_edge_marker    ; 9     ; Integer                ;
; m2_rx_data_ready            ; 1     ; Integer                ;
; m2_rx_data_ready_ack        ; 0     ; Integer                ;
+-----------------------------+-------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CMD_Decode:u5 ;
+----------------+----------+--------------------------------+
; Parameter Name ; Value    ; Type                           ;
+----------------+----------+--------------------------------+
; SETUP          ; 01100001 ; Binary                         ;
; ERASE          ; 01110010 ; Binary                         ;
; WRITE          ; 10000011 ; Binary                         ;
; READ           ; 10010100 ; Binary                         ;
; LCD_DAT        ; 10000011 ; Binary                         ;
; LCD_CMD        ; 10010100 ; Binary                         ;
; LED            ; 11110000 ; Binary                         ;
; SEG7           ; 11100001 ; Binary                         ;
; PS2            ; 11010010 ; Binary                         ;
; FLASH          ; 11000011 ; Binary                         ;
; SDRAM          ; 10110100 ; Binary                         ;
; SRAM           ; 10100101 ; Binary                         ;
; LCD            ; 10010110 ; Binary                         ;
; VGA            ; 10000111 ; Binary                         ;
; SDRSEL         ; 00011111 ; Binary                         ;
; FLSEL          ; 00101110 ; Binary                         ;
; EXTIO          ; 00111101 ; Binary                         ;
; SET_REG        ; 01001100 ; Binary                         ;
; SRSEL          ; 01011011 ; Binary                         ;
; OUTSEL         ; 00110011 ; Binary                         ;
; NORMAL         ; 10101010 ; Binary                         ;
; DISPLAY        ; 11001100 ; Binary                         ;
; BURST          ; 11111111 ; Binary                         ;
; CMD_READ       ; 000      ; Binary                         ;
; CMD_WRITE      ; 001      ; Binary                         ;
; CMD_BLK_ERA    ; 010      ; Binary                         ;
; CMD_SEC_ERA    ; 011      ; Binary                         ;
; CMD_CHP_ERA    ; 100      ; Binary                         ;
; CMD_ENTRY_ID   ; 101      ; Binary                         ;
; CMD_RESET      ; 110      ; Binary                         ;
+----------------+----------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------------+
; Parameter Name                ; Value             ; Type                              ;
+-------------------------------+-------------------+-----------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                           ;
; PLL_TYPE                      ; FAST              ; Untyped                           ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                           ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                           ;
; SCAN_CHAIN                    ; LONG              ; Untyped                           ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                           ;
; INCLK0_INPUT_FREQUENCY        ; 37037             ; Integer                           ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                           ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                           ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                           ;
; LOCK_HIGH                     ; 1                 ; Untyped                           ;
; LOCK_LOW                      ; 1                 ; Untyped                           ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                           ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                           ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                           ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                           ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                           ;
; SKIP_VCO                      ; OFF               ; Untyped                           ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                           ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                           ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                           ;
; BANDWIDTH                     ; 0                 ; Untyped                           ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                           ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                           ;
; DOWN_SPREAD                   ; 0                 ; Untyped                           ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                           ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK1_MULTIPLY_BY              ; 2                 ; Integer                           ;
; CLK0_MULTIPLY_BY              ; 14                ; Integer                           ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK2_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK1_DIVIDE_BY                ; 3                 ; Integer                           ;
; CLK0_DIVIDE_BY                ; 15                ; Integer                           ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK2_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK1_DUTY_CYCLE               ; 50                ; Integer                           ;
; CLK0_DUTY_CYCLE               ; 50                ; Integer                           ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                           ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                           ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                           ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; VCO_MIN                       ; 0                 ; Untyped                           ;
; VCO_MAX                       ; 0                 ; Untyped                           ;
; VCO_CENTER                    ; 0                 ; Untyped                           ;
; PFD_MIN                       ; 0                 ; Untyped                           ;
; PFD_MAX                       ; 0                 ; Untyped                           ;
; M_INITIAL                     ; 0                 ; Untyped                           ;
; M                             ; 0                 ; Untyped                           ;
; N                             ; 1                 ; Untyped                           ;
; M2                            ; 1                 ; Untyped                           ;
; N2                            ; 1                 ; Untyped                           ;
; SS                            ; 1                 ; Untyped                           ;
; C0_HIGH                       ; 0                 ; Untyped                           ;
; C1_HIGH                       ; 0                 ; Untyped                           ;
; C2_HIGH                       ; 0                 ; Untyped                           ;
; C3_HIGH                       ; 0                 ; Untyped                           ;
; C4_HIGH                       ; 0                 ; Untyped                           ;
; C5_HIGH                       ; 0                 ; Untyped                           ;
; C0_LOW                        ; 0                 ; Untyped                           ;
; C1_LOW                        ; 0                 ; Untyped                           ;
; C2_LOW                        ; 0                 ; Untyped                           ;
; C3_LOW                        ; 0                 ; Untyped                           ;
; C4_LOW                        ; 0                 ; Untyped                           ;
; C5_LOW                        ; 0                 ; Untyped                           ;
; C0_INITIAL                    ; 0                 ; Untyped                           ;
; C1_INITIAL                    ; 0                 ; Untyped                           ;
; C2_INITIAL                    ; 0                 ; Untyped                           ;
; C3_INITIAL                    ; 0                 ; Untyped                           ;
; C4_INITIAL                    ; 0                 ; Untyped                           ;
; C5_INITIAL                    ; 0                 ; Untyped                           ;
; C0_MODE                       ; BYPASS            ; Untyped                           ;
; C1_MODE                       ; BYPASS            ; Untyped                           ;
; C2_MODE                       ; BYPASS            ; Untyped                           ;
; C3_MODE                       ; BYPASS            ; Untyped                           ;
; C4_MODE                       ; BYPASS            ; Untyped                           ;
; C5_MODE                       ; BYPASS            ; Untyped                           ;
; C0_PH                         ; 0                 ; Untyped                           ;
; C1_PH                         ; 0                 ; Untyped                           ;
; C2_PH                         ; 0                 ; Untyped                           ;
; C3_PH                         ; 0                 ; Untyped                           ;
; C4_PH                         ; 0                 ; Untyped                           ;
; C5_PH                         ; 0                 ; Untyped                           ;
; L0_HIGH                       ; 1                 ; Untyped                           ;
; L1_HIGH                       ; 1                 ; Untyped                           ;
; G0_HIGH                       ; 1                 ; Untyped                           ;
; G1_HIGH                       ; 1                 ; Untyped                           ;
; G2_HIGH                       ; 1                 ; Untyped                           ;
; G3_HIGH                       ; 1                 ; Untyped                           ;
; E0_HIGH                       ; 1                 ; Untyped                           ;
; E1_HIGH                       ; 1                 ; Untyped                           ;
; E2_HIGH                       ; 1                 ; Untyped                           ;
; E3_HIGH                       ; 1                 ; Untyped                           ;
; L0_LOW                        ; 1                 ; Untyped                           ;
; L1_LOW                        ; 1                 ; Untyped                           ;
; G0_LOW                        ; 1                 ; Untyped                           ;
; G1_LOW                        ; 1                 ; Untyped                           ;
; G2_LOW                        ; 1                 ; Untyped                           ;
; G3_LOW                        ; 1                 ; Untyped                           ;
; E0_LOW                        ; 1                 ; Untyped                           ;
; E1_LOW                        ; 1                 ; Untyped                           ;
; E2_LOW                        ; 1                 ; Untyped                           ;
; E3_LOW                        ; 1                 ; Untyped                           ;
; L0_INITIAL                    ; 1                 ; Untyped                           ;
; L1_INITIAL                    ; 1                 ; Untyped                           ;
; G0_INITIAL                    ; 1                 ; Untyped                           ;
; G1_INITIAL                    ; 1                 ; Untyped                           ;
; G2_INITIAL                    ; 1                 ; Untyped                           ;
; G3_INITIAL                    ; 1                 ; Untyped                           ;
; E0_INITIAL                    ; 1                 ; Untyped                           ;
; E1_INITIAL                    ; 1                 ; Untyped                           ;
; E2_INITIAL                    ; 1                 ; Untyped                           ;
; E3_INITIAL                    ; 1                 ; Untyped                           ;
; L0_MODE                       ; BYPASS            ; Untyped                           ;
; L1_MODE                       ; BYPASS            ; Untyped                           ;
; G0_MODE                       ; BYPASS            ; Untyped                           ;
; G1_MODE                       ; BYPASS            ; Untyped                           ;
; G2_MODE                       ; BYPASS            ; Untyped                           ;
; G3_MODE                       ; BYPASS            ; Untyped                           ;
; E0_MODE                       ; BYPASS            ; Untyped                           ;
; E1_MODE                       ; BYPASS            ; Untyped                           ;
; E2_MODE                       ; BYPASS            ; Untyped                           ;
; E3_MODE                       ; BYPASS            ; Untyped                           ;
; L0_PH                         ; 0                 ; Untyped                           ;
; L1_PH                         ; 0                 ; Untyped                           ;
; G0_PH                         ; 0                 ; Untyped                           ;
; G1_PH                         ; 0                 ; Untyped                           ;
; G2_PH                         ; 0                 ; Untyped                           ;
; G3_PH                         ; 0                 ; Untyped                           ;
; E0_PH                         ; 0                 ; Untyped                           ;
; E1_PH                         ; 0                 ; Untyped                           ;
; E2_PH                         ; 0                 ; Untyped                           ;
; E3_PH                         ; 0                 ; Untyped                           ;
; M_PH                          ; 0                 ; Untyped                           ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                           ;
; CLK0_COUNTER                  ; G0                ; Untyped                           ;
; CLK1_COUNTER                  ; G0                ; Untyped                           ;
; CLK2_COUNTER                  ; G0                ; Untyped                           ;
; CLK3_COUNTER                  ; G0                ; Untyped                           ;
; CLK4_COUNTER                  ; G0                ; Untyped                           ;
; CLK5_COUNTER                  ; G0                ; Untyped                           ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; M_TIME_DELAY                  ; 0                 ; Untyped                           ;
; N_TIME_DELAY                  ; 0                 ; Untyped                           ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                           ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                           ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                           ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                           ;
; ENABLE0_COUNTER               ; L0                ; Untyped                           ;
; ENABLE1_COUNTER               ; L0                ; Untyped                           ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                           ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                           ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                           ;
; VCO_POST_SCALE                ; 0                 ; Untyped                           ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                           ;
; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_LOCKED                   ; PORT_CONNECTIVITY ; Untyped                           ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                           ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                           ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                           ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                    ;
+-------------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Controller:u8 ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; H_SYNC_CYC     ; 96    ; Integer                               ;
; H_SYNC_BACK    ; 48    ; Integer                               ;
; H_SYNC_ACT     ; 640   ; Integer                               ;
; H_SYNC_FRONT   ; 16    ; Integer                               ;
; H_SYNC_TOTAL   ; 800   ; Integer                               ;
; V_SYNC_CYC     ; 2     ; Integer                               ;
; V_SYNC_BACK    ; 32    ; Integer                               ;
; V_SYNC_ACT     ; 480   ; Integer                               ;
; V_SYNC_FRONT   ; 11    ; Integer                               ;
; V_SYNC_TOTAL   ; 525   ; Integer                               ;
; X_START        ; 148   ; Integer                               ;
; Y_START        ; 34    ; Integer                               ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9 ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type                               ;
+----------------+-------+------------------------------------+
; START_X        ; 60    ; Integer                            ;
; START_Y        ; 50    ; Integer                            ;
; END_X          ; 580   ; Integer                            ;
; END_Y          ; 450   ; Integer                            ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                            ;
+------------------------------------+-----------------+-------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                         ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                      ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                    ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                  ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                         ;
; WIDTH_A                            ; 1               ; Integer                                         ;
; WIDTHAD_A                          ; 18              ; Integer                                         ;
; NUMWORDS_A                         ; 208000          ; Integer                                         ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                         ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                         ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                         ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                         ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                         ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                         ;
; WIDTH_B                            ; 8               ; Integer                                         ;
; WIDTHAD_B                          ; 15              ; Integer                                         ;
; NUMWORDS_B                         ; 26000           ; Integer                                         ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                         ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                         ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                         ;
; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                         ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                         ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                         ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                         ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                         ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                         ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                         ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                         ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                         ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                         ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                                         ;
; BYTE_SIZE                          ; 8               ; Untyped                                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                         ;
; INIT_FILE                          ; Img_DATA.hex    ; Untyped                                         ;
; INIT_FILE_LAYOUT                   ; PORT_B          ; Untyped                                         ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                         ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                         ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                         ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                         ;
; CBXI_PARAMETER                     ; altsyncram_f7o1 ; Untyped                                         ;
+------------------------------------+-----------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u10 ;
+----------------+----------+------------------------------------+
; Parameter Name ; Value    ; Type                               ;
+----------------+----------+------------------------------------+
; CLK_Freq       ; 50000000 ; Integer                            ;
; I2C_Freq       ; 20000    ; Integer                            ;
; LUT_SIZE       ; 11       ; Integer                            ;
; Dummy_DATA     ; 0        ; Integer                            ;
; SET_LIN_L      ; 1        ; Integer                            ;
; SET_LIN_R      ; 2        ; Integer                            ;
; SET_HEAD_L     ; 3        ; Integer                            ;
; SET_HEAD_R     ; 4        ; Integer                            ;
; A_PATH_CTRL    ; 5        ; Integer                            ;
; D_PATH_CTRL    ; 6        ; Integer                            ;
; POWER_ON       ; 7        ; Integer                            ;
; SET_FORMAT     ; 8        ; Integer                            ;
; SAMPLE_CTRL    ; 9        ; Integer                            ;
; SET_ACTIVE     ; 10       ; Integer                            ;
+----------------+----------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AUDIO_DAC:u11 ;
+------------------+----------+------------------------------+
; Parameter Name   ; Value    ; Type                         ;
+------------------+----------+------------------------------+
; REF_CLK          ; 18432000 ; Integer                      ;
; SAMPLE_RATE      ; 48000    ; Integer                      ;
; DATA_WIDTH       ; 16       ; Integer                      ;
; CHANNEL_NUM      ; 2        ; Integer                      ;
; SIN_SAMPLE_DATA  ; 48       ; Integer                      ;
; FLASH_DATA_NUM   ; 4194304  ; Integer                      ;
; SDRAM_DATA_NUM   ; 4194304  ; Integer                      ;
; SRAM_DATA_NUM    ; 262144   ; Integer                      ;
; FLASH_ADDR_WIDTH ; 22       ; Integer                      ;
; SDRAM_ADDR_WIDTH ; 22       ; Integer                      ;
; SRAM_ADDR_WIDTH  ; 18       ; Integer                      ;
; FLASH_DATA_WIDTH ; 8        ; Integer                      ;
; SDRAM_DATA_WIDTH ; 16       ; Integer                      ;
; SRAM_DATA_WIDTH  ; 16       ; Integer                      ;
; SIN_SANPLE       ; 0        ; Integer                      ;
; FLASH_DATA       ; 1        ; Integer                      ;
; SDRAM_DATA       ; 2        ; Integer                      ;
; SRAM_DATA        ; 3        ; Integer                      ;
+------------------+----------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Sep 13 15:42:27 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE1_USB_API -c DE1_USB_API
Info: Found 1 design units, including 1 entities, in source file VGA_Controller/Img_RAM.v
    Info: Found entity 1: Img_RAM
Info: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_OSD_RAM.v
    Info: Found entity 1: VGA_OSD_RAM
Info: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_Controller.v
    Info: Found entity 1: VGA_Controller
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/command.v
    Info: Found entity 1: command
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/control_interface.v
    Info: Found entity 1: control_interface
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/Multi_Sdram.v
    Info: Found entity 1: Multi_Sdram
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/PLL1.v
    Info: Found entity 1: PLL1
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/sdr_data_path.v
    Info: Found entity 1: sdr_data_path
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/Sdram_Controller.v
    Info: Found entity 1: Sdram_Controller
Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/Sdram_Multiplexer.v
    Info: Found entity 1: Sdram_Multiplexer
Info: Found 1 design units, including 1 entities, in source file Multi_Flash/Flash_Controller.v
    Info: Found entity 1: Flash_Controller
Info: Found 1 design units, including 1 entities, in source file Multi_Flash/Flash_Multiplexer.v
    Info: Found entity 1: Flash_Multiplexer
Info: Found 1 design units, including 1 entities, in source file Multi_Flash/Multi_Flash.v
    Info: Found entity 1: Multi_Flash
Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC.v
    Info: Found entity 1: AUDIO_DAC
Info: Found 2 design units, including 2 entities, in source file CLK_LOCK.v
    Info: Found entity 1: CLK_LOCK_altclkctrl_tb8
    Info: Found entity 2: CLK_LOCK
Info: Found 1 design units, including 1 entities, in source file CMD_Decode.v
    Info: Found entity 1: CMD_Decode
Info: Found 1 design units, including 1 entities, in source file DE1_USB_API.v
    Info: Found entity 1: DE1_USB_API
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file Multi_Sram.v
    Info: Found entity 1: Multi_Sram
Info: Found 1 design units, including 1 entities, in source file ps2_keyboard.v
    Info: Found entity 1: ps2_keyboard
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Info: Found 1 design units, including 1 entities, in source file RS232_Controller.v
    Info: Found entity 1: RS232_Controller
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v
    Info: Found entity 1: SRAM_16Bit_512K
Info: Found 3 design units, including 3 entities, in source file USB_JTAG.v
    Info: Found entity 1: USB_JTAG
    Info: Found entity 2: JTAG_REC
    Info: Found entity 3: JTAG_TRANS
Info: Found 1 design units, including 1 entities, in source file VGA_Audio_PLL.v
    Info: Found entity 1: VGA_Audio_PLL
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_4.v
    Info: Found entity 1: SEG7_LUT_4
Info: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_Pattern.v
    Info: Found entity 1: VGA_Pattern
Info: Elaborating entity "DE1_USB_API" for the top level hierarchy
Warning (10034): Output port "UART_TXD" at DE1_USB_API.v(145) has no driver
Warning (10034): Output port "SD_CLK" at DE1_USB_API.v(179) has no driver
Info: Elaborating entity "CLK_LOCK" for hierarchy "CLK_LOCK:p0"
Info: Elaborating entity "CLK_LOCK_altclkctrl_tb8" for hierarchy "CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component"
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:d0"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(10): truncated value with size 32 to match size of target (20)
Info: Elaborating entity "SEG7_LUT_4" for hierarchy "SEG7_LUT_4:u0"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_4:u0|SEG7_LUT:u0"
Info: Elaborating entity "USB_JTAG" for hierarchy "USB_JTAG:u1"
Info: Elaborating entity "JTAG_REC" for hierarchy "USB_JTAG:u1|JTAG_REC:u0"
Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(81): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "JTAG_TRANS" for hierarchy "USB_JTAG:u1|JTAG_TRANS:u1"
Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(116): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "Multi_Flash" for hierarchy "Multi_Flash:u2"
Info: Elaborating entity "Flash_Multiplexer" for hierarchy "Multi_Flash:u2|Flash_Multiplexer:u0"
Info: Elaborating entity "Flash_Controller" for hierarchy "Multi_Flash:u2|Flash_Controller:u1"
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(83): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(132): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(227): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(239): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(240): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(241): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(242): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(243): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(244): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(245): truncated value with size 32 to match size of target (22)
Info: Elaborating entity "Multi_Sdram" for hierarchy "Multi_Sdram:u3"
Info: Elaborating entity "Sdram_Multiplexer" for hierarchy "Multi_Sdram:u3|Sdram_Multiplexer:u0"
Info: Elaborating entity "Sdram_Controller" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1"
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(30): object "INIT_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(31): object "REF_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(34): object "SC_RRD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(51): object "SDR_BL" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(56): object "SDR_BT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object "SDR_CL" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at Sdram_Controller.v(225): truncated value with size 32 to match size of target (9)
Info: Elaborating entity "PLL1" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component"
Info: Elaborating entity "control_interface" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1"
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(33): object "SC_RCD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(34): object "SC_RRD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(51): object "SDR_BL" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(56): object "SDR_BT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object "SDR_CL" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at control_interface.v(120): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(125): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(150): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "command" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|command:command1"
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(30): object "INIT_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(31): object "REF_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(34): object "SC_RRD" assigned a value but never read
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[6]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[5]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[4]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[3]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[2]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[1]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[0]"
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(81): inferred latch for "oe1"
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(82): inferred latch for "oe2"
Info: Elaborating entity "sdr_data_path" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1"
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(30): object "INIT_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(31): object "REF_PER" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(33): object "SC_RCD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(34): object "SC_RRD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(51): object "SDR_BL" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(56): object "SDR_BT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Sdram_Params.h(58): object "SDR_CL" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at sdr_data_path.v(24): object "DM1" assigned a value but never read
Info (10041): Verilog HDL or VHDL info at sdr_data_path.v(24): inferred latch for "DM1[1]"
Info (10041): Verilog HDL or VHDL info at sdr_data_path.v(24): inferred latch for "DM1[0]"
Info: Elaborating entity "ps2_keyboard" for hierarchy "ps2_keyboard:u4"
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(310): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(321): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(322): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(327): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(328): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(330): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(348): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(377): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(385): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "CMD_Decode" for hierarchy "CMD_Decode:u5"
Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(6): object "LCD_DAT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(7): object "LCD_CMD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(15): object "LCD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(19): object "EXTIO" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at RS232_Command.h(26): object "BURST" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Flash_Command.h(4): object "CMD_BLK_ERA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Flash_Command.h(5): object "CMD_SEC_ERA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Flash_Command.h(7): object "CMD_ENTRY_ID" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Flash_Command.h(8): object "CMD_RESET" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at CMD_Decode.v(81): object "sel_PS2" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(249): truncated value with size 24 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(250): truncated value with size 16 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(307): truncated value with size 24 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(308): truncated value with size 16 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(433): truncated value with size 24 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(517): truncated value with size 24 to match size of target (18)
Info: Elaborating entity "Multi_Sram" for hierarchy "Multi_Sram:u6"
Info: Elaborating entity "VGA_Audio_PLL" for hierarchy "VGA_Audio_PLL:p1"
Info: Elaborating entity "altpll" for hierarchy "VGA_Audio_PLL:p1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "VGA_Audio_PLL:p1|altpll:altpll_component"
Info: Elaborating entity "VGA_Controller" for hierarchy "VGA_Controller:u8"
Warning (10036): Verilog HDL or VHDL warning at VGA_Param.h(5): object "H_SYNC_FRONT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at VGA_Param.h(11): object "V_SYNC_FRONT" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(74): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(77): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(80): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(98): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(99): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(100): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(159): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(185): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "VGA_OSD_RAM" for hierarchy "VGA_OSD_RAM:u9"
Warning (10230): Verilog HDL assignment warning at VGA_OSD_RAM.v(56): truncated value with size 32 to match size of target (19)
Info: Elaborating entity "Img_RAM" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f7o1.tdf
    Info: Found entity 1: altsyncram_f7o1
Info: Elaborating entity "altsyncram_f7o1" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e132.tdf
    Info: Found entity 1: altsyncram_e132
Info: Elaborating entity "altsyncram_e132" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1"
Warning: Variable or input pin "clocken1" is defined but never used
Info: Found 1 design units, including 1 entities, in source file db/decode_qpa.tdf
    Info: Found entity 1: decode_qpa
Info: Elaborating entity "decode_qpa" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode3"
Info: Elaborating entity "decode_qpa" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a"
Info: Found 1 design units, including 1 entities, in source file db/mux_akb.tdf
    Info: Found entity 1: mux_akb
Info: Elaborating entity "mux_akb" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_akb:mux5"
Info: Found 1 design units, including 1 entities, in source file db/mux_3kb.tdf
    Info: Found entity 1: mux_3kb
Info: Elaborating entity "mux_3kb" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_3kb:mux6"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u10"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(53): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(101): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u10|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "AUDIO_DAC" for hierarchy "AUDIO_DAC:u11"
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC.v(36): object "SRAM_DATA" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(92): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(117): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(125): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(133): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(146): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(160): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(196): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(227): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(256): truncated value with size 32 to match size of target (4)
Warning: Port "rdaddress" on the entity instantiation of "u0" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be driven by GND.
Warning: Port "wraddress" on the entity instantiation of "u0" is connected to a signal of width 19. The formal width of the signal in the module is 18.  Extra bits will be driven by GND.
Warning: Port "iOFF_B" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iOFF_G" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iOFF_R" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iON_B" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iON_G" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iON_R" on the entity instantiation of "u9" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "iVGA_ADDR" on the entity instantiation of "u9" is connected to a signal of width 20. The formal width of the signal in the module is 19.  Extra bits will be driven by GND.
Warning: Port "iAS1_ADDR" on the entity instantiation of "u6" is connected to a signal of width 19. The formal width of the signal in the module is 18.  Extra bits will be driven by GND.
Warning: Port "iSelect" on the entity instantiation of "u6" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be driven by GND.
Warning: Port "oFL_Select" on the entity instantiation of "u5" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be left dangling without any fanout logic.
Warning: Port "oLED_GREEN" on the entity instantiation of "u5" is connected to a signal of width 8. The formal width of the signal in the module is 9.  Extra bits will be left dangling without any fanout logic.
Warning: Port "oLED_RED" on the entity instantiation of "u5" is connected to a signal of width 10. The formal width of the signal in the module is 18.  Extra bits will be left dangling without any fanout logic.
Warning: Port "oSDR_Select" on the entity instantiation of "u5" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be left dangling without any fanout logic.
Warning: Port "oSR_Select" on the entity instantiation of "u5" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be left dangling without any fanout logic.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSR_Select[2]"
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSR_Select[2]"
Warning: Port "CMD" on the entity instantiation of "control1" is connected to a signal of width 2. The formal width of the signal in the module is 3.  Extra bits will be driven by GND.
Warning: Port "CS_N" on the entity instantiation of "u1" is connected to a signal of width 1. The formal width of the signal in the module is 2.  Extra bits will be left dangling without any fanout logic.
Warning: Port "#18" on the entity instantiation of "u3" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be driven by GND.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: Port "#12" on the entity instantiation of "u2" is connected to a signal of width 3. The formal width of the signal in the module is 2.  Extra bits will be driven by GND.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mFL_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mFL_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: Port "#4" on the entity instantiation of "u0" is connected to a signal of width 32. The formal width of the signal in the module is 16.  Extra bits will be driven by GND.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mFL_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mFL_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "mSDR_Select[2]"
    Warning: Net "mFL_Select[2]"
    Warning: Net "mSR_Select[2]"
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out_Tmp[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SDRAM_Out[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out_Tmp[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "AUDIO_DAC:u11|SRAM_Out[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "CMD_Decode:u5|oFL_CMD[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[22]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[21]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[20]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[18]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|r_CMD[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[22]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u10|mI2C_DATA[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_AV_Config:u10|mI2C_DATA[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[20]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u10|mI2C_DATA[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[18]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|mI2C_DATA[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[22]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u10|I2C_Controller:u0|SD[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "I2C_AV_Config:u10|I2C_Controller:u0|SD[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[20]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Info: Power-up level of register "I2C_AV_Config:u10|I2C_Controller:u0|SD[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[18]" with stuck data_in port to stuck value VCC
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u10|I2C_Controller:u0|SD[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "ps2_keyboard:u4|hold_released" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "CMD_Decode:u5|mSR_WRn" merged to single register "CMD_Decode:u5|mSDR_WRn"
    Info: Duplicate register "Multi_Sdram:u3|Sdram_Controller:u1|DQM[0]" merged to single register "Multi_Sdram:u3|Sdram_Controller:u1|DQM[1]"
    Info: Duplicate register "Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CKE" merged to single register "Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CS_N[0]", power-up level changed
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[0]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|mCLK"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|pre_mCLK" merged to single register "Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[1]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[16]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[15]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[14]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[9]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[8]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[7]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[6]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[5]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[4]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[3]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19]"
    Info: Duplicate register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[0]" merged to single register "Multi_Flash:u2|Flash_Controller:u1|CMD_Period[1]"
    Info: Duplicate register "Multi_Sdram:u3|Sdram_Controller:u1|CKE" merged to single register "Multi_Sdram:u3|Sdram_Controller:u1|CS_N[0]", power-up level changed
Warning: Reduced register "ps2_keyboard:u4|rx_ascii[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "CMD_Decode:u5|oPS2_TXD_DATA[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "VGA_OSD_RAM:u9|oRed[9]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oRed[7]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oRed[6]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oGreen[9]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oGreen[8]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oGreen[7]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oGreen[6]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oBlue[8]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oBlue[7]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
    Info: Duplicate register "VGA_OSD_RAM:u9|oBlue[6]" merged to single register "VGA_OSD_RAM:u9|oRed[8]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "I2C_AV_Config:u10|mI2C_DATA[5]" merged to single register "I2C_AV_Config:u10|mI2C_DATA[6]"
    Info: Duplicate register "I2C_AV_Config:u10|mI2C_DATA[3]" merged to single register "I2C_AV_Config:u10|mI2C_DATA[4]"
    Info: Duplicate register "I2C_AV_Config:u10|I2C_Controller:u0|SD[5]" merged to single register "I2C_AV_Config:u10|I2C_Controller:u0|SD[6]"
    Info: Duplicate register "I2C_AV_Config:u10|I2C_Controller:u0|SD[3]" merged to single register "I2C_AV_Config:u10|I2C_Controller:u0|SD[4]"
Warning: Reduced register "Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_WR" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[0]" merged to single register "AUDIO_DAC:u11|Ram0~21"
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[1]" merged to single register "AUDIO_DAC:u11|Ram0~22"
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[2]" merged to single register "AUDIO_DAC:u11|Ram0~23"
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[3]" merged to single register "AUDIO_DAC:u11|Ram0~24"
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[4]" merged to single register "AUDIO_DAC:u11|Ram0~25"
    Info: Duplicate register "AUDIO_DAC:u11|SIN_Cont[5]" merged to single register "AUDIO_DAC:u11|Ram0~26"
Info: State machine "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST" contains 3 states
Info: State machine "|DE1_USB_API|CMD_Decode:u5|mFL_ST" contains 8 states
Info: State machine "|DE1_USB_API|CMD_Decode:u5|mPS2_ST" contains 2 states
Info: State machine "|DE1_USB_API|CMD_Decode:u5|mSDR_ST" contains 6 states
Info: State machine "|DE1_USB_API|CMD_Decode:u5|mSR_ST" contains 6 states
Info: State machine "|DE1_USB_API|ps2_keyboard:u4|m1_state" contains 15 states
Info: State machine "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST" contains 4 states
Info: State machine "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST" contains 14 states
Info: State machine "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST"
Info: Encoding result for state machine "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u10|mSetup_ST.00"
        Info: Encoded state bit "I2C_AV_Config:u10|mSetup_ST.10"
        Info: Encoded state bit "I2C_AV_Config:u10|mSetup_ST.01"
    Info: State "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST.00" uses code string "000"
    Info: State "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST.01" uses code string "101"
    Info: State "|DE1_USB_API|I2C_AV_Config:u10|mSetup_ST.10" uses code string "110"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|CMD_Decode:u5|mFL_ST"
Info: Encoding result for state machine "|DE1_USB_API|CMD_Decode:u5|mFL_ST"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.111"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.001"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.010"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.011"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.100"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.101"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.110"
        Info: Encoded state bit "CMD_Decode:u5|mFL_ST.000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.000" uses code string "00000000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.110" uses code string "00000011"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.101" uses code string "00000101"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.100" uses code string "00001001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.011" uses code string "00010001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.010" uses code string "00100001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.001" uses code string "01000001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mFL_ST.111" uses code string "10000001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|CMD_Decode:u5|mPS2_ST"
Info: Encoding result for state machine "|DE1_USB_API|CMD_Decode:u5|mPS2_ST"
    Info: Completed encoding using 1 state bits
        Info: Encoded state bit "CMD_Decode:u5|mPS2_ST.001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mPS2_ST.000" uses code string "0"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mPS2_ST.001" uses code string "1"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|CMD_Decode:u5|mSDR_ST"
Info: Encoding result for state machine "|DE1_USB_API|CMD_Decode:u5|mSDR_ST"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.101"
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.001"
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.010"
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.011"
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.100"
        Info: Encoded state bit "CMD_Decode:u5|mSDR_ST.000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.000" uses code string "000000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.100" uses code string "000011"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.011" uses code string "000101"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.010" uses code string "001001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.001" uses code string "010001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSDR_ST.101" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|CMD_Decode:u5|mSR_ST"
Info: Encoding result for state machine "|DE1_USB_API|CMD_Decode:u5|mSR_ST"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.101"
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.001"
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.010"
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.011"
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.100"
        Info: Encoded state bit "CMD_Decode:u5|mSR_ST.000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.000" uses code string "000000"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.100" uses code string "000011"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.011" uses code string "000101"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.010" uses code string "001001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.001" uses code string "010001"
    Info: State "|DE1_USB_API|CMD_Decode:u5|mSR_ST.101" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|ps2_keyboard:u4|m1_state"
Info: Encoding result for state machine "|DE1_USB_API|ps2_keyboard:u4|m1_state"
    Info: Completed encoding using 15 state bits
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_error_no_keyboard_ack"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_rx_falling_edge_marker"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_rx_rising_edge_marker"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_rx_clk_l"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_reset_timer"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_force_clk_l"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_h"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_l"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_wait_clk_h"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_rising_edge_marker"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_clk_h"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_clk_l"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_wait_keyboard_ack"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_tx_done_recovery"
        Info: Encoded state bit "ps2_keyboard:u4|m1_state.m1_rx_clk_h"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_rx_clk_h" uses code string "000000000000000"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_done_recovery" uses code string "000000000000011"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_wait_keyboard_ack" uses code string "000000000000101"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_clk_l" uses code string "000000000001001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_clk_h" uses code string "000000000010001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_rising_edge_marker" uses code string "000000000100001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_wait_clk_h" uses code string "000000001000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_l" uses code string "000000010000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_h" uses code string "000000100000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_force_clk_l" uses code string "000001000000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_reset_timer" uses code string "000010000000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_rx_clk_l" uses code string "000100000000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_rx_rising_edge_marker" uses code string "001000000000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_rx_falling_edge_marker" uses code string "010000000000001"
    Info: State "|DE1_USB_API|ps2_keyboard:u4|m1_state.m1_tx_error_no_keyboard_ack" uses code string "100000000000001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST"
Info: Encoding result for state machine "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.11"
        Info: Encoded state bit "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.01"
        Info: Encoded state bit "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.10"
        Info: Encoded state bit "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.00"
    Info: State "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.00" uses code string "0000"
    Info: State "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.10" uses code string "0011"
    Info: State "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.01" uses code string "0101"
    Info: State "|DE1_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.11" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST"
Info: Encoding result for state machine "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST"
    Info: Completed encoding using 14 state bits
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.READ"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P4_PRG"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.RESET"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P1"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P2"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P3_PRG"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P3_DEV"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P3"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P4"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P5"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P6_BLK_ERA"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P6_SEC_ERA"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.P6_CHP_ERA"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Controller:u1|ST.IDEL"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.IDEL" uses code string "00000000000000"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P6_CHP_ERA" uses code string "00000000000011"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P6_SEC_ERA" uses code string "00000000000101"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P6_BLK_ERA" uses code string "00000000001001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P5" uses code string "00000000010001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P4" uses code string "00000000100001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P3" uses code string "00000001000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P3_DEV" uses code string "00000010000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P3_PRG" uses code string "00000100000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P2" uses code string "00001000000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P1" uses code string "00010000000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.RESET" uses code string "00100000000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.P4_PRG" uses code string "01000000000001"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST.READ" uses code string "10000000000001"
Info: Selected Auto state machine encoding method for state machine "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST"
Info: Encoding result for state machine "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "Multi_Flash:u2|Flash_Multiplexer:u0|ST.11"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Multiplexer:u0|ST.01"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Multiplexer:u0|ST.10"
        Info: Encoded state bit "Multi_Flash:u2|Flash_Multiplexer:u0|ST.00"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST.00" uses code string "0000"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST.10" uses code string "0011"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST.01" uses code string "0101"
    Info: State "|DE1_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST.11" uses code string "1001"
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|ST.P6_BLK_ERA" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|ST.P6_SEC_ERA" with stuck data_in port to stuck value GND
Warning: Reduced register "Multi_Flash:u2|Flash_Controller:u1|ST.RESET" with stuck data_in port to stuck value GND
Warning: Reduced register "ps2_keyboard:u4|m1_state.m1_tx_force_clk_l" with stuck data_in port to stuck value GND
Warning: Reduced register "ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_h" with stuck data_in port to stuck value GND
Warning: Reduced register "ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_l" with stuck data_in port to stuck value GND
Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_BCLK~0 that it feeds
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Reduced register "AUDIO_DAC:u11|BCK_DIV[3]" with stuck data_in port to stuck value GND
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "AUD_BCLK~1"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "UART_TXD" stuck at GND
    Warning: Pin "FL_RST_N" stuck at VCC
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SD_CLK" stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a50" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a49" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a48" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a30" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a29" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a28" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a31" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a21" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a22" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a20" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a23" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a17" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a18" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a16" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a19" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a27" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a26" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a25" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a24" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a46" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a45" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a44" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a47" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a13" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a14" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a12" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a15" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a37" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a38" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a36" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a39" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a6" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a5" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a4" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a7" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a33" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a34" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a32" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a35" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a2" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a1" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a0" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a3" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a41" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a40" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a43" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a42" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a10" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a8" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a11" has port clk1 that is stuck at GND
Warning: WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a9" has port clk1 that is stuck at GND
Warning: Design contains 17 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLOCK_24[0]"
    Warning: No output dependent on input pin "CLOCK_24[1]"
    Warning: No output dependent on input pin "CLOCK_27[1]"
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
    Warning: No output dependent on input pin "SW[2]"
    Warning: No output dependent on input pin "SW[3]"
    Warning: No output dependent on input pin "SW[4]"
    Warning: No output dependent on input pin "SW[5]"
    Warning: No output dependent on input pin "SW[6]"
    Warning: No output dependent on input pin "SW[7]"
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "UART_RXD"
    Warning: No output dependent on input pin "AUD_ADCDAT"
Info: Implemented 2644 device resources after synthesis - the final resource count might be different
    Info: Implemented 27 input pins
    Info: Implemented 139 output pins
    Info: Implemented 117 bidirectional pins
    Info: Implemented 2307 logic cells
    Info: Implemented 51 RAM segments
    Info: Implemented 2 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 333 warnings
    Info: Processing ended: Wed Sep 13 15:43:10 2006
    Info: Elapsed time: 00:00:43


