-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --K1_oSEG7_DIG[0] is CMD_Decode:u5|oSEG7_DIG[0] K1_oSEG7_DIG[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[1] is CMD_Decode:u5|oSEG7_DIG[1] K1_oSEG7_DIG[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[2] is CMD_Decode:u5|oSEG7_DIG[2] K1_oSEG7_DIG[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[3] is CMD_Decode:u5|oSEG7_DIG[3] K1_oSEG7_DIG[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, KEY[0], , K1L407, , , , ); --T1L1 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[0]~70 T1L1 = K1_oSEG7_DIG[2] & !K1_oSEG7_DIG[1] & (K1_oSEG7_DIG[0] $ !K1_oSEG7_DIG[3]) # !K1_oSEG7_DIG[2] & K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[1] $ !K1_oSEG7_DIG[3]); --T1L2 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[1]~71 T1L2 = K1_oSEG7_DIG[1] & (K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[3]) # !K1_oSEG7_DIG[0] & K1_oSEG7_DIG[2]) # !K1_oSEG7_DIG[1] & K1_oSEG7_DIG[2] & (K1_oSEG7_DIG[0] $ K1_oSEG7_DIG[3]); --T1L3 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[2]~72 T1L3 = K1_oSEG7_DIG[2] & K1_oSEG7_DIG[3] & (K1_oSEG7_DIG[1] # !K1_oSEG7_DIG[0]) # !K1_oSEG7_DIG[2] & !K1_oSEG7_DIG[0] & K1_oSEG7_DIG[1] & !K1_oSEG7_DIG[3]; --T1L4 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[3]~73 T1L4 = K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[1] $ !K1_oSEG7_DIG[2]) # !K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[1] & !K1_oSEG7_DIG[2] & K1_oSEG7_DIG[3] # !K1_oSEG7_DIG[1] & K1_oSEG7_DIG[2] & !K1_oSEG7_DIG[3]); --T1L5 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[4]~74 T1L5 = K1_oSEG7_DIG[1] & K1_oSEG7_DIG[0] & (!K1_oSEG7_DIG[3]) # !K1_oSEG7_DIG[1] & (K1_oSEG7_DIG[2] & (!K1_oSEG7_DIG[3]) # !K1_oSEG7_DIG[2] & K1_oSEG7_DIG[0]); --T1L6 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[5]~75 T1L6 = K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[3] $ (K1_oSEG7_DIG[1] # !K1_oSEG7_DIG[2])) # !K1_oSEG7_DIG[0] & K1_oSEG7_DIG[1] & !K1_oSEG7_DIG[2] & !K1_oSEG7_DIG[3]; --T1L7 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[6]~76 T1L7 = K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[3] # K1_oSEG7_DIG[1] $ K1_oSEG7_DIG[2]) # !K1_oSEG7_DIG[0] & (K1_oSEG7_DIG[1] # K1_oSEG7_DIG[2] $ K1_oSEG7_DIG[3]); --K1_oSEG7_DIG[4] is CMD_Decode:u5|oSEG7_DIG[4] K1_oSEG7_DIG[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[5] is CMD_Decode:u5|oSEG7_DIG[5] K1_oSEG7_DIG[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[6] is CMD_Decode:u5|oSEG7_DIG[6] K1_oSEG7_DIG[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[7] is CMD_Decode:u5|oSEG7_DIG[7] K1_oSEG7_DIG[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L407, , , , ); --T2L1 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[0]~70 T2L1 = K1_oSEG7_DIG[6] & !K1_oSEG7_DIG[5] & (K1_oSEG7_DIG[4] $ !K1_oSEG7_DIG[7]) # !K1_oSEG7_DIG[6] & K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[5] $ !K1_oSEG7_DIG[7]); --T2L2 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[1]~71 T2L2 = K1_oSEG7_DIG[5] & (K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[7]) # !K1_oSEG7_DIG[4] & K1_oSEG7_DIG[6]) # !K1_oSEG7_DIG[5] & K1_oSEG7_DIG[6] & (K1_oSEG7_DIG[4] $ K1_oSEG7_DIG[7]); --T2L3 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[2]~72 T2L3 = K1_oSEG7_DIG[6] & K1_oSEG7_DIG[7] & (K1_oSEG7_DIG[5] # !K1_oSEG7_DIG[4]) # !K1_oSEG7_DIG[6] & !K1_oSEG7_DIG[4] & K1_oSEG7_DIG[5] & !K1_oSEG7_DIG[7]; --T2L4 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[3]~73 T2L4 = K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[5] $ !K1_oSEG7_DIG[6]) # !K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[5] & !K1_oSEG7_DIG[6] & K1_oSEG7_DIG[7] # !K1_oSEG7_DIG[5] & K1_oSEG7_DIG[6] & !K1_oSEG7_DIG[7]); --T2L5 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[4]~74 T2L5 = K1_oSEG7_DIG[5] & K1_oSEG7_DIG[4] & (!K1_oSEG7_DIG[7]) # !K1_oSEG7_DIG[5] & (K1_oSEG7_DIG[6] & (!K1_oSEG7_DIG[7]) # !K1_oSEG7_DIG[6] & K1_oSEG7_DIG[4]); --T2L6 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[5]~75 T2L6 = K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[7] $ (K1_oSEG7_DIG[5] # !K1_oSEG7_DIG[6])) # !K1_oSEG7_DIG[4] & K1_oSEG7_DIG[5] & !K1_oSEG7_DIG[6] & !K1_oSEG7_DIG[7]; --T2L7 is SEG7_LUT_4:u0|SEG7_LUT:u1|oSEG[6]~76 T2L7 = K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[7] # K1_oSEG7_DIG[5] $ K1_oSEG7_DIG[6]) # !K1_oSEG7_DIG[4] & (K1_oSEG7_DIG[5] # K1_oSEG7_DIG[6] $ K1_oSEG7_DIG[7]); --K1_oSEG7_DIG[8] is CMD_Decode:u5|oSEG7_DIG[8] K1_oSEG7_DIG[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[9] is CMD_Decode:u5|oSEG7_DIG[9] K1_oSEG7_DIG[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[10] is CMD_Decode:u5|oSEG7_DIG[10] K1_oSEG7_DIG[10] = DFFEAS(K1_CMD_Tmp[18], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[11] is CMD_Decode:u5|oSEG7_DIG[11] K1_oSEG7_DIG[11] = DFFEAS(K1_CMD_Tmp[19], CLOCK_50, KEY[0], , K1L407, , , , ); --T3L1 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[0]~70 T3L1 = K1_oSEG7_DIG[10] & !K1_oSEG7_DIG[9] & (K1_oSEG7_DIG[8] $ !K1_oSEG7_DIG[11]) # !K1_oSEG7_DIG[10] & K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[9] $ !K1_oSEG7_DIG[11]); --T3L2 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[1]~71 T3L2 = K1_oSEG7_DIG[9] & (K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[11]) # !K1_oSEG7_DIG[8] & K1_oSEG7_DIG[10]) # !K1_oSEG7_DIG[9] & K1_oSEG7_DIG[10] & (K1_oSEG7_DIG[8] $ K1_oSEG7_DIG[11]); --T3L3 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[2]~72 T3L3 = K1_oSEG7_DIG[10] & K1_oSEG7_DIG[11] & (K1_oSEG7_DIG[9] # !K1_oSEG7_DIG[8]) # !K1_oSEG7_DIG[10] & !K1_oSEG7_DIG[8] & K1_oSEG7_DIG[9] & !K1_oSEG7_DIG[11]; --T3L4 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[3]~73 T3L4 = K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[9] $ !K1_oSEG7_DIG[10]) # !K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[9] & !K1_oSEG7_DIG[10] & K1_oSEG7_DIG[11] # !K1_oSEG7_DIG[9] & K1_oSEG7_DIG[10] & !K1_oSEG7_DIG[11]); --T3L5 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[4]~74 T3L5 = K1_oSEG7_DIG[9] & K1_oSEG7_DIG[8] & (!K1_oSEG7_DIG[11]) # !K1_oSEG7_DIG[9] & (K1_oSEG7_DIG[10] & (!K1_oSEG7_DIG[11]) # !K1_oSEG7_DIG[10] & K1_oSEG7_DIG[8]); --T3L6 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[5]~75 T3L6 = K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[11] $ (K1_oSEG7_DIG[9] # !K1_oSEG7_DIG[10])) # !K1_oSEG7_DIG[8] & K1_oSEG7_DIG[9] & !K1_oSEG7_DIG[10] & !K1_oSEG7_DIG[11]; --T3L7 is SEG7_LUT_4:u0|SEG7_LUT:u2|oSEG[6]~76 T3L7 = K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[11] # K1_oSEG7_DIG[9] $ K1_oSEG7_DIG[10]) # !K1_oSEG7_DIG[8] & (K1_oSEG7_DIG[9] # K1_oSEG7_DIG[10] $ K1_oSEG7_DIG[11]); --K1_oSEG7_DIG[12] is CMD_Decode:u5|oSEG7_DIG[12] K1_oSEG7_DIG[12] = DFFEAS(K1_CMD_Tmp[20], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[13] is CMD_Decode:u5|oSEG7_DIG[13] K1_oSEG7_DIG[13] = DFFEAS(K1_CMD_Tmp[21], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[14] is CMD_Decode:u5|oSEG7_DIG[14] K1_oSEG7_DIG[14] = DFFEAS(K1_CMD_Tmp[22], CLOCK_50, KEY[0], , K1L407, , , , ); --K1_oSEG7_DIG[15] is CMD_Decode:u5|oSEG7_DIG[15] K1_oSEG7_DIG[15] = DFFEAS(K1_CMD_Tmp[23], CLOCK_50, KEY[0], , K1L407, , , , ); --T4L1 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[0]~70 T4L1 = K1_oSEG7_DIG[14] & !K1_oSEG7_DIG[13] & (K1_oSEG7_DIG[12] $ !K1_oSEG7_DIG[15]) # !K1_oSEG7_DIG[14] & K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[13] $ !K1_oSEG7_DIG[15]); --T4L2 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[1]~71 T4L2 = K1_oSEG7_DIG[13] & (K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[15]) # !K1_oSEG7_DIG[12] & K1_oSEG7_DIG[14]) # !K1_oSEG7_DIG[13] & K1_oSEG7_DIG[14] & (K1_oSEG7_DIG[12] $ K1_oSEG7_DIG[15]); --T4L3 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[2]~72 T4L3 = K1_oSEG7_DIG[14] & K1_oSEG7_DIG[15] & (K1_oSEG7_DIG[13] # !K1_oSEG7_DIG[12]) # !K1_oSEG7_DIG[14] & !K1_oSEG7_DIG[12] & K1_oSEG7_DIG[13] & !K1_oSEG7_DIG[15]; --T4L4 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[3]~73 T4L4 = K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[13] $ !K1_oSEG7_DIG[14]) # !K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[13] & !K1_oSEG7_DIG[14] & K1_oSEG7_DIG[15] # !K1_oSEG7_DIG[13] & K1_oSEG7_DIG[14] & !K1_oSEG7_DIG[15]); --T4L5 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[4]~74 T4L5 = K1_oSEG7_DIG[13] & K1_oSEG7_DIG[12] & (!K1_oSEG7_DIG[15]) # !K1_oSEG7_DIG[13] & (K1_oSEG7_DIG[14] & (!K1_oSEG7_DIG[15]) # !K1_oSEG7_DIG[14] & K1_oSEG7_DIG[12]); --T4L6 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[5]~75 T4L6 = K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[15] $ (K1_oSEG7_DIG[13] # !K1_oSEG7_DIG[14])) # !K1_oSEG7_DIG[12] & K1_oSEG7_DIG[13] & !K1_oSEG7_DIG[14] & !K1_oSEG7_DIG[15]; --T4L7 is SEG7_LUT_4:u0|SEG7_LUT:u3|oSEG[6]~76 T4L7 = K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[15] # K1_oSEG7_DIG[13] $ K1_oSEG7_DIG[14]) # !K1_oSEG7_DIG[12] & (K1_oSEG7_DIG[13] # K1_oSEG7_DIG[14] $ K1_oSEG7_DIG[15]); --K1_oLED_GREEN[0] is CMD_Decode:u5|oLED_GREEN[0] K1_oLED_GREEN[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[1] is CMD_Decode:u5|oLED_GREEN[1] K1_oLED_GREEN[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[2] is CMD_Decode:u5|oLED_GREEN[2] K1_oLED_GREEN[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[3] is CMD_Decode:u5|oLED_GREEN[3] K1_oLED_GREEN[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[4] is CMD_Decode:u5|oLED_GREEN[4] K1_oLED_GREEN[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[5] is CMD_Decode:u5|oLED_GREEN[5] K1_oLED_GREEN[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[6] is CMD_Decode:u5|oLED_GREEN[6] K1_oLED_GREEN[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_GREEN[7] is CMD_Decode:u5|oLED_GREEN[7] K1_oLED_GREEN[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[0] is CMD_Decode:u5|oLED_RED[0] K1_oLED_RED[0] = DFFEAS(K1_CMD_Tmp[24], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[1] is CMD_Decode:u5|oLED_RED[1] K1_oLED_RED[1] = DFFEAS(K1_CMD_Tmp[25], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[2] is CMD_Decode:u5|oLED_RED[2] K1_oLED_RED[2] = DFFEAS(K1_CMD_Tmp[26], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[3] is CMD_Decode:u5|oLED_RED[3] K1_oLED_RED[3] = DFFEAS(K1_CMD_Tmp[27], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[4] is CMD_Decode:u5|oLED_RED[4] K1_oLED_RED[4] = DFFEAS(K1_CMD_Tmp[28], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[5] is CMD_Decode:u5|oLED_RED[5] K1_oLED_RED[5] = DFFEAS(K1_CMD_Tmp[29], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[6] is CMD_Decode:u5|oLED_RED[6] K1_oLED_RED[6] = DFFEAS(K1_CMD_Tmp[30], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[7] is CMD_Decode:u5|oLED_RED[7] K1_oLED_RED[7] = DFFEAS(K1_CMD_Tmp[31], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[8] is CMD_Decode:u5|oLED_RED[8] K1_oLED_RED[8] = DFFEAS(K1_CMD_Tmp[32], CLOCK_50, KEY[0], , K1L316, , , , ); --K1_oLED_RED[9] is CMD_Decode:u5|oLED_RED[9] K1_oLED_RED[9] = DFFEAS(K1_CMD_Tmp[33], CLOCK_50, KEY[0], , K1L316, , , , ); --Z1_SA[0] is Multi_Sdram:u3|Sdram_Controller:u1|SA[0] Z1_SA[0] = DFFEAS(Z1L67, S1__clk0, , , , , , , ); --Z1_SA[1] is Multi_Sdram:u3|Sdram_Controller:u1|SA[1] Z1_SA[1] = DFFEAS(Z1L68, S1__clk0, , , , , , , ); --Z1_SA[2] is Multi_Sdram:u3|Sdram_Controller:u1|SA[2] Z1_SA[2] = DFFEAS(Z1L69, S1__clk0, , , , , , , ); --Z1_SA[3] is Multi_Sdram:u3|Sdram_Controller:u1|SA[3] Z1_SA[3] = DFFEAS(Z1L70, S1__clk0, , , , , , , ); --Z1_SA[4] is Multi_Sdram:u3|Sdram_Controller:u1|SA[4] Z1_SA[4] = DFFEAS(Z1L71, S1__clk0, , , , , , , ); --Z1_SA[5] is Multi_Sdram:u3|Sdram_Controller:u1|SA[5] Z1_SA[5] = DFFEAS(Z1L72, S1__clk0, , , , , , , ); --Z1_SA[6] is Multi_Sdram:u3|Sdram_Controller:u1|SA[6] Z1_SA[6] = DFFEAS(Z1L73, S1__clk0, , , , , , , ); --Z1_SA[7] is Multi_Sdram:u3|Sdram_Controller:u1|SA[7] Z1_SA[7] = DFFEAS(Z1L74, S1__clk0, , , , , , , ); --Z1_SA[8] is Multi_Sdram:u3|Sdram_Controller:u1|SA[8] Z1_SA[8] = DFFEAS(Z1L75, S1__clk0, , , , , , , ); --Z1_SA[9] is Multi_Sdram:u3|Sdram_Controller:u1|SA[9] Z1_SA[9] = DFFEAS(Z1L76, S1__clk0, , , , , , , ); --Z1_SA[10] is Multi_Sdram:u3|Sdram_Controller:u1|SA[10] Z1_SA[10] = DFFEAS(Z1L77, S1__clk0, , , , , , , ); --Z1_SA[11] is Multi_Sdram:u3|Sdram_Controller:u1|SA[11] Z1_SA[11] = DFFEAS(Z1L78, S1__clk0, , , , , , , ); --Z1_DQM[1] is Multi_Sdram:u3|Sdram_Controller:u1|DQM[1] Z1_DQM[1] = DFFEAS(Z1L34, S1__clk0, , , , , , , ); --Z1_WE_N is Multi_Sdram:u3|Sdram_Controller:u1|WE_N Z1_WE_N = DFFEAS(Z1L105, S1__clk0, , , , , , , ); --Z1_CAS_N is Multi_Sdram:u3|Sdram_Controller:u1|CAS_N Z1_CAS_N = DFFEAS(Z1L5, S1__clk0, , , , , , , ); --Z1_RAS_N is Multi_Sdram:u3|Sdram_Controller:u1|RAS_N Z1_RAS_N = DFFEAS(Z1L50, S1__clk0, , , , , , , ); --Z1_CS_N[0] is Multi_Sdram:u3|Sdram_Controller:u1|CS_N[0] Z1_CS_N[0] = DFFEAS(AB1_CS_N[0], S1__clk0, , , , , , , ); --Z1_BA[0] is Multi_Sdram:u3|Sdram_Controller:u1|BA[0] Z1_BA[0] = DFFEAS(AB1_BA[0], S1__clk0, , , , , , , ); --Z1_BA[1] is Multi_Sdram:u3|Sdram_Controller:u1|BA[1] Z1_BA[1] = DFFEAS(AB1_BA[1], S1__clk0, , , , , , , ); --S1__clk0 is Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 S1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK()); --S1__clk2 is Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk2 S1__clk2 = PLL.CLK2(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK()); --X1_r_ADDR[0] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[0] X1_r_ADDR[0] = DFFEAS(W1L31, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_ST.P4_PRG is Multi_Flash:u2|Flash_Controller:u1|ST.P4_PRG X1_ST.P4_PRG = DFFEAS(X1L139, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.READ is Multi_Flash:u2|Flash_Controller:u1|ST.READ X1_ST.READ = DFFEAS(X1L140, CLOCK_50, KEY[0], , X1L141, , , , ); --X1L107 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR~0 X1L107 = X1_ST.P4_PRG # X1_ST.READ; --X1_ST.P2 is Multi_Flash:u2|Flash_Controller:u1|ST.P2 X1_ST.P2 = DFFEAS(X1L142, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.P5 is Multi_Flash:u2|Flash_Controller:u1|ST.P5 X1_ST.P5 = DFFEAS(X1L150, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L137 is Multi_Flash:u2|Flash_Controller:u1|ST~410 X1L137 = !X1_ST.P2 & !X1_ST.P5; --X1_r_ADDR[1] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[1] X1_r_ADDR[1] = DFFEAS(W1L32, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_ST.P3 is Multi_Flash:u2|Flash_Controller:u1|ST.P3 X1_ST.P3 = DFFEAS(X1L143, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.P3_PRG is Multi_Flash:u2|Flash_Controller:u1|ST.P3_PRG X1_ST.P3_PRG = DFFEAS(X1L144, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.P4 is Multi_Flash:u2|Flash_Controller:u1|ST.P4 X1_ST.P4 = DFFEAS(X1L145, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.P1 is Multi_Flash:u2|Flash_Controller:u1|ST.P1 X1_ST.P1 = DFFEAS(X1L146, CLOCK_50, KEY[0], , X1L141, , , , ); --X1L138 is Multi_Flash:u2|Flash_Controller:u1|ST~411 X1L138 = !X1_ST.P3 & !X1_ST.P3_PRG & !X1_ST.P4 & !X1_ST.P1; --X1_ST.P6_CHP_ERA is Multi_Flash:u2|Flash_Controller:u1|ST.P6_CHP_ERA X1_ST.P6_CHP_ERA = DFFEAS(X1L147, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1_ST.P3_DEV is Multi_Flash:u2|Flash_Controller:u1|ST.P3_DEV X1_ST.P3_DEV = DFFEAS(X1L148, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1L253 is Multi_Flash:u2|Flash_Controller:u1|reduce_or~110 X1L253 = !X1_ST.P6_CHP_ERA & !X1_ST.P3_DEV; --X1L86 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[1]~1100 X1L86 = X1L107 & X1_r_ADDR[1] # !X1L253 # !X1L138; --X1_r_ADDR[2] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[2] X1_r_ADDR[2] = DFFEAS(W1L33, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_r_ADDR[3] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[3] X1_r_ADDR[3] = DFFEAS(W1L34, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L88 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[3]~1101 X1L88 = X1L107 & X1_r_ADDR[3] # !X1L253 # !X1L138; --X1_r_ADDR[4] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[4] X1_r_ADDR[4] = DFFEAS(W1L35, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_r_ADDR[5] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[5] X1_r_ADDR[5] = DFFEAS(W1L36, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L90 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[5]~1102 X1L90 = X1L107 & X1_r_ADDR[5] # !X1L253 # !X1L138; --X1_r_ADDR[6] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[6] X1_r_ADDR[6] = DFFEAS(W1L37, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_r_ADDR[7] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[7] X1_r_ADDR[7] = DFFEAS(W1L38, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L92 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[7]~1103 X1L92 = X1L107 & X1_r_ADDR[7] # !X1L253 # !X1L138; --X1_r_ADDR[8] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[8] X1_r_ADDR[8] = DFFEAS(W1L39, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_r_ADDR[9] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[9] X1_r_ADDR[9] = DFFEAS(W1L40, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L94 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[9]~1104 X1L94 = X1L107 & X1_r_ADDR[9] # !X1L253 # !X1L138; --X1_r_ADDR[10] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[10] X1_r_ADDR[10] = DFFEAS(W1L41, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1_r_ADDR[11] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[11] X1_r_ADDR[11] = DFFEAS(W1L42, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L96 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[11]~1105 X1L96 = X1L107 & X1_r_ADDR[11] # !X1L253 # !X1L138; --X1_r_ADDR[12] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[12] X1_r_ADDR[12] = DFFEAS(W1L43, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L97 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[12]~1106 X1L97 = X1_r_ADDR[12] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[13] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[13] X1_r_ADDR[13] = DFFEAS(W1L44, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L98 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[13]~1107 X1L98 = X1_r_ADDR[13] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[14] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[14] X1_r_ADDR[14] = DFFEAS(W1L45, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L99 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[14]~1108 X1L99 = X1_r_ADDR[14] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[15] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[15] X1_r_ADDR[15] = DFFEAS(W1L46, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L100 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[15]~1109 X1L100 = X1_r_ADDR[15] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[16] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[16] X1_r_ADDR[16] = DFFEAS(W1L47, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L101 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[16]~1110 X1L101 = X1_r_ADDR[16] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[17] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[17] X1_r_ADDR[17] = DFFEAS(W1L48, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L102 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[17]~1111 X1L102 = X1_r_ADDR[17] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[18] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[18] X1_r_ADDR[18] = DFFEAS(W1L49, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L103 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[18]~1112 X1L103 = X1_r_ADDR[18] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[19] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[19] X1_r_ADDR[19] = DFFEAS(W1L50, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L104 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[19]~1113 X1L104 = X1_r_ADDR[19] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[20] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[20] X1_r_ADDR[20] = DFFEAS(W1L51, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L105 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[20]~1114 X1L105 = X1_r_ADDR[20] & (X1_ST.P4_PRG # X1_ST.READ); --X1_r_ADDR[21] is Multi_Flash:u2|Flash_Controller:u1|r_ADDR[21] X1_r_ADDR[21] = DFFEAS(W1L52, CLOCK_50, , , X1L243, , , K1_oFL_Select[1], ); --X1L106 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[21]~1115 X1L106 = X1_r_ADDR[21] & (X1_ST.P4_PRG # X1_ST.READ); --X1_WE_CLK_Delay[4] is Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[4] X1_WE_CLK_Delay[4] = DFFEAS(X1_WE_CLK_Delay[3], CLOCK_50, KEY[0], , , , , , ); --X1_ST.IDEL is Multi_Flash:u2|Flash_Controller:u1|ST.IDEL X1_ST.IDEL = DFFEAS(X1L149, CLOCK_50, KEY[0], , X1_mACT, , , , ); --X1L108 is Multi_Flash:u2|Flash_Controller:u1|FL_WE_n~17 X1L108 = X1_ST.READ # !X1_ST.IDEL # !X1_WE_CLK_Delay[4]; --M1_oAddress[1] is VGA_Controller:u8|oAddress[1] M1_oAddress[1] = DFFEAS(M1L339, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[0] is CMD_Decode:u5|oSR_ADDR[0] K1_oSR_ADDR[0] = DFFEAS(K1_CMD_Tmp[24], CLOCK_50, , , K1L425, , , , ); --K1_oSR_Select[0] is CMD_Decode:u5|oSR_Select[0] K1_oSR_Select[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L464, , , , ); --K1_oSR_Select[1] is CMD_Decode:u5|oSR_Select[1] K1_oSR_Select[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L464, , , , ); --L1L3 is Multi_Sram:u6|SRAM_ADDR[0]~1080 L1L3 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[1] # !K1_oSR_Select[0] & (K1_oSR_ADDR[0])); --M1_oAddress[2] is VGA_Controller:u8|oAddress[2] M1_oAddress[2] = DFFEAS(M1L342, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[1] is CMD_Decode:u5|oSR_ADDR[1] K1_oSR_ADDR[1] = DFFEAS(K1_CMD_Tmp[25], CLOCK_50, , , K1L425, , , , ); --L1L4 is Multi_Sram:u6|SRAM_ADDR[1]~1081 L1L4 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[2] # !K1_oSR_Select[0] & (K1_oSR_ADDR[1])); --M1_oAddress[3] is VGA_Controller:u8|oAddress[3] M1_oAddress[3] = DFFEAS(M1L345, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[2] is CMD_Decode:u5|oSR_ADDR[2] K1_oSR_ADDR[2] = DFFEAS(K1_CMD_Tmp[26], CLOCK_50, , , K1L425, , , , ); --L1L5 is Multi_Sram:u6|SRAM_ADDR[2]~1082 L1L5 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[3] # !K1_oSR_Select[0] & (K1_oSR_ADDR[2])); --M1_oAddress[4] is VGA_Controller:u8|oAddress[4] M1_oAddress[4] = DFFEAS(M1L348, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[3] is CMD_Decode:u5|oSR_ADDR[3] K1_oSR_ADDR[3] = DFFEAS(K1_CMD_Tmp[27], CLOCK_50, , , K1L425, , , , ); --L1L6 is Multi_Sram:u6|SRAM_ADDR[3]~1083 L1L6 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[4] # !K1_oSR_Select[0] & (K1_oSR_ADDR[3])); --M1_oAddress[5] is VGA_Controller:u8|oAddress[5] M1_oAddress[5] = DFFEAS(M1L351, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[4] is CMD_Decode:u5|oSR_ADDR[4] K1_oSR_ADDR[4] = DFFEAS(K1_CMD_Tmp[28], CLOCK_50, , , K1L425, , , , ); --L1L7 is Multi_Sram:u6|SRAM_ADDR[4]~1084 L1L7 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[5] # !K1_oSR_Select[0] & (K1_oSR_ADDR[4])); --M1_oAddress[6] is VGA_Controller:u8|oAddress[6] M1_oAddress[6] = DFFEAS(M1L354, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[5] is CMD_Decode:u5|oSR_ADDR[5] K1_oSR_ADDR[5] = DFFEAS(K1_CMD_Tmp[29], CLOCK_50, , , K1L425, , , , ); --L1L8 is Multi_Sram:u6|SRAM_ADDR[5]~1085 L1L8 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[6] # !K1_oSR_Select[0] & (K1_oSR_ADDR[5])); --M1_oAddress[7] is VGA_Controller:u8|oAddress[7] M1_oAddress[7] = DFFEAS(M1L357, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[6] is CMD_Decode:u5|oSR_ADDR[6] K1_oSR_ADDR[6] = DFFEAS(K1_CMD_Tmp[30], CLOCK_50, , , K1L425, , , , ); --L1L9 is Multi_Sram:u6|SRAM_ADDR[6]~1086 L1L9 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[7] # !K1_oSR_Select[0] & (K1_oSR_ADDR[6])); --M1_oAddress[8] is VGA_Controller:u8|oAddress[8] M1_oAddress[8] = DFFEAS(M1L360, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[7] is CMD_Decode:u5|oSR_ADDR[7] K1_oSR_ADDR[7] = DFFEAS(K1_CMD_Tmp[31], CLOCK_50, , , K1L425, , , , ); --L1L10 is Multi_Sram:u6|SRAM_ADDR[7]~1087 L1L10 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[8] # !K1_oSR_Select[0] & (K1_oSR_ADDR[7])); --M1_oAddress[9] is VGA_Controller:u8|oAddress[9] M1_oAddress[9] = DFFEAS(M1L363, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[8] is CMD_Decode:u5|oSR_ADDR[8] K1_oSR_ADDR[8] = DFFEAS(K1_CMD_Tmp[32], CLOCK_50, , , K1L425, , , , ); --L1L11 is Multi_Sram:u6|SRAM_ADDR[8]~1088 L1L11 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[9] # !K1_oSR_Select[0] & (K1_oSR_ADDR[8])); --M1_oAddress[10] is VGA_Controller:u8|oAddress[10] M1_oAddress[10] = DFFEAS(M1L366, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[9] is CMD_Decode:u5|oSR_ADDR[9] K1_oSR_ADDR[9] = DFFEAS(K1_CMD_Tmp[33], CLOCK_50, , , K1L425, , , , ); --L1L12 is Multi_Sram:u6|SRAM_ADDR[9]~1089 L1L12 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[10] # !K1_oSR_Select[0] & (K1_oSR_ADDR[9])); --M1_oAddress[11] is VGA_Controller:u8|oAddress[11] M1_oAddress[11] = DFFEAS(M1L369, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[10] is CMD_Decode:u5|oSR_ADDR[10] K1_oSR_ADDR[10] = DFFEAS(K1_CMD_Tmp[34], CLOCK_50, , , K1L425, , , , ); --L1L13 is Multi_Sram:u6|SRAM_ADDR[10]~1090 L1L13 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[11] # !K1_oSR_Select[0] & (K1_oSR_ADDR[10])); --M1_oAddress[12] is VGA_Controller:u8|oAddress[12] M1_oAddress[12] = DFFEAS(M1L372, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[11] is CMD_Decode:u5|oSR_ADDR[11] K1_oSR_ADDR[11] = DFFEAS(K1_CMD_Tmp[35], CLOCK_50, , , K1L425, , , , ); --L1L14 is Multi_Sram:u6|SRAM_ADDR[11]~1091 L1L14 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[12] # !K1_oSR_Select[0] & (K1_oSR_ADDR[11])); --M1_oAddress[13] is VGA_Controller:u8|oAddress[13] M1_oAddress[13] = DFFEAS(M1L375, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[12] is CMD_Decode:u5|oSR_ADDR[12] K1_oSR_ADDR[12] = DFFEAS(K1_CMD_Tmp[36], CLOCK_50, , , K1L425, , , , ); --L1L15 is Multi_Sram:u6|SRAM_ADDR[12]~1092 L1L15 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[13] # !K1_oSR_Select[0] & (K1_oSR_ADDR[12])); --M1_oAddress[14] is VGA_Controller:u8|oAddress[14] M1_oAddress[14] = DFFEAS(M1L378, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[13] is CMD_Decode:u5|oSR_ADDR[13] K1_oSR_ADDR[13] = DFFEAS(K1_CMD_Tmp[37], CLOCK_50, , , K1L425, , , , ); --L1L16 is Multi_Sram:u6|SRAM_ADDR[13]~1093 L1L16 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[14] # !K1_oSR_Select[0] & (K1_oSR_ADDR[13])); --M1_oAddress[15] is VGA_Controller:u8|oAddress[15] M1_oAddress[15] = DFFEAS(M1L381, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[14] is CMD_Decode:u5|oSR_ADDR[14] K1_oSR_ADDR[14] = DFFEAS(K1_CMD_Tmp[38], CLOCK_50, , , K1L425, , , , ); --L1L17 is Multi_Sram:u6|SRAM_ADDR[14]~1094 L1L17 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[15] # !K1_oSR_Select[0] & (K1_oSR_ADDR[14])); --M1_oAddress[16] is VGA_Controller:u8|oAddress[16] M1_oAddress[16] = DFFEAS(M1L384, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[15] is CMD_Decode:u5|oSR_ADDR[15] K1_oSR_ADDR[15] = DFFEAS(K1_CMD_Tmp[39], CLOCK_50, , , K1L425, , , , ); --L1L18 is Multi_Sram:u6|SRAM_ADDR[15]~1095 L1L18 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[16] # !K1_oSR_Select[0] & (K1_oSR_ADDR[15])); --M1_oAddress[17] is VGA_Controller:u8|oAddress[17] M1_oAddress[17] = DFFEAS(M1L387, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[16] is CMD_Decode:u5|oSR_ADDR[16] K1_oSR_ADDR[16] = DFFEAS(K1_CMD_Tmp[40], CLOCK_50, , , K1L425, , , , ); --L1L19 is Multi_Sram:u6|SRAM_ADDR[16]~1096 L1L19 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[17] # !K1_oSR_Select[0] & (K1_oSR_ADDR[16])); --M1_oAddress[18] is VGA_Controller:u8|oAddress[18] M1_oAddress[18] = DFFEAS(M1L390, S2__clk0, B1_oRESET, , M1L330, , , , ); --K1_oSR_ADDR[17] is CMD_Decode:u5|oSR_ADDR[17] K1_oSR_ADDR[17] = DFFEAS(K1_CMD_Tmp[41], CLOCK_50, , , K1L425, , , , ); --L1L20 is Multi_Sram:u6|SRAM_ADDR[17]~1097 L1L20 = !K1_oSR_Select[1] & (K1_oSR_Select[0] & M1_oAddress[18] # !K1_oSR_Select[0] & (K1_oSR_ADDR[17])); --K1_mSDR_WRn is CMD_Decode:u5|mSDR_WRn K1_mSDR_WRn = DFFEAS(K1L215, CLOCK_50, KEY[0], , , , , , ); --K1_mSR_Start is CMD_Decode:u5|mSR_Start K1_mSR_Start = DFFEAS(K1L83, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --L1L38 is Multi_Sram:u6|SRAM_WE_N~56 L1L38 = K1_oSR_Select[1] # !K1_oSR_Select[0] & K1_mSDR_WRn & K1_mSR_Start; --L1L37 is Multi_Sram:u6|SRAM_OE_N~34 L1L37 = !K1_oSR_Select[1] & !K1_oSR_Select[0] & (K1_mSDR_WRn # !K1_mSR_Start); --V1_TDO is USB_JTAG:u1|JTAG_TRANS:u1|TDO V1_TDO = DFFEAS(V1L7, R1_wire_clkctrl1_outclk, !TCS, , , , , , ); --MB1L40Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0]~reg0 MB1L40Q = DFFEAS(MB1L38, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --MB1L46Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2]~reg0 MB1L46Q = DFFEAS(MB1L44, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --MB1L49Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3]~reg0 MB1L49Q = DFFEAS(MB1L47, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --MB1L43Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1]~reg0 MB1L43Q = DFFEAS(MB1L41, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --MB1L15 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~253 MB1L15 = MB1L40Q # MB1L46Q # MB1L49Q # MB1L43Q; --MB1L52Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4]~reg0 MB1L52Q = DFFEAS(MB1L50, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --MB1L16 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~254 MB1L16 = MB1L52Q & (!MB1L49Q # !MB1L46Q) # !MB1L52Q & MB1L15; --MB1L55Q is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5]~reg0 MB1L55Q = DFFEAS(MB1L53, P1_mI2C_CTRL_CLK, KEY[0], , , VCC, , , !P1_mI2C_GO); --P1_mI2C_CTRL_CLK is I2C_AV_Config:u10|mI2C_CTRL_CLK P1_mI2C_CTRL_CLK = DFFEAS(P1L72, CLOCK_50, KEY[0], , , , , , ); --MB1_SCLK is I2C_AV_Config:u10|I2C_Controller:u0|SCLK MB1_SCLK = DFFEAS(MB1L23, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --MB1L17 is I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~255 MB1L17 = MB1L16 & MB1L55Q & !P1_mI2C_CTRL_CLK # !MB1_SCLK; --M1_oVGA_H_SYNC is VGA_Controller:u8|oVGA_H_SYNC M1_oVGA_H_SYNC = DFFEAS(M1L116, S2__clk0, B1_oRESET, , , , , , ); --M1_oVGA_V_SYNC is VGA_Controller:u8|oVGA_V_SYNC M1_oVGA_V_SYNC = DFFEAS(M1L465, S2__clk0, B1_oRESET, , , , , , ); --M1_Cur_Color_R[6] is VGA_Controller:u8|Cur_Color_R[6] M1_Cur_Color_R[6] = DFFEAS(M1L23, S2__clk0, B1_oRESET, , , K1_oCursor_R[6], , , M1L7); --M1_H_Cont[5] is VGA_Controller:u8|H_Cont[5] M1_H_Cont[5] = DFFEAS(M1L96, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[6] is VGA_Controller:u8|H_Cont[6] M1_H_Cont[6] = DFFEAS(M1L99, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1L34 is VGA_Controller:u8|Equal~1112 M1L34 = !M1_H_Cont[5] & !M1_H_Cont[6]; --M1_H_Cont[0] is VGA_Controller:u8|H_Cont[0] M1_H_Cont[0] = DFFEAS(M1L81, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[1] is VGA_Controller:u8|H_Cont[1] M1_H_Cont[1] = DFFEAS(M1L84, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[2] is VGA_Controller:u8|H_Cont[2] M1_H_Cont[2] = DFFEAS(M1L87, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[3] is VGA_Controller:u8|H_Cont[3] M1_H_Cont[3] = DFFEAS(M1L90, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[4] is VGA_Controller:u8|H_Cont[4] M1_H_Cont[4] = DFFEAS(M1L93, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1L110 is VGA_Controller:u8|LessThan~1411 M1L110 = M1_H_Cont[2] & M1_H_Cont[3] & M1_H_Cont[4]; --M1L111 is VGA_Controller:u8|LessThan~1412 M1L111 = M1L34 & (!M1_H_Cont[0] & !M1_H_Cont[1] # !M1L110); --M1_H_Cont[7] is VGA_Controller:u8|H_Cont[7] M1_H_Cont[7] = DFFEAS(M1L102, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[8] is VGA_Controller:u8|H_Cont[8] M1_H_Cont[8] = DFFEAS(M1L105, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1_H_Cont[9] is VGA_Controller:u8|H_Cont[9] M1_H_Cont[9] = DFFEAS(M1L108, S2__clk0, B1_oRESET, , , , , M1L118, ); --M1L462 is VGA_Controller:u8|oVGA_R~315 M1L462 = M1L111 & !M1_H_Cont[7] # !M1_H_Cont[9] # !M1_H_Cont[8]; --M1_V_Cont[6] is VGA_Controller:u8|V_Cont[6] M1_V_Cont[6] = DFFEAS(M1L144, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1_V_Cont[7] is VGA_Controller:u8|V_Cont[7] M1_V_Cont[7] = DFFEAS(M1L147, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1_V_Cont[8] is VGA_Controller:u8|V_Cont[8] M1_V_Cont[8] = DFFEAS(M1L150, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1L112 is VGA_Controller:u8|LessThan~1413 M1L112 = !M1_V_Cont[6] & !M1_V_Cont[7] & !M1_V_Cont[8]; --M1_V_Cont[1] is VGA_Controller:u8|V_Cont[1] M1_V_Cont[1] = DFFEAS(M1L129, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1_V_Cont[2] is VGA_Controller:u8|V_Cont[2] M1_V_Cont[2] = DFFEAS(M1L132, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1_V_Cont[3] is VGA_Controller:u8|V_Cont[3] M1_V_Cont[3] = DFFEAS(M1L135, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1L113 is VGA_Controller:u8|LessThan~1414 M1L113 = !M1_V_Cont[1] & !M1_V_Cont[2] & !M1_V_Cont[3]; --M1_V_Cont[4] is VGA_Controller:u8|V_Cont[4] M1_V_Cont[4] = DFFEAS(M1L138, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1_V_Cont[5] is VGA_Controller:u8|V_Cont[5] M1_V_Cont[5] = DFFEAS(M1L141, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1L114 is VGA_Controller:u8|LessThan~1415 M1L114 = M1L113 & !M1_V_Cont[4] # !M1_V_Cont[5]; --M1_V_Cont[9] is VGA_Controller:u8|V_Cont[9] M1_V_Cont[9] = DFFEAS(M1L153, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --M1L115 is VGA_Controller:u8|LessThan~1416 M1L115 = M1_V_Cont[4] # M1_V_Cont[5] # !M1L113 # !M1L112; --M1L463 is VGA_Controller:u8|oVGA_R~316 M1L463 = M1_V_Cont[9] & (!M1L115) # !M1_V_Cont[9] & (!M1L114 # !M1L112); --M1L35 is VGA_Controller:u8|Equal~1113 M1L35 = !M1_H_Cont[8] & !M1_H_Cont[9]; --M1L458 is VGA_Controller:u8|oVGA_R[6]~317 M1L458 = M1_Cur_Color_R[6] & M1L462 & M1L463 & !M1L122; --M1_Cur_Color_R[7] is VGA_Controller:u8|Cur_Color_R[7] M1_Cur_Color_R[7] = DFFEAS(M1L26, S2__clk0, B1_oRESET, , , K1_oCursor_R[7], , , M1L7); --M1L459 is VGA_Controller:u8|oVGA_R[7]~318 M1L459 = M1L462 & M1L463 & M1_Cur_Color_R[7] & !M1L122; --M1_Cur_Color_R[8] is VGA_Controller:u8|Cur_Color_R[8] M1_Cur_Color_R[8] = DFFEAS(M1L29, S2__clk0, B1_oRESET, , , K1_oCursor_R[8], , , M1L7); --M1L460 is VGA_Controller:u8|oVGA_R[8]~319 M1L460 = M1L462 & M1L463 & M1_Cur_Color_R[8] & !M1L122; --M1_Cur_Color_R[9] is VGA_Controller:u8|Cur_Color_R[9] M1_Cur_Color_R[9] = DFFEAS(M1L32, S2__clk0, B1_oRESET, , , K1_oCursor_R[9], , , M1L7); --M1L461 is VGA_Controller:u8|oVGA_R[9]~320 M1L461 = M1L462 & M1L463 & M1_Cur_Color_R[9] & !M1L122; --M1_Cur_Color_G[6] is VGA_Controller:u8|Cur_Color_G[6] M1_Cur_Color_G[6] = DFFEAS(M1L17, S2__clk0, B1_oRESET, , , , , , ); --M1L453 is VGA_Controller:u8|oVGA_G[6]~60 M1L453 = M1L462 & M1L463 & M1_Cur_Color_G[6] & !M1L122; --M1_Cur_Color_G[7] is VGA_Controller:u8|Cur_Color_G[7] M1_Cur_Color_G[7] = DFFEAS(M1L18, S2__clk0, B1_oRESET, , , , , , ); --M1L454 is VGA_Controller:u8|oVGA_G[7]~61 M1L454 = M1L462 & M1L463 & M1_Cur_Color_G[7] & !M1L122; --M1_Cur_Color_G[8] is VGA_Controller:u8|Cur_Color_G[8] M1_Cur_Color_G[8] = DFFEAS(M1L19, S2__clk0, B1_oRESET, , , , , , ); --M1L455 is VGA_Controller:u8|oVGA_G[8]~62 M1L455 = M1L462 & M1L463 & M1_Cur_Color_G[8] & !M1L122; --M1_Cur_Color_G[9] is VGA_Controller:u8|Cur_Color_G[9] M1_Cur_Color_G[9] = DFFEAS(M1L20, S2__clk0, B1_oRESET, , , , , , ); --M1L456 is VGA_Controller:u8|oVGA_G[9]~63 M1L456 = M1L462 & M1L463 & M1_Cur_Color_G[9] & !M1L122; --M1_Cur_Color_B[6] is VGA_Controller:u8|Cur_Color_B[6] M1_Cur_Color_B[6] = DFFEAS(M1L8, S2__clk0, B1_oRESET, , , , , , ); --M1L449 is VGA_Controller:u8|oVGA_B[6]~60 M1L449 = M1L462 & M1L463 & M1_Cur_Color_B[6] & !M1L122; --M1_Cur_Color_B[7] is VGA_Controller:u8|Cur_Color_B[7] M1_Cur_Color_B[7] = DFFEAS(M1L9, S2__clk0, B1_oRESET, , , , , , ); --M1L450 is VGA_Controller:u8|oVGA_B[7]~61 M1L450 = M1L462 & M1L463 & M1_Cur_Color_B[7] & !M1L122; --M1_Cur_Color_B[8] is VGA_Controller:u8|Cur_Color_B[8] M1_Cur_Color_B[8] = DFFEAS(M1L10, S2__clk0, B1_oRESET, , , , , , ); --M1L451 is VGA_Controller:u8|oVGA_B[8]~62 M1L451 = M1L462 & M1L463 & M1_Cur_Color_B[8] & !M1L122; --M1_Cur_Color_B[9] is VGA_Controller:u8|Cur_Color_B[9] M1_Cur_Color_B[9] = DFFEAS(M1L11, S2__clk0, B1_oRESET, , , , , , ); --M1L452 is VGA_Controller:u8|oVGA_B[9]~63 M1L452 = M1L462 & M1L463 & M1_Cur_Color_B[9] & !M1L122; --Q1_LRCK_1X is AUDIO_DAC:u11|LRCK_1X Q1_LRCK_1X = DFFEAS(Q1L138, S2__clk1, B1_oRESET, , , , , , ); --Q1_FLASH_Out[5] is AUDIO_DAC:u11|FLASH_Out[5] Q1_FLASH_Out[5] = DFFEAS(Q1_FLASH_Out_Tmp[5], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_SEL_Cont[1] is AUDIO_DAC:u11|SEL_Cont[1] Q1_SEL_Cont[1] = DFFEAS(Q1L231, !Q1_oAUD_BCK, B1_oRESET, , , , , , ); --Q1_FLASH_Out[6] is AUDIO_DAC:u11|FLASH_Out[6] Q1_FLASH_Out[6] = DFFEAS(Q1_FLASH_Out_Tmp[6], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_SEL_Cont[0] is AUDIO_DAC:u11|SEL_Cont[0] Q1_SEL_Cont[0] = DFFEAS(Q1L229, !Q1_oAUD_BCK, B1_oRESET, , , , , , ); --Q1_FLASH_Out[7] is AUDIO_DAC:u11|FLASH_Out[7] Q1_FLASH_Out[7] = DFFEAS(Q1_FLASH_Out_Tmp[7], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L207 is AUDIO_DAC:u11|Mux~229 Q1L207 = Q1_SEL_Cont[1] & (Q1_SEL_Cont[0]) # !Q1_SEL_Cont[1] & (Q1_SEL_Cont[0] & Q1_FLASH_Out[6] # !Q1_SEL_Cont[0] & (Q1_FLASH_Out[7])); --Q1_FLASH_Out[4] is AUDIO_DAC:u11|FLASH_Out[4] Q1_FLASH_Out[4] = DFFEAS(Q1_FLASH_Out_Tmp[4], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L208 is AUDIO_DAC:u11|Mux~230 Q1L208 = Q1_SEL_Cont[1] & (Q1L207 & (Q1_FLASH_Out[4]) # !Q1L207 & Q1_FLASH_Out[5]) # !Q1_SEL_Cont[1] & (Q1L207); --Q1_SEL_Cont[3] is AUDIO_DAC:u11|SEL_Cont[3] Q1_SEL_Cont[3] = DFFEAS(Q1L235, !Q1_oAUD_BCK, B1_oRESET, , , , , , ); --Q1_FLASH_Out[10] is AUDIO_DAC:u11|FLASH_Out[10] Q1_FLASH_Out[10] = DFFEAS(Q1_FLASH_Out_Tmp[10], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[9] is AUDIO_DAC:u11|FLASH_Out[9] Q1_FLASH_Out[9] = DFFEAS(Q1_FLASH_Out_Tmp[9], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[11] is AUDIO_DAC:u11|FLASH_Out[11] Q1_FLASH_Out[11] = DFFEAS(Q1_FLASH_Out_Tmp[11], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L209 is AUDIO_DAC:u11|Mux~231 Q1L209 = Q1_SEL_Cont[0] & (Q1_SEL_Cont[1]) # !Q1_SEL_Cont[0] & (Q1_SEL_Cont[1] & Q1_FLASH_Out[9] # !Q1_SEL_Cont[1] & (Q1_FLASH_Out[11])); --Q1_FLASH_Out[8] is AUDIO_DAC:u11|FLASH_Out[8] Q1_FLASH_Out[8] = DFFEAS(Q1_FLASH_Out_Tmp[8], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L210 is AUDIO_DAC:u11|Mux~232 Q1L210 = Q1_SEL_Cont[0] & (Q1L209 & (Q1_FLASH_Out[8]) # !Q1L209 & Q1_FLASH_Out[10]) # !Q1_SEL_Cont[0] & (Q1L209); --Q1_SEL_Cont[2] is AUDIO_DAC:u11|SEL_Cont[2] Q1_SEL_Cont[2] = DFFEAS(Q1L233, !Q1_oAUD_BCK, B1_oRESET, , , , , , ); --Q1_FLASH_Out[14] is AUDIO_DAC:u11|FLASH_Out[14] Q1_FLASH_Out[14] = DFFEAS(Q1_FLASH_Out_Tmp[14], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[13] is AUDIO_DAC:u11|FLASH_Out[13] Q1_FLASH_Out[13] = DFFEAS(Q1_FLASH_Out_Tmp[13], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[15] is AUDIO_DAC:u11|FLASH_Out[15] Q1_FLASH_Out[15] = DFFEAS(Q1_FLASH_Out_Tmp[15], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L211 is AUDIO_DAC:u11|Mux~233 Q1L211 = Q1_SEL_Cont[0] & (Q1_SEL_Cont[1]) # !Q1_SEL_Cont[0] & (Q1_SEL_Cont[1] & Q1_FLASH_Out[13] # !Q1_SEL_Cont[1] & (Q1_FLASH_Out[15])); --Q1_FLASH_Out[12] is AUDIO_DAC:u11|FLASH_Out[12] Q1_FLASH_Out[12] = DFFEAS(Q1_FLASH_Out_Tmp[12], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L212 is AUDIO_DAC:u11|Mux~234 Q1L212 = Q1_SEL_Cont[0] & (Q1L211 & (Q1_FLASH_Out[12]) # !Q1L211 & Q1_FLASH_Out[14]) # !Q1_SEL_Cont[0] & (Q1L211); --Q1L213 is AUDIO_DAC:u11|Mux~235 Q1L213 = Q1_SEL_Cont[3] & (Q1_SEL_Cont[2]) # !Q1_SEL_Cont[3] & (Q1_SEL_Cont[2] & Q1L210 # !Q1_SEL_Cont[2] & (Q1L212)); --Q1_FLASH_Out[1] is AUDIO_DAC:u11|FLASH_Out[1] Q1_FLASH_Out[1] = DFFEAS(Q1_FLASH_Out_Tmp[1], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[2] is AUDIO_DAC:u11|FLASH_Out[2] Q1_FLASH_Out[2] = DFFEAS(Q1_FLASH_Out_Tmp[2], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1_FLASH_Out[3] is AUDIO_DAC:u11|FLASH_Out[3] Q1_FLASH_Out[3] = DFFEAS(Q1_FLASH_Out_Tmp[3], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L214 is AUDIO_DAC:u11|Mux~236 Q1L214 = Q1_SEL_Cont[1] & (Q1_SEL_Cont[0]) # !Q1_SEL_Cont[1] & (Q1_SEL_Cont[0] & Q1_FLASH_Out[2] # !Q1_SEL_Cont[0] & (Q1_FLASH_Out[3])); --Q1_FLASH_Out[0] is AUDIO_DAC:u11|FLASH_Out[0] Q1_FLASH_Out[0] = DFFEAS(Q1_FLASH_Out_Tmp[0], !Q1_LRCK_2X, B1_oRESET, , , , , , ); --Q1L215 is AUDIO_DAC:u11|Mux~237 Q1L215 = Q1_SEL_Cont[1] & (Q1L214 & (Q1_FLASH_Out[0]) # !Q1L214 & Q1_FLASH_Out[1]) # !Q1_SEL_Cont[1] & (Q1L214); --Q1L216 is AUDIO_DAC:u11|Mux~238 Q1L216 = Q1_SEL_Cont[3] & (Q1L213 & (Q1L215) # !Q1L213 & Q1L208) # !Q1_SEL_Cont[3] & (Q1L213); --Q1L242Q is AUDIO_DAC:u11|rom~46 Q1L242Q = DFFEAS(Q1L314, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L239Q is AUDIO_DAC:u11|rom~43 Q1L239Q = DFFEAS(Q1L308, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L240Q is AUDIO_DAC:u11|rom~44 Q1L240Q = DFFEAS(Q1L310, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L241Q is AUDIO_DAC:u11|rom~45 Q1L241Q = DFFEAS(Q1L312, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L243Q is AUDIO_DAC:u11|rom~47 Q1L243Q = DFFEAS(Q1L316, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L245 is AUDIO_DAC:u11|rom~2305 Q1L245 = !Q1L243Q & (Q1L239Q # Q1L240Q & Q1L241Q); --Q1L246 is AUDIO_DAC:u11|rom~2306 Q1L246 = Q1L243Q & (Q1L241Q $ !Q1L242Q # !Q1L240Q) # !Q1L243Q & (Q1L241Q & !Q1L242Q); --Q1L247 is AUDIO_DAC:u11|rom~2307 Q1L247 = Q1L242Q $ (!Q1L239Q & Q1L246); --Q1L244Q is AUDIO_DAC:u11|rom~48 Q1L244Q = DFFEAS(Q1L318, !Q1_LRCK_1X, B1_oRESET, , , , , Q1L194, ); --Q1L248 is AUDIO_DAC:u11|rom~2308 Q1L248 = Q1L244Q & Q1L242Q & Q1L245 # !Q1L244Q & (Q1L247); --Q1L249 is AUDIO_DAC:u11|rom~2309 Q1L249 = Q1L240Q & (Q1L239Q & (Q1L242Q # !Q1L241Q) # !Q1L239Q & (!Q1L242Q)) # !Q1L240Q & (Q1L241Q); --Q1L250 is AUDIO_DAC:u11|rom~2310 Q1L250 = Q1L244Q & (!Q1L243Q & !Q1L249) # !Q1L244Q & Q1L327; --Q1L251 is AUDIO_DAC:u11|rom~2311 Q1L251 = Q1L239Q & Q1L240Q # !Q1L239Q & (Q1L240Q & !Q1L241Q # !Q1L240Q & (Q1L242Q)); --Q1L252 is AUDIO_DAC:u11|rom~2312 Q1L252 = Q1L239Q & (Q1L242Q) # !Q1L239Q & (Q1L240Q & (Q1L242Q) # !Q1L240Q & Q1L241Q & !Q1L242Q); --Q1L253 is AUDIO_DAC:u11|rom~2313 Q1L253 = Q1L251 & !Q1L243Q & (Q1L252 # !Q1L244Q) # !Q1L251 & !Q1L244Q & (Q1L243Q # Q1L252); --Q1L217 is AUDIO_DAC:u11|Mux~239 Q1L217 = Q1_SEL_Cont[2] & (Q1_SEL_Cont[3]) # !Q1_SEL_Cont[2] & (Q1_SEL_Cont[3] & Q1L250 # !Q1_SEL_Cont[3] & (Q1L253)); --Q1L254 is AUDIO_DAC:u11|rom~2314 Q1L254 = Q1L241Q & (Q1L240Q & !Q1L239Q & Q1L242Q # !Q1L240Q & (!Q1L242Q)) # !Q1L241Q & Q1L239Q & (!Q1L242Q # !Q1L240Q); --Q1L255 is AUDIO_DAC:u11|rom~2315 Q1L255 = Q1L240Q & (Q1L239Q & (!Q1L242Q # !Q1L241Q) # !Q1L239Q & (Q1L242Q)) # !Q1L240Q & (Q1L241Q); --Q1L256 is AUDIO_DAC:u11|rom~2316 Q1L256 = Q1L243Q & Q1L254 # !Q1L243Q & (Q1L255); --Q1L257 is AUDIO_DAC:u11|rom~2317 Q1L257 = Q1L241Q & (!Q1L240Q # !Q1L239Q) # !Q1L241Q & (Q1L242Q & Q1L239Q # !Q1L242Q & (Q1L240Q)); --Q1L258 is AUDIO_DAC:u11|rom~2318 Q1L258 = Q1L244Q & (!Q1L243Q & !Q1L257) # !Q1L244Q & Q1L256; --Q1L218 is AUDIO_DAC:u11|Mux~240 Q1L218 = Q1_SEL_Cont[2] & (Q1L217 & (Q1L258) # !Q1L217 & Q1L248) # !Q1_SEL_Cont[2] & (Q1L217); --Q1L259 is AUDIO_DAC:u11|rom~2319 Q1L259 = Q1L240Q & Q1L239Q & (Q1L242Q # !Q1L241Q) # !Q1L240Q & (Q1L241Q # Q1L242Q); --Q1L260 is AUDIO_DAC:u11|rom~2320 Q1L260 = Q1L240Q $ Q1L242Q $ (Q1L239Q & !Q1L241Q); --Q1L261 is AUDIO_DAC:u11|rom~2321 Q1L261 = Q1L243Q & (!Q1L260) # !Q1L243Q & Q1L259; --Q1L262 is AUDIO_DAC:u11|rom~2322 Q1L262 = Q1L239Q & Q1L242Q & (Q1L240Q $ !Q1L241Q) # !Q1L239Q & Q1L240Q; --Q1L263 is AUDIO_DAC:u11|rom~2323 Q1L263 = Q1L244Q & (Q1L262 & !Q1L243Q) # !Q1L244Q & Q1L261; --Q1L264 is AUDIO_DAC:u11|rom~2324 Q1L264 = Q1L239Q & (Q1L241Q & Q1L242Q) # !Q1L239Q & Q1L240Q; --Q1L265 is AUDIO_DAC:u11|rom~2325 Q1L265 = Q1L239Q & (Q1L241Q # Q1L242Q) # !Q1L239Q & !Q1L240Q & (Q1L241Q # Q1L242Q); --Q1L266 is AUDIO_DAC:u11|rom~2326 Q1L266 = !Q1L243Q & (Q1L244Q & Q1L264 # !Q1L244Q & (Q1L265)); --Q1L267 is AUDIO_DAC:u11|rom~2327 Q1L267 = Q1L239Q & (Q1L241Q) # !Q1L239Q & (Q1L240Q $ (Q1L242Q)); --Q1L268 is AUDIO_DAC:u11|rom~2328 Q1L268 = Q1L266 # Q1L243Q & !Q1L244Q & !Q1L267; --Q1L269 is AUDIO_DAC:u11|rom~2329 Q1L269 = !Q1L244Q & (Q1L243Q & (Q1L242Q) # !Q1L243Q & Q1L241Q & !Q1L242Q); --Q1L270 is AUDIO_DAC:u11|rom~2330 Q1L270 = Q1L241Q & Q1L242Q & (!Q1L244Q # !Q1L243Q) # !Q1L241Q & !Q1L244Q & (Q1L243Q $ Q1L242Q); --Q1L271 is AUDIO_DAC:u11|rom~2331 Q1L271 = Q1L270 $ (Q1L269 & (Q1L239Q # Q1L240Q)); --Q1L219 is AUDIO_DAC:u11|Mux~241 Q1L219 = Q1_SEL_Cont[3] & (Q1_SEL_Cont[2]) # !Q1_SEL_Cont[3] & (Q1_SEL_Cont[2] & Q1L268 # !Q1_SEL_Cont[2] & (Q1L271)); --Q1L272 is AUDIO_DAC:u11|rom~2332 Q1L272 = Q1L241Q & !Q1L244Q & (Q1L239Q $ !Q1L240Q); --Q1L273 is AUDIO_DAC:u11|rom~2333 Q1L273 = Q1L241Q & !Q1L240Q & (Q1L239Q # !Q1L244Q) # !Q1L241Q & (Q1L244Q # Q1L239Q & Q1L240Q); --Q1L274 is AUDIO_DAC:u11|rom~2334 Q1L274 = Q1L240Q & Q1L244Q & (Q1L241Q # !Q1L239Q) # !Q1L240Q & (Q1L241Q $ (Q1L239Q # Q1L244Q)); --Q1L275 is AUDIO_DAC:u11|rom~2335 Q1L275 = Q1L243Q & (Q1L242Q) # !Q1L243Q & (Q1L242Q & Q1L273 # !Q1L242Q & (Q1L274)); --Q1L276 is AUDIO_DAC:u11|rom~2336 Q1L276 = !Q1L244Q & (Q1L239Q & (Q1L240Q # Q1L241Q) # !Q1L239Q & Q1L240Q & Q1L241Q); --Q1L277 is AUDIO_DAC:u11|rom~2337 Q1L277 = Q1L243Q & (Q1L275 & (Q1L276) # !Q1L275 & Q1L272) # !Q1L243Q & (Q1L275); --Q1L220 is AUDIO_DAC:u11|Mux~242 Q1L220 = Q1_SEL_Cont[3] & (Q1L219 & (Q1L277) # !Q1L219 & Q1L263) # !Q1_SEL_Cont[3] & (Q1L219); --Q1L278 is AUDIO_DAC:u11|rom~2338 Q1L278 = Q1L239Q & !Q1L242Q & (Q1L240Q $ !Q1L241Q) # !Q1L239Q & Q1L240Q & Q1L241Q & Q1L242Q; --Q1L279 is AUDIO_DAC:u11|rom~2339 Q1L279 = Q1L244Q & (Q1L278 & !Q1L243Q) # !Q1L244Q & Q1L325; --Q1L280 is AUDIO_DAC:u11|rom~2340 Q1L280 = Q1L240Q & Q1L241Q & (Q1L239Q # Q1L242Q) # !Q1L240Q & Q1L239Q & (Q1L242Q # !Q1L241Q); --Q1L281 is AUDIO_DAC:u11|rom~2341 Q1L281 = Q1L241Q & (!Q1L240Q # !Q1L239Q) # !Q1L241Q & Q1L242Q & (Q1L240Q # !Q1L239Q); --Q1L282 is AUDIO_DAC:u11|rom~2342 Q1L282 = !Q1L243Q & (Q1L244Q & Q1L280 # !Q1L244Q & (Q1L281)); --Q1L283 is AUDIO_DAC:u11|rom~2343 Q1L283 = Q1L240Q & Q1L241Q & (!Q1L242Q # !Q1L239Q) # !Q1L240Q & (Q1L239Q & (Q1L241Q # !Q1L242Q) # !Q1L239Q & (Q1L242Q)); --Q1L284 is AUDIO_DAC:u11|rom~2344 Q1L284 = Q1L282 # Q1L243Q & !Q1L244Q & !Q1L283; --Q1L285 is AUDIO_DAC:u11|rom~2345 Q1L285 = Q1L242Q & (Q1L239Q # Q1L240Q # Q1L241Q); --Q1L286 is AUDIO_DAC:u11|rom~2346 Q1L286 = Q1L243Q & (Q1L244Q # !Q1L285) # !Q1L243Q & !Q1L244Q; --Q1L221 is AUDIO_DAC:u11|Mux~243 Q1L221 = Q1_SEL_Cont[3] & (Q1_SEL_Cont[2]) # !Q1_SEL_Cont[3] & (Q1_SEL_Cont[2] & Q1L284 # !Q1_SEL_Cont[2] & (!Q1L286)); --Q1L287 is AUDIO_DAC:u11|rom~2347 Q1L287 = Q1L244Q # Q1L240Q & (Q1L241Q # !Q1L239Q); --Q1L288 is AUDIO_DAC:u11|rom~2348 Q1L288 = Q1L240Q & (Q1L239Q $ Q1L241Q # !Q1L244Q) # !Q1L240Q & (Q1L239Q # Q1L244Q); --Q1L289 is AUDIO_DAC:u11|rom~2349 Q1L289 = Q1L240Q & (Q1L239Q # Q1L244Q) # !Q1L240Q & (Q1L244Q & Q1L239Q # !Q1L244Q & (Q1L241Q)); --Q1L290 is AUDIO_DAC:u11|rom~2350 Q1L290 = Q1L243Q & (Q1L242Q) # !Q1L243Q & (Q1L242Q & !Q1L288 # !Q1L242Q & (Q1L289)); --Q1L291 is AUDIO_DAC:u11|rom~2351 Q1L291 = !Q1L244Q & (Q1L239Q & !Q1L240Q & !Q1L241Q # !Q1L239Q & Q1L240Q & Q1L241Q); --Q1L292 is AUDIO_DAC:u11|rom~2352 Q1L292 = Q1L243Q & (Q1L290 & (Q1L291) # !Q1L290 & !Q1L287) # !Q1L243Q & (Q1L290); --Q1L222 is AUDIO_DAC:u11|Mux~244 Q1L222 = Q1_SEL_Cont[3] & (Q1L221 & (Q1L292) # !Q1L221 & Q1L279) # !Q1_SEL_Cont[3] & (Q1L221); --Q1L223 is AUDIO_DAC:u11|Mux~245 Q1L223 = Q1_SEL_Cont[1] & (Q1_SEL_Cont[0]) # !Q1_SEL_Cont[1] & (Q1_SEL_Cont[0] & Q1L220 # !Q1_SEL_Cont[0] & (Q1L222)); --Q1L293 is AUDIO_DAC:u11|rom~2353 Q1L293 = Q1L239Q & (!Q1L241Q) # !Q1L239Q & Q1L241Q & (Q1L240Q # !Q1L242Q); --Q1L294 is AUDIO_DAC:u11|rom~2354 Q1L294 = Q1L239Q & (Q1L241Q & !Q1L242Q) # !Q1L239Q & (Q1L240Q & (Q1L242Q # !Q1L241Q) # !Q1L240Q & Q1L241Q); --Q1L295 is AUDIO_DAC:u11|rom~2355 Q1L295 = Q1L243Q & Q1L293 # !Q1L243Q & (Q1L294); --Q1L296 is AUDIO_DAC:u11|rom~2356 Q1L296 = Q1L239Q & (!Q1L241Q & Q1L242Q) # !Q1L239Q & (Q1L241Q # Q1L240Q & !Q1L242Q); --Q1L297 is AUDIO_DAC:u11|rom~2357 Q1L297 = Q1L244Q & (!Q1L243Q & !Q1L296) # !Q1L244Q & Q1L295; --Q1L298 is AUDIO_DAC:u11|rom~2358 Q1L298 = Q1L242Q & (Q1L241Q & Q1L244Q # !Q1L241Q & (Q1L243Q # !Q1L244Q)) # !Q1L242Q & (Q1L243Q); --Q1L299 is AUDIO_DAC:u11|rom~2359 Q1L299 = Q1L244Q # Q1L243Q & Q1L242Q; --Q1L300 is AUDIO_DAC:u11|rom~2360 Q1L300 = Q1L239Q & (Q1L241Q # !Q1L242Q) # !Q1L239Q & (Q1L240Q & (!Q1L242Q # !Q1L241Q) # !Q1L240Q & Q1L241Q); --Q1L301 is AUDIO_DAC:u11|rom~2361 Q1L301 = Q1L244Q & (!Q1L243Q & !Q1L300) # !Q1L244Q & Q1L321; --Q1L224 is AUDIO_DAC:u11|Mux~246 Q1L224 = Q1_SEL_Cont[2] & (Q1_SEL_Cont[3]) # !Q1_SEL_Cont[2] & (Q1_SEL_Cont[3] & Q1L323 # !Q1_SEL_Cont[3] & (Q1L301)); --Q1L302 is AUDIO_DAC:u11|rom~2362 Q1L302 = Q1L244Q # Q1L240Q & Q1L241Q; --Q1L303 is AUDIO_DAC:u11|rom~2363 Q1L303 = Q1L240Q & (!Q1L244Q # !Q1L239Q) # !Q1L240Q & (Q1L239Q $ (Q1L241Q & Q1L244Q)); --Q1L304 is AUDIO_DAC:u11|rom~2364 Q1L304 = Q1L241Q & (Q1L239Q # Q1L240Q # !Q1L244Q) # !Q1L241Q & (Q1L244Q # Q1L239Q & Q1L240Q); --Q1L305 is AUDIO_DAC:u11|rom~2365 Q1L305 = Q1L243Q & (Q1L242Q) # !Q1L243Q & (Q1L242Q & !Q1L303 # !Q1L242Q & (Q1L304)); --Q1L306 is AUDIO_DAC:u11|rom~2366 Q1L306 = !Q1L244Q & (Q1L241Q & (!Q1L240Q) # !Q1L241Q & Q1L239Q); --Q1L307 is AUDIO_DAC:u11|rom~2367 Q1L307 = Q1L243Q & (Q1L305 & (Q1L306) # !Q1L305 & !Q1L302) # !Q1L243Q & (Q1L305); --Q1L225 is AUDIO_DAC:u11|Mux~247 Q1L225 = Q1_SEL_Cont[2] & (Q1L224 & (Q1L307) # !Q1L224 & Q1L297) # !Q1_SEL_Cont[2] & (Q1L224); --Q1L226 is AUDIO_DAC:u11|Mux~248 Q1L226 = Q1_SEL_Cont[1] & (Q1L223 & (Q1L225) # !Q1L223 & Q1L218) # !Q1_SEL_Cont[1] & (Q1L223); --Q1L238 is AUDIO_DAC:u11|oAUD_DATA~55 Q1L238 = !SW[1] & (SW[0] & Q1L216 # !SW[0] & (Q1L226)); --S2__clk0 is VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 S2__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(!B1_oRESET), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK()); --S2__clk1 is VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 S2__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(!B1_oRESET), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK()); --K1_CMD_Tmp[8] is CMD_Decode:u5|CMD_Tmp[8] K1_CMD_Tmp[8] = DFFEAS(K1_CMD_Tmp[0], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_f_SEG7 is CMD_Decode:u5|f_SEG7 K1_f_SEG7 = DFFEAS(K1L181, CLOCK_50, KEY[0], , , , , , ); --K1_CMD_Tmp[63] is CMD_Decode:u5|CMD_Tmp[63] K1_CMD_Tmp[63] = DFFEAS(K1_CMD_Tmp[55], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[62] is CMD_Decode:u5|CMD_Tmp[62] K1_CMD_Tmp[62] = DFFEAS(K1_CMD_Tmp[54], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[61] is CMD_Decode:u5|CMD_Tmp[61] K1_CMD_Tmp[61] = DFFEAS(K1_CMD_Tmp[53], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[59] is CMD_Decode:u5|CMD_Tmp[59] K1_CMD_Tmp[59] = DFFEAS(K1_CMD_Tmp[51], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L73 is CMD_Decode:u5|Equal~628 K1L73 = K1_CMD_Tmp[63] & !K1_CMD_Tmp[62] & !K1_CMD_Tmp[61] & !K1_CMD_Tmp[59]; --K1_CMD_Tmp[56] is CMD_Decode:u5|CMD_Tmp[56] K1_CMD_Tmp[56] = DFFEAS(K1_CMD_Tmp[48], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[60] is CMD_Decode:u5|CMD_Tmp[60] K1_CMD_Tmp[60] = DFFEAS(K1_CMD_Tmp[52], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L74 is CMD_Decode:u5|Equal~629 K1L74 = K1_CMD_Tmp[56] & !K1_CMD_Tmp[60]; --K1_CMD_Tmp[57] is CMD_Decode:u5|CMD_Tmp[57] K1_CMD_Tmp[57] = DFFEAS(K1_CMD_Tmp[49], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[58] is CMD_Decode:u5|CMD_Tmp[58] K1_CMD_Tmp[58] = DFFEAS(K1_CMD_Tmp[50], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L75 is CMD_Decode:u5|Equal~630 K1L75 = K1L73 & K1L74 & K1_CMD_Tmp[57] & !K1_CMD_Tmp[58]; --K1_CMD_Tmp[7] is CMD_Decode:u5|CMD_Tmp[7] K1_CMD_Tmp[7] = DFFEAS(F1_oRxD_DATA[7], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[3] is CMD_Decode:u5|CMD_Tmp[3] K1_CMD_Tmp[3] = DFFEAS(F1_oRxD_DATA[3], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[4] is CMD_Decode:u5|CMD_Tmp[4] K1_CMD_Tmp[4] = DFFEAS(F1_oRxD_DATA[4], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[0] is CMD_Decode:u5|CMD_Tmp[0] K1_CMD_Tmp[0] = DFFEAS(F1_oRxD_DATA[0], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L76 is CMD_Decode:u5|Equal~631 K1L76 = K1_CMD_Tmp[7] & K1_CMD_Tmp[3] & !K1_CMD_Tmp[4] & !K1_CMD_Tmp[0]; --K1_CMD_Tmp[6] is CMD_Decode:u5|CMD_Tmp[6] K1_CMD_Tmp[6] = DFFEAS(F1_oRxD_DATA[6], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[2] is CMD_Decode:u5|CMD_Tmp[2] K1_CMD_Tmp[2] = DFFEAS(F1_oRxD_DATA[2], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[5] is CMD_Decode:u5|CMD_Tmp[5] K1_CMD_Tmp[5] = DFFEAS(F1_oRxD_DATA[5], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[1] is CMD_Decode:u5|CMD_Tmp[1] K1_CMD_Tmp[1] = DFFEAS(F1_oRxD_DATA[1], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L149 is CMD_Decode:u5|always5~43 K1L149 = K1_CMD_Tmp[6] & K1_CMD_Tmp[2] & !K1_CMD_Tmp[5] & !K1_CMD_Tmp[1]; --K1L407 is CMD_Decode:u5|oSEG7_DIG[0]~47 K1L407 = K1_f_SEG7 & K1L75 & K1L76 & K1L149; --K1_CMD_Tmp[9] is CMD_Decode:u5|CMD_Tmp[9] K1_CMD_Tmp[9] = DFFEAS(K1_CMD_Tmp[1], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[10] is CMD_Decode:u5|CMD_Tmp[10] K1_CMD_Tmp[10] = DFFEAS(K1_CMD_Tmp[2], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[11] is CMD_Decode:u5|CMD_Tmp[11] K1_CMD_Tmp[11] = DFFEAS(K1_CMD_Tmp[3], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[12] is CMD_Decode:u5|CMD_Tmp[12] K1_CMD_Tmp[12] = DFFEAS(K1_CMD_Tmp[4], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[13] is CMD_Decode:u5|CMD_Tmp[13] K1_CMD_Tmp[13] = DFFEAS(K1_CMD_Tmp[5], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[14] is CMD_Decode:u5|CMD_Tmp[14] K1_CMD_Tmp[14] = DFFEAS(K1_CMD_Tmp[6], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[15] is CMD_Decode:u5|CMD_Tmp[15] K1_CMD_Tmp[15] = DFFEAS(K1_CMD_Tmp[7], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[16] is CMD_Decode:u5|CMD_Tmp[16] K1_CMD_Tmp[16] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[17] is CMD_Decode:u5|CMD_Tmp[17] K1_CMD_Tmp[17] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[18] is CMD_Decode:u5|CMD_Tmp[18] K1_CMD_Tmp[18] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[19] is CMD_Decode:u5|CMD_Tmp[19] K1_CMD_Tmp[19] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[20] is CMD_Decode:u5|CMD_Tmp[20] K1_CMD_Tmp[20] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[21] is CMD_Decode:u5|CMD_Tmp[21] K1_CMD_Tmp[21] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[22] is CMD_Decode:u5|CMD_Tmp[22] K1_CMD_Tmp[22] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[23] is CMD_Decode:u5|CMD_Tmp[23] K1_CMD_Tmp[23] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_f_LED is CMD_Decode:u5|f_LED K1_f_LED = DFFEAS(K1L166, CLOCK_50, KEY[0], , , , , , ); --K1L316 is CMD_Decode:u5|oLED_GREEN[0]~16 K1L316 = K1L75 & K1L76 & K1L149 & K1_f_LED; --K1_CMD_Tmp[24] is CMD_Decode:u5|CMD_Tmp[24] K1_CMD_Tmp[24] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[25] is CMD_Decode:u5|CMD_Tmp[25] K1_CMD_Tmp[25] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[26] is CMD_Decode:u5|CMD_Tmp[26] K1_CMD_Tmp[26] = DFFEAS(K1_CMD_Tmp[18], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[27] is CMD_Decode:u5|CMD_Tmp[27] K1_CMD_Tmp[27] = DFFEAS(K1_CMD_Tmp[19], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[28] is CMD_Decode:u5|CMD_Tmp[28] K1_CMD_Tmp[28] = DFFEAS(K1_CMD_Tmp[20], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[29] is CMD_Decode:u5|CMD_Tmp[29] K1_CMD_Tmp[29] = DFFEAS(K1_CMD_Tmp[21], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[30] is CMD_Decode:u5|CMD_Tmp[30] K1_CMD_Tmp[30] = DFFEAS(K1_CMD_Tmp[22], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[31] is CMD_Decode:u5|CMD_Tmp[31] K1_CMD_Tmp[31] = DFFEAS(K1_CMD_Tmp[23], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[32] is CMD_Decode:u5|CMD_Tmp[32] K1_CMD_Tmp[32] = DFFEAS(K1_CMD_Tmp[24], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[33] is CMD_Decode:u5|CMD_Tmp[33] K1_CMD_Tmp[33] = DFFEAS(K1_CMD_Tmp[25], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --AB1_SA[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[0] AB1_SA[0] = DFFEAS(AB1L22, S1__clk0, , , , KEY[0], , , AB1L43); --Z1_ST[8] is Multi_Sdram:u3|Sdram_Controller:u1|ST[8] Z1_ST[8] = DFFEAS(Z1L101, S1__clk0, KEY[0], , , , , , ); --Z1_ST[7] is Multi_Sdram:u3|Sdram_Controller:u1|ST[7] Z1_ST[7] = DFFEAS(Z1L95, S1__clk0, KEY[0], , , , , , ); --Z1L37 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~492 Z1L37 = !Z1_ST[8] & !Z1_ST[7]; --Z1_ST[4] is Multi_Sdram:u3|Sdram_Controller:u1|ST[4] Z1_ST[4] = DFFEAS(Z1L89, S1__clk0, KEY[0], , , , , , ); --Z1_ST[6] is Multi_Sdram:u3|Sdram_Controller:u1|ST[6] Z1_ST[6] = DFFEAS(Z1L93, S1__clk0, KEY[0], , , , , , ); --Z1_ST[5] is Multi_Sdram:u3|Sdram_Controller:u1|ST[5] Z1_ST[5] = DFFEAS(Z1L91, S1__clk0, KEY[0], , , , , , ); --Z1L38 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~493 Z1L38 = Z1L37 & !Z1_ST[4] & !Z1_ST[6] & !Z1_ST[5]; --Z1_ST[1] is Multi_Sdram:u3|Sdram_Controller:u1|ST[1] Z1_ST[1] = DFFEAS(Z1L129, S1__clk0, KEY[0], , , , , , ); --Z1_ST[0] is Multi_Sdram:u3|Sdram_Controller:u1|ST[0] Z1_ST[0] = DFFEAS(Z1L81, S1__clk0, KEY[0], , , Z1_ST[0], , , Z1L100); --Z1L35 is Multi_Sdram:u3|Sdram_Controller:u1|Decoder~1171 Z1L35 = !Z1_ST[1] & !Z1_ST[0]; --Z1_ST[2] is Multi_Sdram:u3|Sdram_Controller:u1|ST[2] Z1_ST[2] = DFFEAS(Z1L85, S1__clk0, KEY[0], , , , , , ); --Z1_ST[3] is Multi_Sdram:u3|Sdram_Controller:u1|ST[3] Z1_ST[3] = DFFEAS(Z1L87, S1__clk0, KEY[0], , , , , , ); --Z1L39 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~494 Z1L39 = Z1L38 & Z1L35 & Z1_ST[2] & !Z1_ST[3]; --Z1L67 is Multi_Sdram:u3|Sdram_Controller:u1|SA~462 Z1L67 = AB1_SA[0] & !Z1L39; --AB1_SA[1] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1] AB1_SA[1] = DFFEAS(AB1L25, S1__clk0, , , , KEY[0], , , AB1L43); --Z1L68 is Multi_Sdram:u3|Sdram_Controller:u1|SA~463 Z1L68 = AB1_SA[1] & !Z1L39; --AB1_SA[2] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[2] AB1_SA[2] = DFFEAS(AB1L28, S1__clk0, , , , KEY[0], , , AB1L43); --Z1L69 is Multi_Sdram:u3|Sdram_Controller:u1|SA~464 Z1L69 = AB1_SA[2] & !Z1L39; --AB1_SA[3] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[3] AB1_SA[3] = DFFEAS(AB1L44, S1__clk0, , , , , , , ); --Z1L70 is Multi_Sdram:u3|Sdram_Controller:u1|SA~465 Z1L70 = AB1_SA[3] & !Z1L39; --AB1_SA[4] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[4] AB1_SA[4] = DFFEAS(AB1L32, S1__clk0, , , , KEY[0], , , AB1L43); --Z1L71 is Multi_Sdram:u3|Sdram_Controller:u1|SA~466 Z1L71 = AB1_SA[4] & !Z1L39; --AB1_SA[5] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[5] AB1_SA[5] = DFFEAS(AB1L35, S1__clk0, , , , KEY[0], , , AB1L43); --Z1L72 is Multi_Sdram:u3|Sdram_Controller:u1|SA~467 Z1L72 = AB1_SA[5] & !Z1L39; --AB1_SA[6] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[6] AB1_SA[6] = DFFEAS(AB1L45, S1__clk0, , , , , , , ); --Z1L73 is Multi_Sdram:u3|Sdram_Controller:u1|SA~468 Z1L73 = AB1_SA[6] & !Z1L39; --AB1_SA[7] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[7] AB1_SA[7] = DFFEAS(AB1L46, S1__clk0, , , , , , , ); --Z1L74 is Multi_Sdram:u3|Sdram_Controller:u1|SA~469 Z1L74 = AB1_SA[7] & !Z1L39; --AB1_SA[8] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[8] AB1_SA[8] = DFFEAS(AB1L48, S1__clk0, , , , , , , ); --Z1L75 is Multi_Sdram:u3|Sdram_Controller:u1|SA~470 Z1L75 = AB1_SA[8] & !Z1L39; --AB1_SA[9] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[9] AB1_SA[9] = DFFEAS(AB1L49, S1__clk0, , , , , , , ); --Z1L76 is Multi_Sdram:u3|Sdram_Controller:u1|SA~471 Z1L76 = Z1L39 # AB1_SA[9]; --AB1_SA[10] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[10] AB1_SA[10] = DFFEAS(AB1L47, S1__clk0, , , , , , !KEY[0], ); --Z1L77 is Multi_Sdram:u3|Sdram_Controller:u1|SA~472 Z1L77 = AB1_SA[10] & !Z1L39; --AB1_SA[11] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[11] AB1_SA[11] = DFFEAS(AB1L50, S1__clk0, , , , , , , ); --Z1L78 is Multi_Sdram:u3|Sdram_Controller:u1|SA~473 Z1L78 = AB1_SA[11] & !Z1L39; --Z1L40 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~495 Z1L40 = Z1_ST[1] & Z1_ST[0]; --Z1L44 is Multi_Sdram:u3|Sdram_Controller:u1|LessThan~74 Z1L44 = Z1L38 & !Z1_ST[3] & !Z1_ST[2] & !Z1L40; --Z1_Write is Multi_Sdram:u3|Sdram_Controller:u1|Write Z1_Write = DFFEAS(Z1L108, S1__clk0, KEY[0], , , , , , ); --Z1_Read is Multi_Sdram:u3|Sdram_Controller:u1|Read Z1_Read = DFFEAS(Z1L52, S1__clk0, KEY[0], , , , , , ); --Z1L34 is Multi_Sdram:u3|Sdram_Controller:u1|DQM~86 Z1L34 = Z1L44 # Z1_Write & Z1L39 # !Z1_Write & (!Z1_Read); --AB1_WE_N is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|WE_N AB1_WE_N = DFFEAS(AB1L53, S1__clk0, , , , VCC, , , !KEY[0]); --Z1L105 is Multi_Sdram:u3|Sdram_Controller:u1|WE_N~41 Z1L105 = AB1_WE_N & !Z1L39; --AB1_CAS_N is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CAS_N AB1_CAS_N = DFFEAS(AB1L7, S1__clk0, , , , VCC, , , !KEY[0]); --Z1L5 is Multi_Sdram:u3|Sdram_Controller:u1|CAS_N~9 Z1L5 = Z1L39 # AB1_CAS_N; --AB1_RAS_N is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|RAS_N AB1_RAS_N = DFFEAS(AB1L16, S1__clk0, , , , VCC, , , !KEY[0]); --Z1L50 is Multi_Sdram:u3|Sdram_Controller:u1|RAS_N~41 Z1L50 = AB1_RAS_N & !Z1L39; --AB1_CS_N[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CS_N[0] AB1_CS_N[0] = DFFEAS(AB1L12, S1__clk0, , , , , , , ); --AB1_BA[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[0] AB1_BA[0] = DFFEAS(AB1L4, S1__clk0, , , , , , , ); --AB1_BA[1] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[1] AB1_BA[1] = DFFEAS(AB1L5, S1__clk0, , , , , , , ); --Q1_FLASH_Cont[0] is AUDIO_DAC:u11|FLASH_Cont[0] Q1_FLASH_Cont[0] = DFFEAS(Q1L10, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[0] is CMD_Decode:u5|oFL_ADDR[0] K1_oFL_ADDR[0] = DFFEAS(K1_CMD_Tmp[24], CLOCK_50, , , K1L264, , , , ); --K1_oFL_Select[0] is CMD_Decode:u5|oFL_Select[0] K1_oFL_Select[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L301, , , , ); --W1L31 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[0]~352 W1L31 = K1_oFL_Select[0] & Q1_FLASH_Cont[0] # !K1_oFL_Select[0] & (K1_oFL_ADDR[0]); --K1_oFL_Select[1] is CMD_Decode:u5|oFL_Select[1] K1_oFL_Select[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L301, , , , ); --W1_mFL_Start is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_Start W1_mFL_Start = DFFEAS(W1L22, CLOCK_50, KEY[0], , , , , , ); --K1_oFL_Start is CMD_Decode:u5|oFL_Start K1_oFL_Start = DFFEAS(K1L86, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --W1L1 is Multi_Flash:u2|Flash_Multiplexer:u0|Equal~213 W1L1 = K1_oFL_Select[0] # K1_oFL_Select[1]; --X1_preStart is Multi_Flash:u2|Flash_Controller:u1|preStart X1_preStart = DFFEAS(W1L63, CLOCK_50, KEY[0], , , , , , ); --X1L83 is Multi_Flash:u2|Flash_Controller:u1|Equal~59 X1L83 = !X1_preStart & (W1L1 & W1_mFL_Start # !W1L1 & (K1_oFL_Start)); --X1L243 is Multi_Flash:u2|Flash_Controller:u1|r_CMD[2]~0 X1L243 = KEY[0] & X1L83; --X1_mStart is Multi_Flash:u2|Flash_Controller:u1|mStart X1_mStart = DFFEAS(X1L205, CLOCK_50, KEY[0], , , , , , ); --X1L139 is Multi_Flash:u2|Flash_Controller:u1|ST~412 X1L139 = X1_ST.P3_PRG & !X1_mStart; --X1_mACT is Multi_Flash:u2|Flash_Controller:u1|mACT X1_mACT = DFFEAS(X1L84, CLOCK_50, KEY[0], , , , , , ); --X1_r_CMD[0] is Multi_Flash:u2|Flash_Controller:u1|r_CMD[0] X1_r_CMD[0] = DFFEAS(W1L53, CLOCK_50, , , X1L243, , , , ); --X1_r_CMD[2] is Multi_Flash:u2|Flash_Controller:u1|r_CMD[2] X1_r_CMD[2] = DFFEAS(W1L54, CLOCK_50, , , X1L243, , , , ); --X1L140 is Multi_Flash:u2|Flash_Controller:u1|ST~413 X1L140 = X1_mStart & !X1_r_CMD[0] & !X1_r_CMD[2]; --X1L82 is Multi_Flash:u2|Flash_Controller:u1|Decoder~86 X1L82 = X1_r_CMD[2] & !X1_r_CMD[0]; --X1L141 is Multi_Flash:u2|Flash_Controller:u1|ST~414 X1L141 = X1_mACT & (X1_mStart # X1L82 # !X1_ST.P5); --X1L142 is Multi_Flash:u2|Flash_Controller:u1|ST~415 X1L142 = X1_ST.P1 & !X1_mStart; --X1L150 is Multi_Flash:u2|Flash_Controller:u1|Select~171 X1L150 = X1_ST.P4 # X1_ST.P5 & (X1_r_CMD[0] # !X1_r_CMD[2]); --Q1_FLASH_Cont[1] is AUDIO_DAC:u11|FLASH_Cont[1] Q1_FLASH_Cont[1] = DFFEAS(Q1L13, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[1] is CMD_Decode:u5|oFL_ADDR[1] K1_oFL_ADDR[1] = DFFEAS(K1_CMD_Tmp[25], CLOCK_50, , , K1L264, , , , ); --W1L32 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[1]~353 W1L32 = K1_oFL_Select[0] & Q1_FLASH_Cont[1] # !K1_oFL_Select[0] & (K1_oFL_ADDR[1]); --X1L143 is Multi_Flash:u2|Flash_Controller:u1|ST~416 X1L143 = X1_ST.P2 & !X1_mStart & !X1_r_CMD[0]; --X1L144 is Multi_Flash:u2|Flash_Controller:u1|ST~417 X1L144 = X1_ST.P2 & X1_r_CMD[0] & !X1_mStart & !X1_r_CMD[2]; --X1L145 is Multi_Flash:u2|Flash_Controller:u1|ST~418 X1L145 = X1_ST.P3 & !X1_mStart; --X1L146 is Multi_Flash:u2|Flash_Controller:u1|ST~419 X1L146 = X1_mStart & (X1_r_CMD[0] # X1_r_CMD[2]); --X1L147 is Multi_Flash:u2|Flash_Controller:u1|ST~420 X1L147 = X1_ST.P5 & X1_r_CMD[2] & !X1_mStart & !X1_r_CMD[0]; --X1L148 is Multi_Flash:u2|Flash_Controller:u1|ST~421 X1L148 = X1_ST.P2 & X1_r_CMD[0] & X1_r_CMD[2] & !X1_mStart; --Q1_FLASH_Cont[2] is AUDIO_DAC:u11|FLASH_Cont[2] Q1_FLASH_Cont[2] = DFFEAS(Q1L16, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[2] is CMD_Decode:u5|oFL_ADDR[2] K1_oFL_ADDR[2] = DFFEAS(K1_CMD_Tmp[26], CLOCK_50, , , K1L264, , , , ); --W1L33 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[2]~354 W1L33 = K1_oFL_Select[0] & Q1_FLASH_Cont[2] # !K1_oFL_Select[0] & (K1_oFL_ADDR[2]); --Q1_FLASH_Cont[3] is AUDIO_DAC:u11|FLASH_Cont[3] Q1_FLASH_Cont[3] = DFFEAS(Q1L19, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[3] is CMD_Decode:u5|oFL_ADDR[3] K1_oFL_ADDR[3] = DFFEAS(K1_CMD_Tmp[27], CLOCK_50, , , K1L264, , , , ); --W1L34 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[3]~355 W1L34 = K1_oFL_Select[0] & Q1_FLASH_Cont[3] # !K1_oFL_Select[0] & (K1_oFL_ADDR[3]); --Q1_FLASH_Cont[4] is AUDIO_DAC:u11|FLASH_Cont[4] Q1_FLASH_Cont[4] = DFFEAS(Q1L22, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[4] is CMD_Decode:u5|oFL_ADDR[4] K1_oFL_ADDR[4] = DFFEAS(K1_CMD_Tmp[28], CLOCK_50, , , K1L264, , , , ); --W1L35 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[4]~356 W1L35 = K1_oFL_Select[0] & Q1_FLASH_Cont[4] # !K1_oFL_Select[0] & (K1_oFL_ADDR[4]); --Q1_FLASH_Cont[5] is AUDIO_DAC:u11|FLASH_Cont[5] Q1_FLASH_Cont[5] = DFFEAS(Q1L25, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[5] is CMD_Decode:u5|oFL_ADDR[5] K1_oFL_ADDR[5] = DFFEAS(K1_CMD_Tmp[29], CLOCK_50, , , K1L264, , , , ); --W1L36 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[5]~357 W1L36 = K1_oFL_Select[0] & Q1_FLASH_Cont[5] # !K1_oFL_Select[0] & (K1_oFL_ADDR[5]); --Q1_FLASH_Cont[6] is AUDIO_DAC:u11|FLASH_Cont[6] Q1_FLASH_Cont[6] = DFFEAS(Q1L28, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[6] is CMD_Decode:u5|oFL_ADDR[6] K1_oFL_ADDR[6] = DFFEAS(K1_CMD_Tmp[30], CLOCK_50, , , K1L264, , , , ); --W1L37 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[6]~358 W1L37 = K1_oFL_Select[0] & Q1_FLASH_Cont[6] # !K1_oFL_Select[0] & (K1_oFL_ADDR[6]); --Q1_FLASH_Cont[7] is AUDIO_DAC:u11|FLASH_Cont[7] Q1_FLASH_Cont[7] = DFFEAS(Q1L31, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[7] is CMD_Decode:u5|oFL_ADDR[7] K1_oFL_ADDR[7] = DFFEAS(K1_CMD_Tmp[31], CLOCK_50, , , K1L264, , , , ); --W1L38 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[7]~359 W1L38 = K1_oFL_Select[0] & Q1_FLASH_Cont[7] # !K1_oFL_Select[0] & (K1_oFL_ADDR[7]); --Q1_FLASH_Cont[8] is AUDIO_DAC:u11|FLASH_Cont[8] Q1_FLASH_Cont[8] = DFFEAS(Q1L34, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[8] is CMD_Decode:u5|oFL_ADDR[8] K1_oFL_ADDR[8] = DFFEAS(K1_CMD_Tmp[32], CLOCK_50, , , K1L264, , , , ); --W1L39 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[8]~360 W1L39 = K1_oFL_Select[0] & Q1_FLASH_Cont[8] # !K1_oFL_Select[0] & (K1_oFL_ADDR[8]); --Q1_FLASH_Cont[9] is AUDIO_DAC:u11|FLASH_Cont[9] Q1_FLASH_Cont[9] = DFFEAS(Q1L37, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[9] is CMD_Decode:u5|oFL_ADDR[9] K1_oFL_ADDR[9] = DFFEAS(K1_CMD_Tmp[33], CLOCK_50, , , K1L264, , , , ); --W1L40 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[9]~361 W1L40 = K1_oFL_Select[0] & Q1_FLASH_Cont[9] # !K1_oFL_Select[0] & (K1_oFL_ADDR[9]); --Q1_FLASH_Cont[10] is AUDIO_DAC:u11|FLASH_Cont[10] Q1_FLASH_Cont[10] = DFFEAS(Q1L40, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[10] is CMD_Decode:u5|oFL_ADDR[10] K1_oFL_ADDR[10] = DFFEAS(K1_CMD_Tmp[34], CLOCK_50, , , K1L264, , , , ); --W1L41 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[10]~362 W1L41 = K1_oFL_Select[0] & Q1_FLASH_Cont[10] # !K1_oFL_Select[0] & (K1_oFL_ADDR[10]); --Q1_FLASH_Cont[11] is AUDIO_DAC:u11|FLASH_Cont[11] Q1_FLASH_Cont[11] = DFFEAS(Q1L43, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[11] is CMD_Decode:u5|oFL_ADDR[11] K1_oFL_ADDR[11] = DFFEAS(K1_CMD_Tmp[35], CLOCK_50, , , K1L264, , , , ); --W1L42 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[11]~363 W1L42 = K1_oFL_Select[0] & Q1_FLASH_Cont[11] # !K1_oFL_Select[0] & (K1_oFL_ADDR[11]); --Q1_FLASH_Cont[12] is AUDIO_DAC:u11|FLASH_Cont[12] Q1_FLASH_Cont[12] = DFFEAS(Q1L46, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[12] is CMD_Decode:u5|oFL_ADDR[12] K1_oFL_ADDR[12] = DFFEAS(K1_CMD_Tmp[36], CLOCK_50, , , K1L264, , , , ); --W1L43 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[12]~364 W1L43 = K1_oFL_Select[0] & Q1_FLASH_Cont[12] # !K1_oFL_Select[0] & (K1_oFL_ADDR[12]); --Q1_FLASH_Cont[13] is AUDIO_DAC:u11|FLASH_Cont[13] Q1_FLASH_Cont[13] = DFFEAS(Q1L49, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[13] is CMD_Decode:u5|oFL_ADDR[13] K1_oFL_ADDR[13] = DFFEAS(K1_CMD_Tmp[37], CLOCK_50, , , K1L264, , , , ); --W1L44 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[13]~365 W1L44 = K1_oFL_Select[0] & Q1_FLASH_Cont[13] # !K1_oFL_Select[0] & (K1_oFL_ADDR[13]); --Q1_FLASH_Cont[14] is AUDIO_DAC:u11|FLASH_Cont[14] Q1_FLASH_Cont[14] = DFFEAS(Q1L52, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[14] is CMD_Decode:u5|oFL_ADDR[14] K1_oFL_ADDR[14] = DFFEAS(K1_CMD_Tmp[38], CLOCK_50, , , K1L264, , , , ); --W1L45 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[14]~366 W1L45 = K1_oFL_Select[0] & Q1_FLASH_Cont[14] # !K1_oFL_Select[0] & (K1_oFL_ADDR[14]); --Q1_FLASH_Cont[15] is AUDIO_DAC:u11|FLASH_Cont[15] Q1_FLASH_Cont[15] = DFFEAS(Q1L55, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[15] is CMD_Decode:u5|oFL_ADDR[15] K1_oFL_ADDR[15] = DFFEAS(K1_CMD_Tmp[39], CLOCK_50, , , K1L264, , , , ); --W1L46 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[15]~367 W1L46 = K1_oFL_Select[0] & Q1_FLASH_Cont[15] # !K1_oFL_Select[0] & (K1_oFL_ADDR[15]); --Q1_FLASH_Cont[16] is AUDIO_DAC:u11|FLASH_Cont[16] Q1_FLASH_Cont[16] = DFFEAS(Q1L58, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[16] is CMD_Decode:u5|oFL_ADDR[16] K1_oFL_ADDR[16] = DFFEAS(K1_CMD_Tmp[40], CLOCK_50, , , K1L264, , , , ); --W1L47 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[16]~368 W1L47 = K1_oFL_Select[0] & Q1_FLASH_Cont[16] # !K1_oFL_Select[0] & (K1_oFL_ADDR[16]); --Q1_FLASH_Cont[17] is AUDIO_DAC:u11|FLASH_Cont[17] Q1_FLASH_Cont[17] = DFFEAS(Q1L61, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[17] is CMD_Decode:u5|oFL_ADDR[17] K1_oFL_ADDR[17] = DFFEAS(K1_CMD_Tmp[41], CLOCK_50, , , K1L264, , , , ); --W1L48 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[17]~369 W1L48 = K1_oFL_Select[0] & Q1_FLASH_Cont[17] # !K1_oFL_Select[0] & (K1_oFL_ADDR[17]); --Q1_FLASH_Cont[18] is AUDIO_DAC:u11|FLASH_Cont[18] Q1_FLASH_Cont[18] = DFFEAS(Q1L64, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[18] is CMD_Decode:u5|oFL_ADDR[18] K1_oFL_ADDR[18] = DFFEAS(K1_CMD_Tmp[42], CLOCK_50, , , K1L264, , , , ); --W1L49 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[18]~370 W1L49 = K1_oFL_Select[0] & Q1_FLASH_Cont[18] # !K1_oFL_Select[0] & (K1_oFL_ADDR[18]); --Q1_FLASH_Cont[19] is AUDIO_DAC:u11|FLASH_Cont[19] Q1_FLASH_Cont[19] = DFFEAS(Q1L67, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[19] is CMD_Decode:u5|oFL_ADDR[19] K1_oFL_ADDR[19] = DFFEAS(K1_CMD_Tmp[43], CLOCK_50, , , K1L264, , , , ); --W1L50 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[19]~371 W1L50 = K1_oFL_Select[0] & Q1_FLASH_Cont[19] # !K1_oFL_Select[0] & (K1_oFL_ADDR[19]); --Q1_FLASH_Cont[20] is AUDIO_DAC:u11|FLASH_Cont[20] Q1_FLASH_Cont[20] = DFFEAS(Q1L70, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[20] is CMD_Decode:u5|oFL_ADDR[20] K1_oFL_ADDR[20] = DFFEAS(K1_CMD_Tmp[44], CLOCK_50, , , K1L264, , , , ); --W1L51 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[20]~372 W1L51 = K1_oFL_Select[0] & Q1_FLASH_Cont[20] # !K1_oFL_Select[0] & (K1_oFL_ADDR[20]); --Q1_FLASH_Cont[21] is AUDIO_DAC:u11|FLASH_Cont[21] Q1_FLASH_Cont[21] = DFFEAS(Q1L73, !Q1_LRCK_4X, B1_oRESET, , , , , Q1L201, ); --K1_oFL_ADDR[21] is CMD_Decode:u5|oFL_ADDR[21] K1_oFL_ADDR[21] = DFFEAS(K1_CMD_Tmp[45], CLOCK_50, , , K1L264, , , , ); --W1L52 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_ADDR[21]~373 W1L52 = K1_oFL_Select[0] & Q1_FLASH_Cont[21] # !K1_oFL_Select[0] & (K1_oFL_ADDR[21]); --X1_WE_CLK_Delay[3] is Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[3] X1_WE_CLK_Delay[3] = DFFEAS(X1_WE_CLK_Delay[2], CLOCK_50, KEY[0], , , , , , ); --M1_oCoord_X[1] is VGA_Controller:u8|oCoord_X[1] M1_oCoord_X[1] = DFFEAS(M1_H_Cont[1], S2__clk0, B1_oRESET, , M1L330, , , , ); --M1_oCoord_X[0] is VGA_Controller:u8|oCoord_X[0] M1_oCoord_X[0] = DFFEAS(M1_H_Cont[0], S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L336 is VGA_Controller:u8|oAddress[0]~171 M1L336 = M1_oCoord_X[0] $ VCC; --M1L337 is VGA_Controller:u8|oAddress[0]~172 M1L337 = CARRY(M1_oCoord_X[0]); --M1L339 is VGA_Controller:u8|oAddress[1]~173 M1L339 = M1_oCoord_X[1] & !M1L337 # !M1_oCoord_X[1] & (M1L337 # GND); --M1L340 is VGA_Controller:u8|oAddress[1]~174 M1L340 = CARRY(!M1L337 # !M1_oCoord_X[1]); --B1_oRESET is Reset_Delay:d0|oRESET B1_oRESET = DFFEAS(B1L69, CLOCK_50, , , , , , , ); --M1L36 is VGA_Controller:u8|Equal~1114 M1L36 = !M1_H_Cont[2] & !M1_H_Cont[3]; --M1L329 is VGA_Controller:u8|always0~249 M1L329 = M1_H_Cont[8] & (M1L123 & !M1_H_Cont[7] # !M1_H_Cont[9]) # !M1_H_Cont[8] & (M1_H_Cont[9] # !M1L123 & M1_H_Cont[7]); --M1L330 is VGA_Controller:u8|always0~250 M1L330 = M1L463 & M1L329; --K1_f_SRAM is CMD_Decode:u5|f_SRAM K1_f_SRAM = DFFEAS(K1L187, CLOCK_50, KEY[0], , , , , , ); --K1L137 is CMD_Decode:u5|always0~328 K1L137 = K1_CMD_Tmp[5] & K1_CMD_Tmp[1] & !K1_CMD_Tmp[6] & !K1_CMD_Tmp[2]; --K1_CMD_Tmp[55] is CMD_Decode:u5|CMD_Tmp[55] K1_CMD_Tmp[55] = DFFEAS(K1_CMD_Tmp[47], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[51] is CMD_Decode:u5|CMD_Tmp[51] K1_CMD_Tmp[51] = DFFEAS(K1_CMD_Tmp[43], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L151 is CMD_Decode:u5|always7~140 K1L151 = K1L76 & K1L137 & K1_CMD_Tmp[55] & !K1_CMD_Tmp[51]; --K1_CMD_Tmp[53] is CMD_Decode:u5|CMD_Tmp[53] K1_CMD_Tmp[53] = DFFEAS(K1_CMD_Tmp[45], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[50] is CMD_Decode:u5|CMD_Tmp[50] K1_CMD_Tmp[50] = DFFEAS(K1_CMD_Tmp[42], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[54] is CMD_Decode:u5|CMD_Tmp[54] K1_CMD_Tmp[54] = DFFEAS(K1_CMD_Tmp[46], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[49] is CMD_Decode:u5|CMD_Tmp[49] K1_CMD_Tmp[49] = DFFEAS(K1_CMD_Tmp[41], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L157 is CMD_Decode:u5|always9~95 K1L157 = K1_CMD_Tmp[53] & K1_CMD_Tmp[50] & !K1_CMD_Tmp[54] & !K1_CMD_Tmp[49]; --K1_CMD_Tmp[48] is CMD_Decode:u5|CMD_Tmp[48] K1_CMD_Tmp[48] = DFFEAS(K1_CMD_Tmp[40], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[52] is CMD_Decode:u5|CMD_Tmp[52] K1_CMD_Tmp[52] = DFFEAS(K1_CMD_Tmp[44], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L158 is CMD_Decode:u5|always10~1 K1L158 = K1L151 & K1L157 & K1_CMD_Tmp[48] & !K1_CMD_Tmp[52]; --K1_mSR_ST.000 is CMD_Decode:u5|mSR_ST.000 K1_mSR_ST.000 = DFFEAS(K1L88, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1L425 is CMD_Decode:u5|oSR_ADDR[0]~35 K1L425 = KEY[0] & K1_f_SRAM & K1L158 & !K1_mSR_ST.000; --K1_f_SR_SEL is CMD_Decode:u5|f_SR_SEL K1_f_SR_SEL = DFFEAS(K1L190, CLOCK_50, KEY[0], , , , , , ); --K1L77 is CMD_Decode:u5|Equal~632 K1L77 = !K1_CMD_Tmp[63] & !K1_CMD_Tmp[58]; --K1L78 is CMD_Decode:u5|Equal~633 K1L78 = K1_CMD_Tmp[62] & K1_CMD_Tmp[61] & K1L77 & !K1_CMD_Tmp[59]; --K1_CMD_Tmp[44] is CMD_Decode:u5|CMD_Tmp[44] K1_CMD_Tmp[44] = DFFEAS(K1_CMD_Tmp[36], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[40] is CMD_Decode:u5|CMD_Tmp[40] K1_CMD_Tmp[40] = DFFEAS(K1_CMD_Tmp[32], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L138 is CMD_Decode:u5|always0~329 K1L138 = K1_CMD_Tmp[44] & !K1_CMD_Tmp[40]; --K1L139 is CMD_Decode:u5|always0~330 K1L139 = K1L74 & K1L78 & K1L137 & K1L138; --K1_CMD_Tmp[41] is CMD_Decode:u5|CMD_Tmp[41] K1_CMD_Tmp[41] = DFFEAS(K1_CMD_Tmp[33], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[45] is CMD_Decode:u5|CMD_Tmp[45] K1_CMD_Tmp[45] = DFFEAS(K1_CMD_Tmp[37], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L140 is CMD_Decode:u5|always0~331 K1L140 = K1_CMD_Tmp[41] & !K1_CMD_Tmp[57] & !K1_CMD_Tmp[7] & !K1_CMD_Tmp[45]; --K1L141 is CMD_Decode:u5|always0~332 K1L141 = K1_CMD_Tmp[4] & K1_CMD_Tmp[0] & !K1_CMD_Tmp[3] & !K1_CMD_Tmp[24]; --K1L142 is CMD_Decode:u5|always0~333 K1L142 = K1_CMD_Tmp[25] & K1_CMD_Tmp[26] & K1_CMD_Tmp[28] & !K1_CMD_Tmp[27]; --K1L143 is CMD_Decode:u5|always0~334 K1L143 = K1_CMD_Tmp[30] & !K1_CMD_Tmp[29] & !K1_CMD_Tmp[31] & !K1_CMD_Tmp[32]; --K1L144 is CMD_Decode:u5|always0~335 K1L144 = K1L140 & K1L141 & K1L142 & K1L143; --K1_CMD_Tmp[37] is CMD_Decode:u5|CMD_Tmp[37] K1_CMD_Tmp[37] = DFFEAS(K1_CMD_Tmp[29], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[39] is CMD_Decode:u5|CMD_Tmp[39] K1_CMD_Tmp[39] = DFFEAS(K1_CMD_Tmp[31], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[38] is CMD_Decode:u5|CMD_Tmp[38] K1_CMD_Tmp[38] = DFFEAS(K1_CMD_Tmp[30], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L145 is CMD_Decode:u5|always0~336 K1L145 = K1_CMD_Tmp[37] & !K1_CMD_Tmp[33] & !K1_CMD_Tmp[39] & !K1_CMD_Tmp[38]; --K1_CMD_Tmp[36] is CMD_Decode:u5|CMD_Tmp[36] K1_CMD_Tmp[36] = DFFEAS(K1_CMD_Tmp[28], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[34] is CMD_Decode:u5|CMD_Tmp[34] K1_CMD_Tmp[34] = DFFEAS(K1_CMD_Tmp[26], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[35] is CMD_Decode:u5|CMD_Tmp[35] K1_CMD_Tmp[35] = DFFEAS(K1_CMD_Tmp[27], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[47] is CMD_Decode:u5|CMD_Tmp[47] K1_CMD_Tmp[47] = DFFEAS(K1_CMD_Tmp[39], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L146 is CMD_Decode:u5|always0~337 K1L146 = K1_CMD_Tmp[36] & K1_CMD_Tmp[34] & !K1_CMD_Tmp[35] & !K1_CMD_Tmp[47]; --K1_CMD_Tmp[46] is CMD_Decode:u5|CMD_Tmp[46] K1_CMD_Tmp[46] = DFFEAS(K1_CMD_Tmp[38], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[43] is CMD_Decode:u5|CMD_Tmp[43] K1_CMD_Tmp[43] = DFFEAS(K1_CMD_Tmp[35], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1_CMD_Tmp[42] is CMD_Decode:u5|CMD_Tmp[42] K1_CMD_Tmp[42] = DFFEAS(K1_CMD_Tmp[34], CLOCK_50, KEY[0], , F1_oRxD_Ready, , , , ); --K1L147 is CMD_Decode:u5|always0~338 K1L147 = K1L146 & !K1_CMD_Tmp[46] & !K1_CMD_Tmp[43] & !K1_CMD_Tmp[42]; --K1L148 is CMD_Decode:u5|always0~339 K1L148 = K1L139 & K1L144 & K1L145 & K1L147; --K1L464 is CMD_Decode:u5|oSR_Select[1]~2 K1L464 = K1_f_SR_SEL & K1L148; --M1_oCoord_X[2] is VGA_Controller:u8|oCoord_X[2] M1_oCoord_X[2] = DFFEAS(M1L396, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L342 is VGA_Controller:u8|oAddress[2]~175 M1L342 = M1_oCoord_X[2] & (GND # !M1L340) # !M1_oCoord_X[2] & (M1L340 $ GND); --M1L343 is VGA_Controller:u8|oAddress[2]~176 M1L343 = CARRY(M1_oCoord_X[2] # !M1L340); --M1_oCoord_X[3] is VGA_Controller:u8|oCoord_X[3] M1_oCoord_X[3] = DFFEAS(M1L399, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L345 is VGA_Controller:u8|oAddress[3]~177 M1L345 = M1_oCoord_X[3] & M1L343 & VCC # !M1_oCoord_X[3] & !M1L343; --M1L346 is VGA_Controller:u8|oAddress[3]~178 M1L346 = CARRY(!M1_oCoord_X[3] & !M1L343); --M1_oCoord_X[4] is VGA_Controller:u8|oCoord_X[4] M1_oCoord_X[4] = DFFEAS(M1L402, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L348 is VGA_Controller:u8|oAddress[4]~179 M1L348 = M1_oCoord_X[4] & (GND # !M1L346) # !M1_oCoord_X[4] & (M1L346 $ GND); --M1L349 is VGA_Controller:u8|oAddress[4]~180 M1L349 = CARRY(M1_oCoord_X[4] # !M1L346); --M1_oCoord_X[5] is VGA_Controller:u8|oCoord_X[5] M1_oCoord_X[5] = DFFEAS(M1L405, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L351 is VGA_Controller:u8|oAddress[5]~181 M1L351 = M1_oCoord_X[5] & M1L349 & VCC # !M1_oCoord_X[5] & !M1L349; --M1L352 is VGA_Controller:u8|oAddress[5]~182 M1L352 = CARRY(!M1_oCoord_X[5] & !M1L349); --M1_oCoord_X[6] is VGA_Controller:u8|oCoord_X[6] M1_oCoord_X[6] = DFFEAS(M1L408, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L354 is VGA_Controller:u8|oAddress[6]~183 M1L354 = M1_oCoord_X[6] & (GND # !M1L352) # !M1_oCoord_X[6] & (M1L352 $ GND); --M1L355 is VGA_Controller:u8|oAddress[6]~184 M1L355 = CARRY(M1_oCoord_X[6] # !M1L352); --M1_oCoord_Y[0] is VGA_Controller:u8|oCoord_Y[0] M1_oCoord_Y[0] = DFFEAS(M1_V_Cont[0], S2__clk0, B1_oRESET, , M1L330, , , , ); --M1_oCoord_X[7] is VGA_Controller:u8|oCoord_X[7] M1_oCoord_X[7] = DFFEAS(M1L411, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L155 is VGA_Controller:u8|add~2186 M1L155 = M1_oCoord_Y[0] & (M1_oCoord_X[7] $ VCC) # !M1_oCoord_Y[0] & M1_oCoord_X[7] & VCC; --M1L156 is VGA_Controller:u8|add~2187 M1L156 = CARRY(M1_oCoord_Y[0] & M1_oCoord_X[7]); --M1L357 is VGA_Controller:u8|oAddress[7]~185 M1L357 = M1L155 & M1L355 & VCC # !M1L155 & !M1L355; --M1L358 is VGA_Controller:u8|oAddress[7]~186 M1L358 = CARRY(!M1L155 & !M1L355); --M1_oCoord_Y[1] is VGA_Controller:u8|oCoord_Y[1] M1_oCoord_Y[1] = DFFEAS(M1L422, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1_oCoord_X[8] is VGA_Controller:u8|oCoord_X[8] M1_oCoord_X[8] = DFFEAS(M1L414, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L157 is VGA_Controller:u8|add~2188 M1L157 = M1_oCoord_Y[1] & (M1_oCoord_X[8] & M1L156 & VCC # !M1_oCoord_X[8] & !M1L156) # !M1_oCoord_Y[1] & (M1_oCoord_X[8] & !M1L156 # !M1_oCoord_X[8] & (M1L156 # GND)); --M1L158 is VGA_Controller:u8|add~2189 M1L158 = CARRY(M1_oCoord_Y[1] & !M1_oCoord_X[8] & !M1L156 # !M1_oCoord_Y[1] & (!M1L156 # !M1_oCoord_X[8])); --M1L360 is VGA_Controller:u8|oAddress[8]~187 M1L360 = M1L157 & (GND # !M1L358) # !M1L157 & (M1L358 $ GND); --M1L361 is VGA_Controller:u8|oAddress[8]~188 M1L361 = CARRY(M1L157 # !M1L358); --M1_oCoord_Y[2] is VGA_Controller:u8|oCoord_Y[2] M1_oCoord_Y[2] = DFFEAS(M1L425, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L159 is VGA_Controller:u8|add~2190 M1L159 = M1_oCoord_Y[0] & (M1_oCoord_Y[2] $ VCC) # !M1_oCoord_Y[0] & M1_oCoord_Y[2] & VCC; --M1L160 is VGA_Controller:u8|add~2191 M1L160 = CARRY(M1_oCoord_Y[0] & M1_oCoord_Y[2]); --M1_oCoord_X[9] is VGA_Controller:u8|oCoord_X[9] M1_oCoord_X[9] = DFFEAS(M1L417, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L161 is VGA_Controller:u8|add~2192 M1L161 = (M1L159 $ M1_oCoord_X[9] $ !M1L158) # GND; --M1L162 is VGA_Controller:u8|add~2193 M1L162 = CARRY(M1L159 & (M1_oCoord_X[9] # !M1L158) # !M1L159 & M1_oCoord_X[9] & !M1L158); --M1L363 is VGA_Controller:u8|oAddress[9]~189 M1L363 = M1L161 & M1L361 & VCC # !M1L161 & !M1L361; --M1L364 is VGA_Controller:u8|oAddress[9]~190 M1L364 = CARRY(!M1L161 & !M1L361); --M1_oCoord_Y[3] is VGA_Controller:u8|oCoord_Y[3] M1_oCoord_Y[3] = DFFEAS(M1L428, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L163 is VGA_Controller:u8|add~2194 M1L163 = M1_oCoord_Y[1] & (M1_oCoord_Y[3] & M1L160 & VCC # !M1_oCoord_Y[3] & !M1L160) # !M1_oCoord_Y[1] & (M1_oCoord_Y[3] & !M1L160 # !M1_oCoord_Y[3] & (M1L160 # GND)); --M1L164 is VGA_Controller:u8|add~2195 M1L164 = CARRY(M1_oCoord_Y[1] & !M1_oCoord_Y[3] & !M1L160 # !M1_oCoord_Y[1] & (!M1L160 # !M1_oCoord_Y[3])); --M1L165 is VGA_Controller:u8|add~2196 M1L165 = M1L163 & !M1L162 # !M1L163 & (M1L162 # GND); --M1L166 is VGA_Controller:u8|add~2197 M1L166 = CARRY(!M1L162 # !M1L163); --M1L366 is VGA_Controller:u8|oAddress[10]~191 M1L366 = M1L165 & (GND # !M1L364) # !M1L165 & (M1L364 $ GND); --M1L367 is VGA_Controller:u8|oAddress[10]~192 M1L367 = CARRY(M1L165 # !M1L364); --M1_oCoord_Y[4] is VGA_Controller:u8|oCoord_Y[4] M1_oCoord_Y[4] = DFFEAS(M1L432, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L167 is VGA_Controller:u8|add~2198 M1L167 = (M1_oCoord_Y[2] $ M1_oCoord_Y[4] $ !M1L164) # GND; --M1L168 is VGA_Controller:u8|add~2199 M1L168 = CARRY(M1_oCoord_Y[2] & (M1_oCoord_Y[4] # !M1L164) # !M1_oCoord_Y[2] & M1_oCoord_Y[4] & !M1L164); --M1L169 is VGA_Controller:u8|add~2200 M1L169 = M1L167 & (M1L166 $ GND) # !M1L167 & !M1L166 & VCC; --M1L170 is VGA_Controller:u8|add~2201 M1L170 = CARRY(M1L167 & !M1L166); --M1L369 is VGA_Controller:u8|oAddress[11]~193 M1L369 = M1L169 & M1L367 & VCC # !M1L169 & !M1L367; --M1L370 is VGA_Controller:u8|oAddress[11]~194 M1L370 = CARRY(!M1L169 & !M1L367); --M1_oCoord_Y[5] is VGA_Controller:u8|oCoord_Y[5] M1_oCoord_Y[5] = DFFEAS(M1L435, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L171 is VGA_Controller:u8|add~2202 M1L171 = M1_oCoord_Y[3] & (M1_oCoord_Y[5] & M1L168 & VCC # !M1_oCoord_Y[5] & !M1L168) # !M1_oCoord_Y[3] & (M1_oCoord_Y[5] & !M1L168 # !M1_oCoord_Y[5] & (M1L168 # GND)); --M1L172 is VGA_Controller:u8|add~2203 M1L172 = CARRY(M1_oCoord_Y[3] & !M1_oCoord_Y[5] & !M1L168 # !M1_oCoord_Y[3] & (!M1L168 # !M1_oCoord_Y[5])); --M1L173 is VGA_Controller:u8|add~2204 M1L173 = M1L171 & !M1L170 # !M1L171 & (M1L170 # GND); --M1L174 is VGA_Controller:u8|add~2205 M1L174 = CARRY(!M1L170 # !M1L171); --M1L372 is VGA_Controller:u8|oAddress[12]~195 M1L372 = M1L173 & (GND # !M1L370) # !M1L173 & (M1L370 $ GND); --M1L373 is VGA_Controller:u8|oAddress[12]~196 M1L373 = CARRY(M1L173 # !M1L370); --M1_oCoord_Y[6] is VGA_Controller:u8|oCoord_Y[6] M1_oCoord_Y[6] = DFFEAS(M1L438, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L175 is VGA_Controller:u8|add~2206 M1L175 = (M1_oCoord_Y[4] $ M1_oCoord_Y[6] $ !M1L172) # GND; --M1L176 is VGA_Controller:u8|add~2207 M1L176 = CARRY(M1_oCoord_Y[4] & (M1_oCoord_Y[6] # !M1L172) # !M1_oCoord_Y[4] & M1_oCoord_Y[6] & !M1L172); --M1L177 is VGA_Controller:u8|add~2208 M1L177 = M1L175 & (M1L174 $ GND) # !M1L175 & !M1L174 & VCC; --M1L178 is VGA_Controller:u8|add~2209 M1L178 = CARRY(M1L175 & !M1L174); --M1L375 is VGA_Controller:u8|oAddress[13]~197 M1L375 = M1L177 & M1L373 & VCC # !M1L177 & !M1L373; --M1L376 is VGA_Controller:u8|oAddress[13]~198 M1L376 = CARRY(!M1L177 & !M1L373); --M1_oCoord_Y[7] is VGA_Controller:u8|oCoord_Y[7] M1_oCoord_Y[7] = DFFEAS(M1L441, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L179 is VGA_Controller:u8|add~2210 M1L179 = M1_oCoord_Y[5] & (M1_oCoord_Y[7] & M1L176 & VCC # !M1_oCoord_Y[7] & !M1L176) # !M1_oCoord_Y[5] & (M1_oCoord_Y[7] & !M1L176 # !M1_oCoord_Y[7] & (M1L176 # GND)); --M1L180 is VGA_Controller:u8|add~2211 M1L180 = CARRY(M1_oCoord_Y[5] & !M1_oCoord_Y[7] & !M1L176 # !M1_oCoord_Y[5] & (!M1L176 # !M1_oCoord_Y[7])); --M1L181 is VGA_Controller:u8|add~2212 M1L181 = M1L179 & !M1L178 # !M1L179 & (M1L178 # GND); --M1L182 is VGA_Controller:u8|add~2213 M1L182 = CARRY(!M1L178 # !M1L179); --M1L378 is VGA_Controller:u8|oAddress[14]~199 M1L378 = M1L181 & (GND # !M1L376) # !M1L181 & (M1L376 $ GND); --M1L379 is VGA_Controller:u8|oAddress[14]~200 M1L379 = CARRY(M1L181 # !M1L376); --M1_oCoord_Y[8] is VGA_Controller:u8|oCoord_Y[8] M1_oCoord_Y[8] = DFFEAS(M1L444, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L183 is VGA_Controller:u8|add~2214 M1L183 = (M1_oCoord_Y[6] $ M1_oCoord_Y[8] $ !M1L180) # GND; --M1L184 is VGA_Controller:u8|add~2215 M1L184 = CARRY(M1_oCoord_Y[6] & (M1_oCoord_Y[8] # !M1L180) # !M1_oCoord_Y[6] & M1_oCoord_Y[8] & !M1L180); --M1L185 is VGA_Controller:u8|add~2216 M1L185 = M1L183 & (M1L182 $ GND) # !M1L183 & !M1L182 & VCC; --M1L186 is VGA_Controller:u8|add~2217 M1L186 = CARRY(M1L183 & !M1L182); --M1L381 is VGA_Controller:u8|oAddress[15]~201 M1L381 = M1L185 & M1L379 & VCC # !M1L185 & !M1L379; --M1L382 is VGA_Controller:u8|oAddress[15]~202 M1L382 = CARRY(!M1L185 & !M1L379); --M1_oCoord_Y[9] is VGA_Controller:u8|oCoord_Y[9] M1_oCoord_Y[9] = DFFEAS(M1L447, S2__clk0, B1_oRESET, , M1L330, , , , ); --M1L187 is VGA_Controller:u8|add~2218 M1L187 = M1_oCoord_Y[7] & (M1_oCoord_Y[9] & M1L184 & VCC # !M1_oCoord_Y[9] & !M1L184) # !M1_oCoord_Y[7] & (M1_oCoord_Y[9] & !M1L184 # !M1_oCoord_Y[9] & (M1L184 # GND)); --M1L188 is VGA_Controller:u8|add~2219 M1L188 = CARRY(M1_oCoord_Y[7] & !M1_oCoord_Y[9] & !M1L184 # !M1_oCoord_Y[7] & (!M1L184 # !M1_oCoord_Y[9])); --M1L189 is VGA_Controller:u8|add~2220 M1L189 = M1L187 & !M1L186 # !M1L187 & (M1L186 # GND); --M1L190 is VGA_Controller:u8|add~2221 M1L190 = CARRY(!M1L186 # !M1L187); --M1L384 is VGA_Controller:u8|oAddress[16]~203 M1L384 = M1L189 & (GND # !M1L382) # !M1L189 & (M1L382 $ GND); --M1L385 is VGA_Controller:u8|oAddress[16]~204 M1L385 = CARRY(M1L189 # !M1L382); --M1L191 is VGA_Controller:u8|add~2222 M1L191 = M1_oCoord_Y[8] & (M1L188 $ GND) # !M1_oCoord_Y[8] & !M1L188 & VCC; --M1L192 is VGA_Controller:u8|add~2223 M1L192 = CARRY(M1_oCoord_Y[8] & !M1L188); --M1L193 is VGA_Controller:u8|add~2224 M1L193 = M1L191 & (M1L190 $ GND) # !M1L191 & !M1L190 & VCC; --M1L194 is VGA_Controller:u8|add~2225 M1L194 = CARRY(M1L191 & !M1L190); --M1L387 is VGA_Controller:u8|oAddress[17]~205 M1L387 = M1L193 & M1L385 & VCC # !M1L193 & !M1L385; --M1L388 is VGA_Controller:u8|oAddress[17]~206 M1L388 = CARRY(!M1L193 & !M1L385); --M1L195 is VGA_Controller:u8|add~2226 M1L195 = M1_oCoord_Y[9] $ M1L192; --M1L197 is VGA_Controller:u8|add~2228 M1L197 = M1L195 $ M1L194; --M1L390 is VGA_Controller:u8|oAddress[18]~207 M1L390 = M1L197 $ M1L388; --K1L79 is CMD_Decode:u5|Equal~634 K1L79 = K1_CMD_Tmp[60] & K1_CMD_Tmp[58] & !K1_CMD_Tmp[56] & !K1_CMD_Tmp[57]; --K1L215 is CMD_Decode:u5|mSDR_WRn~80 K1L215 = K1_mSDR_WRn & (!K1L79 # !K1L73) # !K1_mSDR_WRn & K1L75 & (!K1L79 # !K1L73); --K1L426 is CMD_Decode:u5|oSR_ADDR[0]~1141 K1L426 = K1L158 & !K1_mSR_ST.000; --K1_mSR_ST.100 is CMD_Decode:u5|mSR_ST.100 K1_mSR_ST.100 = DFFEAS(K1L89, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1_mSR_ST.101 is CMD_Decode:u5|mSR_ST.101 K1_mSR_ST.101 = DFFEAS(K1L222, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --F1_oTxD_Done is USB_JTAG:u1|oTxD_Done F1_oTxD_Done = DFFEAS(F1L1, CLOCK_50, KEY[0], , , , , , ); --K1L81 is CMD_Decode:u5|Select~2906 K1L81 = K1_mSR_ST.100 # K1_mSR_ST.101 & !F1_oTxD_Done # !K1_mSR_ST.000; --K1_mSR_ST.011 is CMD_Decode:u5|mSR_ST.011 K1_mSR_ST.011 = DFFEAS(K1L223, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1_mSR_ST.010 is CMD_Decode:u5|mSR_ST.010 K1_mSR_ST.010 = DFFEAS(K1L90, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1_mSR_ST.001 is CMD_Decode:u5|mSR_ST.001 K1_mSR_ST.001 = DFFEAS(K1L426, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1L82 is CMD_Decode:u5|Select~2907 K1L82 = K1_mSR_ST.011 # K1_mSR_ST.010 # K1_mSR_ST.001 & !K1_mSDR_WRn; --K1L83 is CMD_Decode:u5|Select~2908 K1L83 = K1L426 # K1_mSR_Start & (K1L81 # K1L82); --K1_oFL_TXD_Start is CMD_Decode:u5|oFL_TXD_Start K1_oFL_TXD_Start = DFFEAS(K1L91, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1_oSDR_TXD_Start is CMD_Decode:u5|oSDR_TXD_Start K1_oSDR_TXD_Start = DFFEAS(K1L93, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1_oSR_TXD_Start is CMD_Decode:u5|oSR_TXD_Start K1_oSR_TXD_Start = DFFEAS(K1L95, CLOCK_50, KEY[0], , K1_f_SRAM, , , , ); --K1_oPS2_TXD_Start is CMD_Decode:u5|oPS2_TXD_Start K1_oPS2_TXD_Start = DFFEAS(K1L348, CLOCK_50, KEY[0], , , , , , ); --K1_sel_SR is CMD_Decode:u5|sel_SR K1_sel_SR = DFFEAS(K1L96, CLOCK_50, KEY[0], , K1L507, , , , ); --K1L499 is CMD_Decode:u5|oTXD_Start~293 K1L499 = K1_sel_SR & K1_oSR_TXD_Start # !K1_sel_SR & (K1_oPS2_TXD_Start); --K1_sel_SDR is CMD_Decode:u5|sel_SDR K1_sel_SDR = DFFEAS(K1L97, CLOCK_50, KEY[0], , K1L507, , , , ); --K1L500 is CMD_Decode:u5|oTXD_Start~294 K1L500 = K1_sel_SDR & K1_oSDR_TXD_Start # !K1_sel_SDR & (K1L499); --K1_sel_FL is CMD_Decode:u5|sel_FL K1_sel_FL = DFFEAS(K1L98, CLOCK_50, KEY[0], , K1L507, , , , ); --K1L501 is CMD_Decode:u5|oTXD_Start~295 K1L501 = K1_sel_FL & K1_oFL_TXD_Start # !K1_sel_FL & (K1L500); --K1_oFL_TXD_DATA[5] is CMD_Decode:u5|oFL_TXD_DATA[5] K1_oFL_TXD_DATA[5] = DFFEAS(W1L69, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[5] is CMD_Decode:u5|oSDR_TXD_DATA[5] K1_oSDR_TXD_DATA[5] = DFFEAS(K1L99, CLOCK_50, , , K1L403, , , , ); --K1_oSR_TXD_DATA[5] is CMD_Decode:u5|oSR_TXD_DATA[5] K1_oSR_TXD_DATA[5] = DFFEAS(K1L100, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[5] is CMD_Decode:u5|oPS2_TXD_DATA[5] K1_oPS2_TXD_DATA[5] = DFFEAS(J1_rx_ascii[5], CLOCK_50, , , K1L346, , , , ); --K1L491 is CMD_Decode:u5|oTXD_DATA[5]~2138 K1L491 = K1_sel_SR & K1_oSR_TXD_DATA[5] # !K1_sel_SR & (K1_oPS2_TXD_DATA[5]); --K1L492 is CMD_Decode:u5|oTXD_DATA[5]~2139 K1L492 = K1_sel_SDR & K1_oSDR_TXD_DATA[5] # !K1_sel_SDR & (K1L491); --K1L493 is CMD_Decode:u5|oTXD_DATA[5]~2140 K1L493 = K1_sel_FL & K1_oFL_TXD_DATA[5] # !K1_sel_FL & (K1L492); --V1_rCont[0] is USB_JTAG:u1|JTAG_TRANS:u1|rCont[0] V1_rCont[0] = DFFEAS(V1L13, R1_wire_clkctrl1_outclk, !TCS, , , , , , ); --K1_oFL_TXD_DATA[6] is CMD_Decode:u5|oFL_TXD_DATA[6] K1_oFL_TXD_DATA[6] = DFFEAS(W1L70, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[6] is CMD_Decode:u5|oSDR_TXD_DATA[6] K1_oSDR_TXD_DATA[6] = DFFEAS(K1L101, CLOCK_50, , , K1L403, , , , ); --K1L494 is CMD_Decode:u5|oTXD_DATA[6]~2141 K1L494 = K1_sel_SDR & K1_oSDR_TXD_DATA[6]; --K1_oSR_TXD_DATA[6] is CMD_Decode:u5|oSR_TXD_DATA[6] K1_oSR_TXD_DATA[6] = DFFEAS(K1L102, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[6] is CMD_Decode:u5|oPS2_TXD_DATA[6] K1_oPS2_TXD_DATA[6] = DFFEAS(J1_rx_ascii[6], CLOCK_50, , , K1L346, , , , ); --K1L495 is CMD_Decode:u5|oTXD_DATA[6]~2142 K1L495 = !K1_sel_SDR & (K1_sel_SR & K1_oSR_TXD_DATA[6] # !K1_sel_SR & (K1_oPS2_TXD_DATA[6])); --K1L496 is CMD_Decode:u5|oTXD_DATA[6]~2143 K1L496 = K1_sel_FL & K1_oFL_TXD_DATA[6] # !K1_sel_FL & (K1L494 # K1L495); --V1_rCont[1] is USB_JTAG:u1|JTAG_TRANS:u1|rCont[1] V1_rCont[1] = DFFEAS(V1L14, R1_wire_clkctrl1_outclk, !TCS, , , , , , ); --K1_oFL_TXD_DATA[4] is CMD_Decode:u5|oFL_TXD_DATA[4] K1_oFL_TXD_DATA[4] = DFFEAS(W1L68, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[4] is CMD_Decode:u5|oSDR_TXD_DATA[4] K1_oSDR_TXD_DATA[4] = DFFEAS(K1L103, CLOCK_50, , , K1L403, , , , ); --K1_oSR_TXD_DATA[4] is CMD_Decode:u5|oSR_TXD_DATA[4] K1_oSR_TXD_DATA[4] = DFFEAS(K1L104, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[4] is CMD_Decode:u5|oPS2_TXD_DATA[4] K1_oPS2_TXD_DATA[4] = DFFEAS(J1_rx_ascii[4], CLOCK_50, , , K1L346, , , , ); --K1L488 is CMD_Decode:u5|oTXD_DATA[4]~2144 K1L488 = K1_sel_SR & K1_oSR_TXD_DATA[4] # !K1_sel_SR & (K1_oPS2_TXD_DATA[4]); --K1L489 is CMD_Decode:u5|oTXD_DATA[4]~2145 K1L489 = K1_sel_SDR & K1_oSDR_TXD_DATA[4] # !K1_sel_SDR & (K1L488); --K1L490 is CMD_Decode:u5|oTXD_DATA[4]~2146 K1L490 = K1_sel_FL & K1_oFL_TXD_DATA[4] # !K1_sel_FL & (K1L489); --V1L2 is USB_JTAG:u1|JTAG_TRANS:u1|Mux~66 V1L2 = V1_rCont[0] & (V1_rCont[1]) # !V1_rCont[0] & (V1_rCont[1] & K1L496 # !V1_rCont[1] & (K1L490)); --K1_oFL_TXD_DATA[7] is CMD_Decode:u5|oFL_TXD_DATA[7] K1_oFL_TXD_DATA[7] = DFFEAS(W1L71, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[7] is CMD_Decode:u5|oSDR_TXD_DATA[7] K1_oSDR_TXD_DATA[7] = DFFEAS(K1L105, CLOCK_50, , , K1L403, , , , ); --K1_oSR_TXD_DATA[7] is CMD_Decode:u5|oSR_TXD_DATA[7] K1_oSR_TXD_DATA[7] = DFFEAS(K1L106, CLOCK_50, , , K1L474, , , , ); --K1L497 is CMD_Decode:u5|oTXD_DATA[7]~2147 K1L497 = K1_sel_SDR & K1_oSDR_TXD_DATA[7] # !K1_sel_SDR & (K1_sel_SR & K1_oSR_TXD_DATA[7]); --K1L498 is CMD_Decode:u5|oTXD_DATA[7]~2148 K1L498 = K1_sel_FL & K1_oFL_TXD_DATA[7] # !K1_sel_FL & (K1L497); --V1L3 is USB_JTAG:u1|JTAG_TRANS:u1|Mux~67 V1L3 = V1_rCont[0] & (V1L2 & (K1L498) # !V1L2 & K1L493) # !V1_rCont[0] & (V1L2); --K1_oFL_TXD_DATA[2] is CMD_Decode:u5|oFL_TXD_DATA[2] K1_oFL_TXD_DATA[2] = DFFEAS(W1L66, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[2] is CMD_Decode:u5|oSDR_TXD_DATA[2] K1_oSDR_TXD_DATA[2] = DFFEAS(K1L107, CLOCK_50, , , K1L403, , , , ); --K1L482 is CMD_Decode:u5|oTXD_DATA[2]~2149 K1L482 = K1_sel_SDR & K1_oSDR_TXD_DATA[2]; --K1_oSR_TXD_DATA[2] is CMD_Decode:u5|oSR_TXD_DATA[2] K1_oSR_TXD_DATA[2] = DFFEAS(K1L108, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[2] is CMD_Decode:u5|oPS2_TXD_DATA[2] K1_oPS2_TXD_DATA[2] = DFFEAS(J1_rx_ascii[2], CLOCK_50, , , K1L346, , , , ); --K1L483 is CMD_Decode:u5|oTXD_DATA[2]~2150 K1L483 = !K1_sel_SDR & (K1_sel_SR & K1_oSR_TXD_DATA[2] # !K1_sel_SR & (K1_oPS2_TXD_DATA[2])); --K1L484 is CMD_Decode:u5|oTXD_DATA[2]~2151 K1L484 = K1_sel_FL & K1_oFL_TXD_DATA[2] # !K1_sel_FL & (K1L482 # K1L483); --K1_oFL_TXD_DATA[1] is CMD_Decode:u5|oFL_TXD_DATA[1] K1_oFL_TXD_DATA[1] = DFFEAS(W1L65, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[1] is CMD_Decode:u5|oSDR_TXD_DATA[1] K1_oSDR_TXD_DATA[1] = DFFEAS(K1L109, CLOCK_50, , , K1L403, , , , ); --K1L479 is CMD_Decode:u5|oTXD_DATA[1]~2152 K1L479 = K1_sel_SDR & K1_oSDR_TXD_DATA[1]; --K1_oSR_TXD_DATA[1] is CMD_Decode:u5|oSR_TXD_DATA[1] K1_oSR_TXD_DATA[1] = DFFEAS(K1L110, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[1] is CMD_Decode:u5|oPS2_TXD_DATA[1] K1_oPS2_TXD_DATA[1] = DFFEAS(J1_rx_ascii[1], CLOCK_50, , , K1L346, , , , ); --K1L480 is CMD_Decode:u5|oTXD_DATA[1]~2153 K1L480 = !K1_sel_SDR & (K1_sel_SR & K1_oSR_TXD_DATA[1] # !K1_sel_SR & (K1_oPS2_TXD_DATA[1])); --K1L481 is CMD_Decode:u5|oTXD_DATA[1]~2154 K1L481 = K1_sel_FL & K1_oFL_TXD_DATA[1] # !K1_sel_FL & (K1L479 # K1L480); --K1_oFL_TXD_DATA[0] is CMD_Decode:u5|oFL_TXD_DATA[0] K1_oFL_TXD_DATA[0] = DFFEAS(W1L64, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[0] is CMD_Decode:u5|oSDR_TXD_DATA[0] K1_oSDR_TXD_DATA[0] = DFFEAS(K1L111, CLOCK_50, , , K1L403, , , , ); --K1_oSR_TXD_DATA[0] is CMD_Decode:u5|oSR_TXD_DATA[0] K1_oSR_TXD_DATA[0] = DFFEAS(K1L112, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[0] is CMD_Decode:u5|oPS2_TXD_DATA[0] K1_oPS2_TXD_DATA[0] = DFFEAS(J1_rx_ascii[0], CLOCK_50, , , K1L346, , , , ); --K1L476 is CMD_Decode:u5|oTXD_DATA[0]~2155 K1L476 = K1_sel_SR & K1_oSR_TXD_DATA[0] # !K1_sel_SR & (K1_oPS2_TXD_DATA[0]); --K1L477 is CMD_Decode:u5|oTXD_DATA[0]~2156 K1L477 = K1_sel_SDR & K1_oSDR_TXD_DATA[0] # !K1_sel_SDR & (K1L476); --K1L478 is CMD_Decode:u5|oTXD_DATA[0]~2157 K1L478 = K1_sel_FL & K1_oFL_TXD_DATA[0] # !K1_sel_FL & (K1L477); --V1L4 is USB_JTAG:u1|JTAG_TRANS:u1|Mux~68 V1L4 = V1_rCont[1] & (V1_rCont[0]) # !V1_rCont[1] & (V1_rCont[0] & K1L481 # !V1_rCont[0] & (K1L478)); --K1_oFL_TXD_DATA[3] is CMD_Decode:u5|oFL_TXD_DATA[3] K1_oFL_TXD_DATA[3] = DFFEAS(W1L67, CLOCK_50, , , K1L312, , , , ); --K1_oSDR_TXD_DATA[3] is CMD_Decode:u5|oSDR_TXD_DATA[3] K1_oSDR_TXD_DATA[3] = DFFEAS(K1L113, CLOCK_50, , , K1L403, , , , ); --K1L485 is CMD_Decode:u5|oTXD_DATA[3]~2158 K1L485 = K1_sel_SDR & K1_oSDR_TXD_DATA[3]; --K1_oSR_TXD_DATA[3] is CMD_Decode:u5|oSR_TXD_DATA[3] K1_oSR_TXD_DATA[3] = DFFEAS(K1L114, CLOCK_50, , , K1L474, , , , ); --K1_oPS2_TXD_DATA[3] is CMD_Decode:u5|oPS2_TXD_DATA[3] K1_oPS2_TXD_DATA[3] = DFFEAS(J1_rx_ascii[3], CLOCK_50, , , K1L346, , , , ); --K1L486 is CMD_Decode:u5|oTXD_DATA[3]~2159 K1L486 = !K1_sel_SDR & (K1_sel_SR & K1_oSR_TXD_DATA[3] # !K1_sel_SR & (K1_oPS2_TXD_DATA[3])); --K1L487 is CMD_Decode:u5|oTXD_DATA[3]~2160 K1L487 = K1_sel_FL & K1_oFL_TXD_DATA[3] # !K1_sel_FL & (K1L485 # K1L486); --V1L5 is USB_JTAG:u1|JTAG_TRANS:u1|Mux~69 V1L5 = V1_rCont[1] & (V1L4 & (K1L487) # !V1L4 & K1L484) # !V1_rCont[1] & (V1L4); --V1_rCont[2] is USB_JTAG:u1|JTAG_TRANS:u1|rCont[2] V1_rCont[2] = DFFEAS(V1L15, R1_wire_clkctrl1_outclk, !TCS, , , , , , ); --V1L7 is USB_JTAG:u1|JTAG_TRANS:u1|TDO~83 V1L7 = K1L501 & (V1_rCont[2] & V1L3 # !V1_rCont[2] & (V1L5)); --R1_wire_clkctrl1_outclk is CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component|wire_clkctrl1_outclk R1_wire_clkctrl1_outclk = CLKCTRL(.ENA = VCC, .INCLK[0] = TCK, .CLKSELECT[0] = GND, .CLKSELECT[1] = GND) WITH (clock_type = "Global Clock", ena_register_mode = "none"); --MB1L56 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1103 MB1L56 = !MB1L52Q & !MB1L46Q & !MB1L49Q & !MB1L43Q; --MB1L18 is I2C_AV_Config:u10|I2C_Controller:u0|LessThan~163 MB1L18 = MB1L40Q # MB1L55Q # !MB1L56; --MB1L38 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0]~280 MB1L38 = MB1L18 & !MB1L40Q # !MB1L18 & MB1L40Q & VCC; --MB1L39 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0]~281 MB1L39 = CARRY(MB1L18 & !MB1L40Q); --P1_mI2C_GO is I2C_AV_Config:u10|mI2C_GO P1_mI2C_GO = DFFEAS(P1L19, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --MB1L41 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1]~282 MB1L41 = MB1L43Q & (GND # !MB1L39) # !MB1L43Q & (MB1L39 $ GND); --MB1L42 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1]~283 MB1L42 = CARRY(MB1L43Q # !MB1L39); --MB1L44 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2]~284 MB1L44 = MB1L46Q & MB1L42 & VCC # !MB1L46Q & !MB1L42; --MB1L45 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2]~285 MB1L45 = CARRY(!MB1L46Q & !MB1L42); --MB1L47 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3]~286 MB1L47 = MB1L49Q & (GND # !MB1L45) # !MB1L49Q & (MB1L45 $ GND); --MB1L48 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3]~287 MB1L48 = CARRY(MB1L49Q # !MB1L45); --MB1L50 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4]~288 MB1L50 = MB1L52Q & MB1L48 & VCC # !MB1L52Q & !MB1L48; --MB1L51 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4]~289 MB1L51 = CARRY(!MB1L52Q & !MB1L48); --MB1L53 is I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5]~290 MB1L53 = MB1L55Q $ MB1L51; --P1_mI2C_CLK_DIV[12] is I2C_AV_Config:u10|mI2C_CLK_DIV[12] P1_mI2C_CLK_DIV[12] = DFFEAS(P1L60, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[13] is I2C_AV_Config:u10|mI2C_CLK_DIV[13] P1_mI2C_CLK_DIV[13] = DFFEAS(P1L63, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[14] is I2C_AV_Config:u10|mI2C_CLK_DIV[14] P1_mI2C_CLK_DIV[14] = DFFEAS(P1L66, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[15] is I2C_AV_Config:u10|mI2C_CLK_DIV[15] P1_mI2C_CLK_DIV[15] = DFFEAS(P1L69, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L14 is I2C_AV_Config:u10|LessThan~226 P1L14 = !P1_mI2C_CLK_DIV[12] & !P1_mI2C_CLK_DIV[13] & !P1_mI2C_CLK_DIV[14] & !P1_mI2C_CLK_DIV[15]; --P1_mI2C_CLK_DIV[2] is I2C_AV_Config:u10|mI2C_CLK_DIV[2] P1_mI2C_CLK_DIV[2] = DFFEAS(P1L30, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[3] is I2C_AV_Config:u10|mI2C_CLK_DIV[3] P1_mI2C_CLK_DIV[3] = DFFEAS(P1L33, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[4] is I2C_AV_Config:u10|mI2C_CLK_DIV[4] P1_mI2C_CLK_DIV[4] = DFFEAS(P1L36, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[5] is I2C_AV_Config:u10|mI2C_CLK_DIV[5] P1_mI2C_CLK_DIV[5] = DFFEAS(P1L39, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L15 is I2C_AV_Config:u10|LessThan~227 P1L15 = !P1_mI2C_CLK_DIV[2] & !P1_mI2C_CLK_DIV[3] & !P1_mI2C_CLK_DIV[4] & !P1_mI2C_CLK_DIV[5]; --P1_mI2C_CLK_DIV[6] is I2C_AV_Config:u10|mI2C_CLK_DIV[6] P1_mI2C_CLK_DIV[6] = DFFEAS(P1L42, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[7] is I2C_AV_Config:u10|mI2C_CLK_DIV[7] P1_mI2C_CLK_DIV[7] = DFFEAS(P1L45, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[8] is I2C_AV_Config:u10|mI2C_CLK_DIV[8] P1_mI2C_CLK_DIV[8] = DFFEAS(P1L48, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L16 is I2C_AV_Config:u10|LessThan~228 P1L16 = P1L15 # !P1_mI2C_CLK_DIV[8] # !P1_mI2C_CLK_DIV[7] # !P1_mI2C_CLK_DIV[6]; --P1_mI2C_CLK_DIV[9] is I2C_AV_Config:u10|mI2C_CLK_DIV[9] P1_mI2C_CLK_DIV[9] = DFFEAS(P1L51, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[10] is I2C_AV_Config:u10|mI2C_CLK_DIV[10] P1_mI2C_CLK_DIV[10] = DFFEAS(P1L54, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L17 is I2C_AV_Config:u10|LessThan~229 P1L17 = !P1_mI2C_CLK_DIV[9] & !P1_mI2C_CLK_DIV[10]; --P1_mI2C_CLK_DIV[11] is I2C_AV_Config:u10|mI2C_CLK_DIV[11] P1_mI2C_CLK_DIV[11] = DFFEAS(P1L57, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L18 is I2C_AV_Config:u10|LessThan~230 P1L18 = P1_mI2C_CLK_DIV[11] & (!P1L17 # !P1L16) # !P1L14; --P1L72 is I2C_AV_Config:u10|mI2C_CTRL_CLK~79 P1L72 = P1_mI2C_CTRL_CLK $ P1L18; --MB1L20 is I2C_AV_Config:u10|I2C_Controller:u0|SCLK~145 MB1L20 = MB1L43Q & !MB1L49Q # !MB1L43Q & (MB1L46Q); --MB1L21 is I2C_AV_Config:u10|I2C_Controller:u0|SCLK~146 MB1L21 = MB1L52Q & (!MB1L20 # !MB1L49Q # !MB1L40Q) # !MB1L52Q & (MB1L49Q # MB1L20); --MB1L37 is I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~829 MB1L37 = MB1L52Q & MB1L46Q & MB1L49Q & MB1L43Q; --MB1L22 is I2C_AV_Config:u10|I2C_Controller:u0|SCLK~147 MB1L22 = MB1L40Q & (MB1L37 $ !MB1L21); --MB1L23 is I2C_AV_Config:u10|I2C_Controller:u0|SCLK~148 MB1L23 = MB1L55Q & (MB1L21 & MB1_SCLK & !MB1L22 # !MB1L21 & (MB1L22)) # !MB1L55Q & MB1_SCLK; --M1L116 is VGA_Controller:u8|LessThan~1417 M1L116 = M1_H_Cont[7] # M1_H_Cont[5] & M1_H_Cont[6] # !M1L35; --M1L37 is VGA_Controller:u8|Equal~1115 M1L37 = M1L34 & M1L36 & !M1_H_Cont[7] & !M1_H_Cont[4]; --M1L38 is VGA_Controller:u8|Equal~1116 M1L38 = M1L35 & M1L37 & !M1_H_Cont[0] & !M1_H_Cont[1]; --M1L465 is VGA_Controller:u8|oVGA_V_SYNC~174 M1L465 = M1L38 & (M1_V_Cont[9] # M1L115) # !M1L38 & M1_oVGA_V_SYNC; --N1_oRed[8] is VGA_OSD_RAM:u9|oRed[8] N1_oRed[8] = DFFEAS(N1L140, S2__clk0, KEY[0], , , , , , ); --L1L1 is Multi_Sram:u6|Equal~143 L1L1 = K1_oSR_Select[0] & !K1_oSR_Select[1]; --M1_oAddress[0] is VGA_Controller:u8|oAddress[0] M1_oAddress[0] = DFFEAS(M1L336, S2__clk0, B1_oRESET, , M1L330, , , , ); --A1L347 is mVGA_R[6]~263 A1L347 = L1L1 & (M1_oAddress[0] & A1L301 # !M1_oAddress[0] & (A1L285)); --K1_oOSD_CUR_EN[1] is CMD_Decode:u5|oOSD_CUR_EN[1] K1_oOSD_CUR_EN[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L67, , , , ); --M1L23 is VGA_Controller:u8|Cur_Color_R[6]~52 M1L23 = K1_oOSD_CUR_EN[1] & (A1L347) # !K1_oOSD_CUR_EN[1] & N1_oRed[8]; --K1_oCursor_R[6] is CMD_Decode:u5|oCursor_R[6] K1_oCursor_R[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L68, , , , ); --K1_oOSD_CUR_EN[0] is CMD_Decode:u5|oOSD_CUR_EN[0] K1_oOSD_CUR_EN[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L67, , , , ); --K1_oCursor_Y[0] is CMD_Decode:u5|oCursor_Y[0] K1_oCursor_Y[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L69, , , , ); --M1L199 is VGA_Controller:u8|add~2230 M1L199 = K1_oCursor_Y[0] $ VCC; --M1L200 is VGA_Controller:u8|add~2231 M1L200 = CARRY(K1_oCursor_Y[0]); --M1_V_Cont[0] is VGA_Controller:u8|V_Cont[0] M1_V_Cont[0] = DFFEAS(M1L126, S2__clk0, B1_oRESET, , M1L38, , , M1L121, ); --K1_oCursor_Y[4] is CMD_Decode:u5|oCursor_Y[4] K1_oCursor_Y[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, KEY[0], , K1L69, , , , ); --K1_oCursor_Y[3] is CMD_Decode:u5|oCursor_Y[3] K1_oCursor_Y[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, KEY[0], , K1L69, , , , ); --K1_oCursor_Y[2] is CMD_Decode:u5|oCursor_Y[2] K1_oCursor_Y[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, KEY[0], , K1L69, , , , ); --K1_oCursor_Y[1] is CMD_Decode:u5|oCursor_Y[1] K1_oCursor_Y[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L69, , , , ); --M1L201 is VGA_Controller:u8|add~2232 M1L201 = K1_oCursor_Y[1] $ VCC; --M1L202 is VGA_Controller:u8|add~2233 M1L202 = CARRY(K1_oCursor_Y[1]); --M1L203 is VGA_Controller:u8|add~2234 M1L203 = K1_oCursor_Y[2] & !M1L202 # !K1_oCursor_Y[2] & (M1L202 # GND); --M1L204 is VGA_Controller:u8|add~2235 M1L204 = CARRY(!M1L202 # !K1_oCursor_Y[2]); --M1L205 is VGA_Controller:u8|add~2236 M1L205 = K1_oCursor_Y[3] & (M1L204 $ GND) # !K1_oCursor_Y[3] & !M1L204 & VCC; --M1L206 is VGA_Controller:u8|add~2237 M1L206 = CARRY(K1_oCursor_Y[3] & !M1L204); --M1L207 is VGA_Controller:u8|add~2238 M1L207 = K1_oCursor_Y[4] & !M1L206 # !K1_oCursor_Y[4] & (M1L206 # GND); --M1L208 is VGA_Controller:u8|add~2239 M1L208 = CARRY(!M1L206 # !K1_oCursor_Y[4]); --M1L209 is VGA_Controller:u8|add~2240 M1L209 = M1L201 & !M1L200 # !M1L201 & (M1L200 # GND); --M1L210 is VGA_Controller:u8|add~2241 M1L210 = CARRY(!M1L200 # !M1L201); --M1L211 is VGA_Controller:u8|add~2242 M1L211 = M1L203 & (M1L210 $ GND) # !M1L203 & !M1L210 & VCC; --M1L212 is VGA_Controller:u8|add~2243 M1L212 = CARRY(M1L203 & !M1L210); --M1L213 is VGA_Controller:u8|add~2244 M1L213 = M1L205 & !M1L212 # !M1L205 & (M1L212 # GND); --M1L214 is VGA_Controller:u8|add~2245 M1L214 = CARRY(!M1L212 # !M1L205); --M1L215 is VGA_Controller:u8|add~2246 M1L215 = M1L207 & (M1L214 $ GND) # !M1L207 & !M1L214 & VCC; --M1L216 is VGA_Controller:u8|add~2247 M1L216 = CARRY(M1L207 & !M1L214); --M1L39 is VGA_Controller:u8|Equal~1117 M1L39 = M1_V_Cont[4] & M1L215 & (M1L199 $ !M1_V_Cont[0]) # !M1_V_Cont[4] & !M1L215 & (M1L199 $ !M1_V_Cont[0]); --K1_oCursor_Y[5] is CMD_Decode:u5|oCursor_Y[5] K1_oCursor_Y[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, KEY[0], , K1L69, , , , ); --M1L217 is VGA_Controller:u8|add~2248 M1L217 = K1_oCursor_Y[5] & (GND # !M1L208) # !K1_oCursor_Y[5] & (M1L208 $ GND); --M1L218 is VGA_Controller:u8|add~2249 M1L218 = CARRY(K1_oCursor_Y[5] # !M1L208); --M1L219 is VGA_Controller:u8|add~2250 M1L219 = M1L217 & !M1L216 # !M1L217 & (M1L216 # GND); --M1L220 is VGA_Controller:u8|add~2251 M1L220 = CARRY(!M1L216 # !M1L217); --M1L40 is VGA_Controller:u8|Equal~1118 M1L40 = M1_V_Cont[5] & M1L219 & (M1_V_Cont[1] $ !M1L209) # !M1_V_Cont[5] & !M1L219 & (M1_V_Cont[1] $ !M1L209); --K1_oCursor_Y[8] is CMD_Decode:u5|oCursor_Y[8] K1_oCursor_Y[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L69, , , , ); --K1_oCursor_Y[7] is CMD_Decode:u5|oCursor_Y[7] K1_oCursor_Y[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L69, , , , ); --K1_oCursor_Y[6] is CMD_Decode:u5|oCursor_Y[6] K1_oCursor_Y[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L69, , , , ); --M1L221 is VGA_Controller:u8|add~2252 M1L221 = K1_oCursor_Y[6] & !M1L218 # !K1_oCursor_Y[6] & (M1L218 # GND); --M1L222 is VGA_Controller:u8|add~2253 M1L222 = CARRY(!M1L218 # !K1_oCursor_Y[6]); --M1L223 is VGA_Controller:u8|add~2254 M1L223 = K1_oCursor_Y[7] & (M1L222 $ GND) # !K1_oCursor_Y[7] & !M1L222 & VCC; --M1L224 is VGA_Controller:u8|add~2255 M1L224 = CARRY(K1_oCursor_Y[7] & !M1L222); --M1L225 is VGA_Controller:u8|add~2256 M1L225 = K1_oCursor_Y[8] & !M1L224 # !K1_oCursor_Y[8] & (M1L224 # GND); --M1L226 is VGA_Controller:u8|add~2257 M1L226 = CARRY(!M1L224 # !K1_oCursor_Y[8]); --M1L227 is VGA_Controller:u8|add~2258 M1L227 = M1L221 & (M1L220 $ GND) # !M1L221 & !M1L220 & VCC; --M1L228 is VGA_Controller:u8|add~2259 M1L228 = CARRY(M1L221 & !M1L220); --M1L229 is VGA_Controller:u8|add~2260 M1L229 = M1L223 & !M1L228 # !M1L223 & (M1L228 # GND); --M1L230 is VGA_Controller:u8|add~2261 M1L230 = CARRY(!M1L228 # !M1L223); --M1L231 is VGA_Controller:u8|add~2262 M1L231 = M1L225 & (M1L230 $ GND) # !M1L225 & !M1L230 & VCC; --M1L232 is VGA_Controller:u8|add~2263 M1L232 = CARRY(M1L225 & !M1L230); --M1L41 is VGA_Controller:u8|Equal~1119 M1L41 = M1_V_Cont[8] & M1L231 & (M1_V_Cont[2] $ !M1L211) # !M1_V_Cont[8] & !M1L231 & (M1_V_Cont[2] $ !M1L211); --K1_oCursor_Y[9] is CMD_Decode:u5|oCursor_Y[9] K1_oCursor_Y[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L69, , , , ); --M1L233 is VGA_Controller:u8|add~2264 M1L233 = K1_oCursor_Y[9] & (M1L226 $ GND) # !K1_oCursor_Y[9] & !M1L226 & VCC; --M1L234 is VGA_Controller:u8|add~2265 M1L234 = CARRY(K1_oCursor_Y[9] & !M1L226); --M1L235 is VGA_Controller:u8|add~2266 M1L235 = M1L233 & !M1L232 # !M1L233 & (M1L232 # GND); --M1L236 is VGA_Controller:u8|add~2267 M1L236 = CARRY(!M1L232 # !M1L233); --M1L42 is VGA_Controller:u8|Equal~1120 M1L42 = M1_V_Cont[9] & M1L235 & (M1_V_Cont[3] $ !M1L213) # !M1_V_Cont[9] & !M1L235 & (M1_V_Cont[3] $ !M1L213); --M1L43 is VGA_Controller:u8|Equal~1121 M1L43 = M1L39 & M1L40 & M1L41 & M1L42; --M1L44 is VGA_Controller:u8|Equal~1122 M1L44 = M1_V_Cont[6] & M1L227 & (M1_V_Cont[7] $ !M1L229) # !M1_V_Cont[6] & !M1L227 & (M1_V_Cont[7] $ !M1L229); --M1L237 is VGA_Controller:u8|add~2268 M1L237 = M1L234; --M1L239 is VGA_Controller:u8|add~2270 M1L239 = M1L237 $ !M1L236; --M1L45 is VGA_Controller:u8|Equal~1123 M1L45 = M1L43 & M1L44 & !M1L239; --K1_oCursor_X[4] is CMD_Decode:u5|oCursor_X[4] K1_oCursor_X[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, KEY[0], , K1L70, , , , ); --K1_oCursor_X[3] is CMD_Decode:u5|oCursor_X[3] K1_oCursor_X[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, KEY[0], , K1L70, , , , ); --K1_oCursor_X[2] is CMD_Decode:u5|oCursor_X[2] K1_oCursor_X[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, KEY[0], , K1L70, , , , ); --M1L241 is VGA_Controller:u8|add~2272 M1L241 = K1_oCursor_X[2] $ VCC; --M1L242 is VGA_Controller:u8|add~2273 M1L242 = CARRY(K1_oCursor_X[2]); --M1L243 is VGA_Controller:u8|add~2274 M1L243 = K1_oCursor_X[3] & M1L242 & VCC # !K1_oCursor_X[3] & !M1L242; --M1L244 is VGA_Controller:u8|add~2275 M1L244 = CARRY(!K1_oCursor_X[3] & !M1L242); --M1L245 is VGA_Controller:u8|add~2276 M1L245 = K1_oCursor_X[4] & (GND # !M1L244) # !K1_oCursor_X[4] & (M1L244 $ GND); --M1L246 is VGA_Controller:u8|add~2277 M1L246 = CARRY(K1_oCursor_X[4] # !M1L244); --K1_oCursor_X[1] is CMD_Decode:u5|oCursor_X[1] K1_oCursor_X[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L70, , , , ); --K1_oCursor_X[0] is CMD_Decode:u5|oCursor_X[0] K1_oCursor_X[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L70, , , , ); --M1L247 is VGA_Controller:u8|add~2278 M1L247 = K1_oCursor_X[0] $ VCC; --M1L248 is VGA_Controller:u8|add~2279 M1L248 = CARRY(K1_oCursor_X[0]); --M1L249 is VGA_Controller:u8|add~2280 M1L249 = K1_oCursor_X[1] & !M1L248 # !K1_oCursor_X[1] & (M1L248 # GND); --M1L250 is VGA_Controller:u8|add~2281 M1L250 = CARRY(!M1L248 # !K1_oCursor_X[1]); --M1L251 is VGA_Controller:u8|add~2282 M1L251 = M1L241 & (M1L250 $ GND) # !M1L241 & !M1L250 & VCC; --M1L252 is VGA_Controller:u8|add~2283 M1L252 = CARRY(M1L241 & !M1L250); --M1L253 is VGA_Controller:u8|add~2284 M1L253 = M1L243 & !M1L252 # !M1L243 & (M1L252 # GND); --M1L254 is VGA_Controller:u8|add~2285 M1L254 = CARRY(!M1L252 # !M1L243); --M1L255 is VGA_Controller:u8|add~2286 M1L255 = M1L245 & (M1L254 $ GND) # !M1L245 & !M1L254 & VCC; --M1L256 is VGA_Controller:u8|add~2287 M1L256 = CARRY(M1L245 & !M1L254); --M1L46 is VGA_Controller:u8|Equal~1124 M1L46 = M1_H_Cont[0] & M1L247 & (M1_H_Cont[4] $ !M1L255) # !M1_H_Cont[0] & !M1L247 & (M1_H_Cont[4] $ !M1L255); --K1_oCursor_X[5] is CMD_Decode:u5|oCursor_X[5] K1_oCursor_X[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, KEY[0], , K1L70, , , , ); --M1L257 is VGA_Controller:u8|add~2288 M1L257 = K1_oCursor_X[5] & !M1L246 # !K1_oCursor_X[5] & (M1L246 # GND); --M1L258 is VGA_Controller:u8|add~2289 M1L258 = CARRY(!M1L246 # !K1_oCursor_X[5]); --M1L259 is VGA_Controller:u8|add~2290 M1L259 = M1L257 & !M1L256 # !M1L257 & (M1L256 # GND); --M1L260 is VGA_Controller:u8|add~2291 M1L260 = CARRY(!M1L256 # !M1L257); --M1L47 is VGA_Controller:u8|Equal~1125 M1L47 = M1_H_Cont[1] & M1L249 & (M1_H_Cont[5] $ !M1L259) # !M1_H_Cont[1] & !M1L249 & (M1_H_Cont[5] $ !M1L259); --K1_oCursor_X[8] is CMD_Decode:u5|oCursor_X[8] K1_oCursor_X[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L70, , , , ); --K1_oCursor_X[7] is CMD_Decode:u5|oCursor_X[7] K1_oCursor_X[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L70, , , , ); --K1_oCursor_X[6] is CMD_Decode:u5|oCursor_X[6] K1_oCursor_X[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L70, , , , ); --M1L261 is VGA_Controller:u8|add~2292 M1L261 = K1_oCursor_X[6] & (M1L258 $ GND) # !K1_oCursor_X[6] & !M1L258 & VCC; --M1L262 is VGA_Controller:u8|add~2293 M1L262 = CARRY(K1_oCursor_X[6] & !M1L258); --M1L263 is VGA_Controller:u8|add~2294 M1L263 = K1_oCursor_X[7] & M1L262 & VCC # !K1_oCursor_X[7] & !M1L262; --M1L264 is VGA_Controller:u8|add~2295 M1L264 = CARRY(!K1_oCursor_X[7] & !M1L262); --M1L265 is VGA_Controller:u8|add~2296 M1L265 = K1_oCursor_X[8] & (M1L264 $ GND) # !K1_oCursor_X[8] & !M1L264 & VCC; --M1L266 is VGA_Controller:u8|add~2297 M1L266 = CARRY(K1_oCursor_X[8] & !M1L264); --M1L267 is VGA_Controller:u8|add~2298 M1L267 = M1L261 & (M1L260 $ GND) # !M1L261 & !M1L260 & VCC; --M1L268 is VGA_Controller:u8|add~2299 M1L268 = CARRY(M1L261 & !M1L260); --M1L269 is VGA_Controller:u8|add~2300 M1L269 = M1L263 & !M1L268 # !M1L263 & (M1L268 # GND); --M1L270 is VGA_Controller:u8|add~2301 M1L270 = CARRY(!M1L268 # !M1L263); --M1L271 is VGA_Controller:u8|add~2302 M1L271 = M1L265 & (M1L270 $ GND) # !M1L265 & !M1L270 & VCC; --M1L272 is VGA_Controller:u8|add~2303 M1L272 = CARRY(M1L265 & !M1L270); --M1L48 is VGA_Controller:u8|Equal~1126 M1L48 = M1_H_Cont[2] & M1L251 & (M1_H_Cont[8] $ !M1L271) # !M1_H_Cont[2] & !M1L251 & (M1_H_Cont[8] $ !M1L271); --K1_oCursor_X[9] is CMD_Decode:u5|oCursor_X[9] K1_oCursor_X[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L70, , , , ); --M1L273 is VGA_Controller:u8|add~2304 M1L273 = K1_oCursor_X[9] & !M1L266 # !K1_oCursor_X[9] & (M1L266 # GND); --M1L274 is VGA_Controller:u8|add~2305 M1L274 = CARRY(!M1L266 # !K1_oCursor_X[9]); --M1L275 is VGA_Controller:u8|add~2306 M1L275 = M1L273 & !M1L272 # !M1L273 & (M1L272 # GND); --M1L276 is VGA_Controller:u8|add~2307 M1L276 = CARRY(!M1L272 # !M1L273); --M1L49 is VGA_Controller:u8|Equal~1127 M1L49 = M1_H_Cont[3] & M1L253 & (M1_H_Cont[9] $ !M1L275) # !M1_H_Cont[3] & !M1L253 & (M1_H_Cont[9] $ !M1L275); --M1L50 is VGA_Controller:u8|Equal~1128 M1L50 = M1L46 & M1L47 & M1L48 & M1L49; --M1L51 is VGA_Controller:u8|Equal~1129 M1L51 = M1_H_Cont[7] & M1L269 & (M1_H_Cont[6] $ !M1L267) # !M1_H_Cont[7] & !M1L269 & (M1_H_Cont[6] $ !M1L267); --M1L277 is VGA_Controller:u8|add~2308 M1L277 = !M1L274; --M1L279 is VGA_Controller:u8|add~2310 M1L279 = M1L277 $ !M1L276; --M1L331 is VGA_Controller:u8|always1~273 M1L331 = M1L45 # M1L50 & M1L51 & !M1L279; --M1L281 is VGA_Controller:u8|add~2312 M1L281 = K1_oCursor_X[0] $ VCC; --M1L282 is VGA_Controller:u8|add~2313 M1L282 = CARRY(K1_oCursor_X[0]); --M1L283 is VGA_Controller:u8|add~2314 M1L283 = K1_oCursor_X[1] & M1L282 & VCC # !K1_oCursor_X[1] & !M1L282; --M1L284 is VGA_Controller:u8|add~2315 M1L284 = CARRY(!K1_oCursor_X[1] & !M1L282); --M1L285 is VGA_Controller:u8|add~2316 M1L285 = M1L241 & (GND # !M1L284) # !M1L241 & (M1L284 $ GND); --M1L286 is VGA_Controller:u8|add~2317 M1L286 = CARRY(M1L241 # !M1L284); --M1L287 is VGA_Controller:u8|add~2318 M1L287 = M1L243 & M1L286 & VCC # !M1L243 & !M1L286; --M1L288 is VGA_Controller:u8|add~2319 M1L288 = CARRY(!M1L243 & !M1L286); --M1L289 is VGA_Controller:u8|add~2320 M1L289 = M1L245 & (GND # !M1L288) # !M1L245 & (M1L288 $ GND); --M1L290 is VGA_Controller:u8|add~2321 M1L290 = CARRY(M1L245 # !M1L288); --M1L291 is VGA_Controller:u8|add~2322 M1L291 = M1L257 & M1L290 & VCC # !M1L257 & !M1L290; --M1L292 is VGA_Controller:u8|add~2323 M1L292 = CARRY(!M1L257 & !M1L290); --M1L293 is VGA_Controller:u8|add~2324 M1L293 = M1L261 & (GND # !M1L292) # !M1L261 & (M1L292 $ GND); --M1L294 is VGA_Controller:u8|add~2325 M1L294 = CARRY(M1L261 # !M1L292); --M1L295 is VGA_Controller:u8|add~2326 M1L295 = M1L263 & M1L294 & VCC # !M1L263 & !M1L294; --M1L296 is VGA_Controller:u8|add~2327 M1L296 = CARRY(!M1L263 & !M1L294); --M1L297 is VGA_Controller:u8|add~2328 M1L297 = M1L265 & (GND # !M1L296) # !M1L265 & (M1L296 $ GND); --M1L298 is VGA_Controller:u8|add~2329 M1L298 = CARRY(M1L265 # !M1L296); --M1L299 is VGA_Controller:u8|add~2330 M1L299 = M1L273 & M1L298 & VCC # !M1L273 & !M1L298; --M1L300 is VGA_Controller:u8|add~2331 M1L300 = CARRY(!M1L273 & !M1L298); --M1L301 is VGA_Controller:u8|add~2332 M1L301 = M1L277 & (GND # !M1L300) # !M1L277 & (M1L300 $ GND); --M1L302 is VGA_Controller:u8|add~2333 M1L302 = CARRY(M1L277 # !M1L300); --M1L303 is VGA_Controller:u8|add~2334 M1L303 = M1L302; --M1L52 is VGA_Controller:u8|Equal~1130 M1L52 = M1_H_Cont[2] & M1L285 & (M1_H_Cont[8] $ !M1L297) # !M1_H_Cont[2] & !M1L285 & (M1_H_Cont[8] $ !M1L297); --M1L53 is VGA_Controller:u8|Equal~1131 M1L53 = M1_H_Cont[7] & M1L295 & (M1_H_Cont[9] $ !M1L299) # !M1_H_Cont[7] & !M1L295 & (M1_H_Cont[9] $ !M1L299); --M1L54 is VGA_Controller:u8|Equal~1132 M1L54 = M1_H_Cont[1] & M1L283 & (M1_H_Cont[6] $ !M1L293) # !M1_H_Cont[1] & !M1L283 & (M1_H_Cont[6] $ !M1L293); --M1L55 is VGA_Controller:u8|Equal~1133 M1L55 = M1_H_Cont[0] & M1L281 & (M1_H_Cont[3] $ !M1L287) # !M1_H_Cont[0] & !M1L281 & (M1_H_Cont[3] $ !M1L287); --M1L56 is VGA_Controller:u8|Equal~1134 M1L56 = M1L52 & M1L53 & M1L54 & M1L55; --M1L57 is VGA_Controller:u8|Equal~1135 M1L57 = M1_H_Cont[4] & M1L289 & (M1_H_Cont[5] $ !M1L291) # !M1_H_Cont[4] & !M1L289 & (M1_H_Cont[5] $ !M1L291); --M1L58 is VGA_Controller:u8|Equal~1136 M1L58 = M1L303 & M1L56 & M1L57 & !M1L301; --M1L59 is VGA_Controller:u8|Equal~1137 M1L59 = M1_H_Cont[3] & M1L243 & (M1_H_Cont[9] $ !M1L273) # !M1_H_Cont[3] & !M1L243 & (M1_H_Cont[9] $ !M1L273); --M1L60 is VGA_Controller:u8|Equal~1138 M1L60 = M1_H_Cont[7] & M1L263 & (M1_H_Cont[6] $ !M1L261) # !M1_H_Cont[7] & !M1L263 & (M1_H_Cont[6] $ !M1L261); --M1L61 is VGA_Controller:u8|Equal~1139 M1L61 = M1_H_Cont[0] & K1_oCursor_X[0] & (M1_H_Cont[4] $ !M1L245) # !M1_H_Cont[0] & !K1_oCursor_X[0] & (M1_H_Cont[4] $ !M1L245); --M1L62 is VGA_Controller:u8|Equal~1140 M1L62 = M1_H_Cont[1] & K1_oCursor_X[1] & (M1_H_Cont[5] $ !M1L257) # !M1_H_Cont[1] & !K1_oCursor_X[1] & (M1_H_Cont[5] $ !M1L257); --M1L63 is VGA_Controller:u8|Equal~1141 M1L63 = M1L59 & M1L60 & M1L61 & M1L62; --M1L64 is VGA_Controller:u8|Equal~1142 M1L64 = M1_H_Cont[2] & M1L241 & (M1_H_Cont[8] $ !M1L265) # !M1_H_Cont[2] & !M1L241 & (M1_H_Cont[8] $ !M1L265); --M1L332 is VGA_Controller:u8|always1~274 M1L332 = M1L58 # M1L63 & M1L64 & !M1L277; --M1L65 is VGA_Controller:u8|Equal~1143 M1L65 = M1_V_Cont[9] & M1L233 & (M1_V_Cont[3] $ !M1L205) # !M1_V_Cont[9] & !M1L233 & (M1_V_Cont[3] $ !M1L205); --M1L66 is VGA_Controller:u8|Equal~1144 M1L66 = M1_V_Cont[6] & M1L221 & (M1_V_Cont[7] $ !M1L223) # !M1_V_Cont[6] & !M1L221 & (M1_V_Cont[7] $ !M1L223); --M1L67 is VGA_Controller:u8|Equal~1145 M1L67 = M1_V_Cont[4] & M1L207 & (K1_oCursor_Y[0] $ !M1_V_Cont[0]) # !M1_V_Cont[4] & !M1L207 & (K1_oCursor_Y[0] $ !M1_V_Cont[0]); --M1L68 is VGA_Controller:u8|Equal~1146 M1L68 = M1_V_Cont[5] & M1L217 & (M1_V_Cont[1] $ !M1L201) # !M1_V_Cont[5] & !M1L217 & (M1_V_Cont[1] $ !M1L201); --M1L69 is VGA_Controller:u8|Equal~1147 M1L69 = M1L65 & M1L66 & M1L67 & M1L68; --M1L70 is VGA_Controller:u8|Equal~1148 M1L70 = M1_V_Cont[8] & M1L225 & (M1_V_Cont[2] $ !M1L203) # !M1_V_Cont[8] & !M1L225 & (M1_V_Cont[2] $ !M1L203); --M1L71 is VGA_Controller:u8|Equal~1149 M1L71 = M1L69 & M1L70 & !M1L237; --M1L305 is VGA_Controller:u8|add~2336 M1L305 = K1_oCursor_Y[0] $ VCC; --M1L306 is VGA_Controller:u8|add~2337 M1L306 = CARRY(K1_oCursor_Y[0]); --M1L307 is VGA_Controller:u8|add~2338 M1L307 = M1L201 & M1L306 & VCC # !M1L201 & !M1L306; --M1L308 is VGA_Controller:u8|add~2339 M1L308 = CARRY(!M1L201 & !M1L306); --M1L309 is VGA_Controller:u8|add~2340 M1L309 = M1L203 & (GND # !M1L308) # !M1L203 & (M1L308 $ GND); --M1L310 is VGA_Controller:u8|add~2341 M1L310 = CARRY(M1L203 # !M1L308); --M1L311 is VGA_Controller:u8|add~2342 M1L311 = M1L205 & M1L310 & VCC # !M1L205 & !M1L310; --M1L312 is VGA_Controller:u8|add~2343 M1L312 = CARRY(!M1L205 & !M1L310); --M1L313 is VGA_Controller:u8|add~2344 M1L313 = M1L207 & (GND # !M1L312) # !M1L207 & (M1L312 $ GND); --M1L314 is VGA_Controller:u8|add~2345 M1L314 = CARRY(M1L207 # !M1L312); --M1L315 is VGA_Controller:u8|add~2346 M1L315 = M1L217 & M1L314 & VCC # !M1L217 & !M1L314; --M1L316 is VGA_Controller:u8|add~2347 M1L316 = CARRY(!M1L217 & !M1L314); --M1L317 is VGA_Controller:u8|add~2348 M1L317 = M1L221 & (GND # !M1L316) # !M1L221 & (M1L316 $ GND); --M1L318 is VGA_Controller:u8|add~2349 M1L318 = CARRY(M1L221 # !M1L316); --M1L319 is VGA_Controller:u8|add~2350 M1L319 = M1L223 & M1L318 & VCC # !M1L223 & !M1L318; --M1L320 is VGA_Controller:u8|add~2351 M1L320 = CARRY(!M1L223 & !M1L318); --M1L321 is VGA_Controller:u8|add~2352 M1L321 = M1L225 & (GND # !M1L320) # !M1L225 & (M1L320 $ GND); --M1L322 is VGA_Controller:u8|add~2353 M1L322 = CARRY(M1L225 # !M1L320); --M1L323 is VGA_Controller:u8|add~2354 M1L323 = M1L233 & M1L322 & VCC # !M1L233 & !M1L322; --M1L324 is VGA_Controller:u8|add~2355 M1L324 = CARRY(!M1L233 & !M1L322); --M1L325 is VGA_Controller:u8|add~2356 M1L325 = M1L237 & (GND # !M1L324) # !M1L237 & (M1L324 $ GND); --M1L326 is VGA_Controller:u8|add~2357 M1L326 = CARRY(M1L237 # !M1L324); --M1L327 is VGA_Controller:u8|add~2358 M1L327 = M1L326; --M1L72 is VGA_Controller:u8|Equal~1150 M1L72 = M1_V_Cont[8] & M1L321 & (M1_V_Cont[2] $ !M1L309) # !M1_V_Cont[8] & !M1L321 & (M1_V_Cont[2] $ !M1L309); --M1L73 is VGA_Controller:u8|Equal~1151 M1L73 = M1_V_Cont[9] & M1L323 & (M1_V_Cont[7] $ !M1L319) # !M1_V_Cont[9] & !M1L323 & (M1_V_Cont[7] $ !M1L319); --M1L74 is VGA_Controller:u8|Equal~1152 M1L74 = M1_V_Cont[6] & M1L317 & (M1_V_Cont[1] $ !M1L307) # !M1_V_Cont[6] & !M1L317 & (M1_V_Cont[1] $ !M1L307); --M1L75 is VGA_Controller:u8|Equal~1153 M1L75 = M1_V_Cont[3] & M1L311 & (M1_V_Cont[0] $ !M1L305) # !M1_V_Cont[3] & !M1L311 & (M1_V_Cont[0] $ !M1L305); --M1L76 is VGA_Controller:u8|Equal~1154 M1L76 = M1L72 & M1L73 & M1L74 & M1L75; --M1L77 is VGA_Controller:u8|Equal~1155 M1L77 = M1_V_Cont[4] & M1L313 & (M1_V_Cont[5] $ !M1L315) # !M1_V_Cont[4] & !M1L313 & (M1_V_Cont[5] $ !M1L315); --M1L78 is VGA_Controller:u8|Equal~1156 M1L78 = M1L327 & M1L76 & M1L77 & !M1L325; --M1L333 is VGA_Controller:u8|always1~275 M1L333 = M1L331 # M1L332 # M1L71 # M1L78; --M1L117 is VGA_Controller:u8|LessThan~1418 M1L117 = M1L34 & (!M1_H_Cont[4] # !M1_H_Cont[3] # !M1_H_Cont[2]); --M1L6 is VGA_Controller:u8|Cur_Color_B~227 M1L6 = M1_H_Cont[8] & (M1L117 & !M1_H_Cont[7] # !M1_H_Cont[9]) # !M1_H_Cont[8] & (M1_H_Cont[9] # !M1L117 & M1_H_Cont[7]); --M1L7 is VGA_Controller:u8|Cur_Color_B~228 M1L7 = M1L463 & K1_oOSD_CUR_EN[0] & M1L333 & M1L6; --M1L81 is VGA_Controller:u8|H_Cont[0]~265 M1L81 = M1_H_Cont[0] $ VCC; --M1L82 is VGA_Controller:u8|H_Cont[0]~266 M1L82 = CARRY(M1_H_Cont[0]); --M1L84 is VGA_Controller:u8|H_Cont[1]~267 M1L84 = M1_H_Cont[1] & !M1L82 # !M1_H_Cont[1] & (M1L82 # GND); --M1L85 is VGA_Controller:u8|H_Cont[1]~268 M1L85 = CARRY(!M1L82 # !M1_H_Cont[1]); --M1L87 is VGA_Controller:u8|H_Cont[2]~269 M1L87 = M1_H_Cont[2] & (M1L85 $ GND) # !M1_H_Cont[2] & !M1L85 & VCC; --M1L88 is VGA_Controller:u8|H_Cont[2]~270 M1L88 = CARRY(M1_H_Cont[2] & !M1L85); --M1L90 is VGA_Controller:u8|H_Cont[3]~271 M1L90 = M1_H_Cont[3] & !M1L88 # !M1_H_Cont[3] & (M1L88 # GND); --M1L91 is VGA_Controller:u8|H_Cont[3]~272 M1L91 = CARRY(!M1L88 # !M1_H_Cont[3]); --M1L93 is VGA_Controller:u8|H_Cont[4]~273 M1L93 = M1_H_Cont[4] & (M1L91 $ GND) # !M1_H_Cont[4] & !M1L91 & VCC; --M1L94 is VGA_Controller:u8|H_Cont[4]~274 M1L94 = CARRY(M1_H_Cont[4] & !M1L91); --M1L96 is VGA_Controller:u8|H_Cont[5]~275 M1L96 = M1_H_Cont[5] & !M1L94 # !M1_H_Cont[5] & (M1L94 # GND); --M1L97 is VGA_Controller:u8|H_Cont[5]~276 M1L97 = CARRY(!M1L94 # !M1_H_Cont[5]); --M1L118 is VGA_Controller:u8|LessThan~1419 M1L118 = M1_H_Cont[8] & M1_H_Cont[9] & (M1_H_Cont[7] # !M1L34); --M1L99 is VGA_Controller:u8|H_Cont[6]~277 M1L99 = M1_H_Cont[6] & (M1L97 $ GND) # !M1_H_Cont[6] & !M1L97 & VCC; --M1L100 is VGA_Controller:u8|H_Cont[6]~278 M1L100 = CARRY(M1_H_Cont[6] & !M1L97); --M1L102 is VGA_Controller:u8|H_Cont[7]~279 M1L102 = M1_H_Cont[7] & !M1L100 # !M1_H_Cont[7] & (M1L100 # GND); --M1L103 is VGA_Controller:u8|H_Cont[7]~280 M1L103 = CARRY(!M1L100 # !M1_H_Cont[7]); --M1L105 is VGA_Controller:u8|H_Cont[8]~281 M1L105 = M1_H_Cont[8] & (M1L103 $ GND) # !M1_H_Cont[8] & !M1L103 & VCC; --M1L106 is VGA_Controller:u8|H_Cont[8]~282 M1L106 = CARRY(M1_H_Cont[8] & !M1L103); --M1L108 is VGA_Controller:u8|H_Cont[9]~283 M1L108 = M1_H_Cont[9] $ M1L106; --M1L126 is VGA_Controller:u8|V_Cont[0]~1012 M1L126 = M1_V_Cont[0] $ VCC; --M1L127 is VGA_Controller:u8|V_Cont[0]~1013 M1L127 = CARRY(M1_V_Cont[0]); --M1L129 is VGA_Controller:u8|V_Cont[1]~1014 M1L129 = M1_V_Cont[1] & !M1L127 # !M1_V_Cont[1] & (M1L127 # GND); --M1L130 is VGA_Controller:u8|V_Cont[1]~1015 M1L130 = CARRY(!M1L127 # !M1_V_Cont[1]); --M1L132 is VGA_Controller:u8|V_Cont[2]~1016 M1L132 = M1_V_Cont[2] & (M1L130 $ GND) # !M1_V_Cont[2] & !M1L130 & VCC; --M1L133 is VGA_Controller:u8|V_Cont[2]~1017 M1L133 = CARRY(M1_V_Cont[2] & !M1L130); --M1L135 is VGA_Controller:u8|V_Cont[3]~1018 M1L135 = M1_V_Cont[3] & !M1L133 # !M1_V_Cont[3] & (M1L133 # GND); --M1L136 is VGA_Controller:u8|V_Cont[3]~1019 M1L136 = CARRY(!M1L133 # !M1_V_Cont[3]); --M1L138 is VGA_Controller:u8|V_Cont[4]~1020 M1L138 = M1_V_Cont[4] & (M1L136 $ GND) # !M1_V_Cont[4] & !M1L136 & VCC; --M1L139 is VGA_Controller:u8|V_Cont[4]~1021 M1L139 = CARRY(M1_V_Cont[4] & !M1L136); --M1L141 is VGA_Controller:u8|V_Cont[5]~1022 M1L141 = M1_V_Cont[5] & !M1L139 # !M1_V_Cont[5] & (M1L139 # GND); --M1L142 is VGA_Controller:u8|V_Cont[5]~1023 M1L142 = CARRY(!M1L139 # !M1_V_Cont[5]); --M1L144 is VGA_Controller:u8|V_Cont[6]~1024 M1L144 = M1_V_Cont[6] & (M1L142 $ GND) # !M1_V_Cont[6] & !M1L142 & VCC; --M1L145 is VGA_Controller:u8|V_Cont[6]~1025 M1L145 = CARRY(M1_V_Cont[6] & !M1L142); --M1L119 is VGA_Controller:u8|LessThan~1420 M1L119 = M1L112 & !M1_V_Cont[4] & !M1_V_Cont[5]; --M1L120 is VGA_Controller:u8|LessThan~1421 M1L120 = !M1_V_Cont[1] & !M1_V_Cont[0] # !M1_V_Cont[3] # !M1_V_Cont[2]; --M1L121 is VGA_Controller:u8|LessThan~1422 M1L121 = M1_V_Cont[9] & (!M1L120 # !M1L119); --M1L147 is VGA_Controller:u8|V_Cont[7]~1026 M1L147 = M1_V_Cont[7] & !M1L145 # !M1_V_Cont[7] & (M1L145 # GND); --M1L148 is VGA_Controller:u8|V_Cont[7]~1027 M1L148 = CARRY(!M1L145 # !M1_V_Cont[7]); --M1L150 is VGA_Controller:u8|V_Cont[8]~1028 M1L150 = M1_V_Cont[8] & (M1L148 $ GND) # !M1_V_Cont[8] & !M1L148 & VCC; --M1L151 is VGA_Controller:u8|V_Cont[8]~1029 M1L151 = CARRY(M1_V_Cont[8] & !M1L148); --M1L153 is VGA_Controller:u8|V_Cont[9]~1030 M1L153 = M1_V_Cont[9] $ M1L151; --A1L348 is mVGA_R[7]~264 A1L348 = L1L1 & (M1_oAddress[0] & A1L303 # !M1_oAddress[0] & (A1L287)); --M1L26 is VGA_Controller:u8|Cur_Color_R[7]~53 M1L26 = K1_oOSD_CUR_EN[1] & (A1L348) # !K1_oOSD_CUR_EN[1] & N1_oRed[8]; --K1_oCursor_R[7] is CMD_Decode:u5|oCursor_R[7] K1_oCursor_R[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L68, , , , ); --A1L349 is mVGA_R[8]~265 A1L349 = L1L1 & (M1_oAddress[0] & A1L305 # !M1_oAddress[0] & (A1L289)); --M1L29 is VGA_Controller:u8|Cur_Color_R[8]~54 M1L29 = K1_oOSD_CUR_EN[1] & (A1L349) # !K1_oOSD_CUR_EN[1] & N1_oRed[8]; --K1_oCursor_R[8] is CMD_Decode:u5|oCursor_R[8] K1_oCursor_R[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L68, , , , ); --A1L350 is mVIN_R[9]~71 A1L350 = L1L1 & (M1_oAddress[0] & A1L307 # !M1_oAddress[0] & (A1L291)); --M1L32 is VGA_Controller:u8|Cur_Color_R[9]~55 M1L32 = K1_oOSD_CUR_EN[1] & (A1L350) # !K1_oOSD_CUR_EN[1] & N1_oRed[8]; --K1_oCursor_R[9] is CMD_Decode:u5|oCursor_R[9] K1_oCursor_R[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L68, , , , ); --K1_oCursor_G[6] is CMD_Decode:u5|oCursor_G[6] K1_oCursor_G[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L71, , , , ); --M1L17 is VGA_Controller:u8|Cur_Color_G~100 M1L17 = M1L7 & K1_oCursor_G[6] # !M1L7 & (M1L23); --K1_oCursor_G[7] is CMD_Decode:u5|oCursor_G[7] K1_oCursor_G[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L71, , , , ); --M1L18 is VGA_Controller:u8|Cur_Color_G~101 M1L18 = M1L7 & K1_oCursor_G[7] # !M1L7 & (M1L26); --K1_oCursor_G[8] is CMD_Decode:u5|oCursor_G[8] K1_oCursor_G[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L71, , , , ); --M1L19 is VGA_Controller:u8|Cur_Color_G~102 M1L19 = M1L7 & K1_oCursor_G[8] # !M1L7 & (M1L29); --K1_oCursor_G[9] is CMD_Decode:u5|oCursor_G[9] K1_oCursor_G[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L71, , , , ); --M1L20 is VGA_Controller:u8|Cur_Color_G~103 M1L20 = M1L7 & K1_oCursor_G[9] # !M1L7 & (M1L32); --K1_oCursor_B[6] is CMD_Decode:u5|oCursor_B[6] K1_oCursor_B[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, KEY[0], , K1L72, , , , ); --M1L8 is VGA_Controller:u8|Cur_Color_B~229 M1L8 = M1L7 & K1_oCursor_B[6] # !M1L7 & (M1L23); --K1_oCursor_B[7] is CMD_Decode:u5|oCursor_B[7] K1_oCursor_B[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, KEY[0], , K1L72, , , , ); --M1L9 is VGA_Controller:u8|Cur_Color_B~230 M1L9 = M1L7 & K1_oCursor_B[7] # !M1L7 & (M1L26); --K1_oCursor_B[8] is CMD_Decode:u5|oCursor_B[8] K1_oCursor_B[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, KEY[0], , K1L72, , , , ); --M1L10 is VGA_Controller:u8|Cur_Color_B~231 M1L10 = M1L7 & K1_oCursor_B[8] # !M1L7 & (M1L29); --K1_oCursor_B[9] is CMD_Decode:u5|oCursor_B[9] K1_oCursor_B[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, KEY[0], , K1L72, , , , ); --N1_oBlue[9] is VGA_OSD_RAM:u9|oBlue[9] N1_oBlue[9] = DFFEAS(VCC, S2__clk0, KEY[0], , , , , , ); --A1L346 is mVGA_B[9]~47 A1L346 = K1_oOSD_CUR_EN[1] & A1L350 # !K1_oOSD_CUR_EN[1] & (N1_oBlue[9]); --M1L11 is VGA_Controller:u8|Cur_Color_B~232 M1L11 = M1L7 & K1_oCursor_B[9] # !M1L7 & (A1L346); --Q1_LRCK_1X_DIV[0] is AUDIO_DAC:u11|LRCK_1X_DIV[0] Q1_LRCK_1X_DIV[0] = DFFEAS(Q1L112, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[1] is AUDIO_DAC:u11|LRCK_1X_DIV[1] Q1_LRCK_1X_DIV[1] = DFFEAS(Q1L115, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[2] is AUDIO_DAC:u11|LRCK_1X_DIV[2] Q1_LRCK_1X_DIV[2] = DFFEAS(Q1L118, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[3] is AUDIO_DAC:u11|LRCK_1X_DIV[3] Q1_LRCK_1X_DIV[3] = DFFEAS(Q1L121, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1L190 is AUDIO_DAC:u11|LessThan~864 Q1L190 = !Q1_LRCK_1X_DIV[3] # !Q1_LRCK_1X_DIV[2] # !Q1_LRCK_1X_DIV[1] # !Q1_LRCK_1X_DIV[0]; --Q1_LRCK_1X_DIV[4] is AUDIO_DAC:u11|LRCK_1X_DIV[4] Q1_LRCK_1X_DIV[4] = DFFEAS(Q1L124, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[5] is AUDIO_DAC:u11|LRCK_1X_DIV[5] Q1_LRCK_1X_DIV[5] = DFFEAS(Q1L127, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1L191 is AUDIO_DAC:u11|LessThan~865 Q1L191 = Q1L190 # !Q1_LRCK_1X_DIV[5] # !Q1_LRCK_1X_DIV[4]; --Q1_LRCK_1X_DIV[6] is AUDIO_DAC:u11|LRCK_1X_DIV[6] Q1_LRCK_1X_DIV[6] = DFFEAS(Q1L130, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[7] is AUDIO_DAC:u11|LRCK_1X_DIV[7] Q1_LRCK_1X_DIV[7] = DFFEAS(Q1L133, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1_LRCK_1X_DIV[8] is AUDIO_DAC:u11|LRCK_1X_DIV[8] Q1_LRCK_1X_DIV[8] = DFFEAS(Q1L136, S2__clk1, B1_oRESET, , , , , Q1L192, ); --Q1L192 is AUDIO_DAC:u11|LessThan~866 Q1L192 = Q1_LRCK_1X_DIV[8] # Q1_LRCK_1X_DIV[7] & (Q1_LRCK_1X_DIV[6] # !Q1L191); --Q1L138 is AUDIO_DAC:u11|LRCK_1X~51 Q1L138 = Q1_LRCK_1X $ Q1L192; --Q1_FLASH_Out_Tmp[5] is AUDIO_DAC:u11|FLASH_Out_Tmp[5] Q1_FLASH_Out_Tmp[5] = DFFEAS(W1L28, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_LRCK_2X is AUDIO_DAC:u11|LRCK_2X Q1_LRCK_2X = DFFEAS(Q1L165, S2__clk1, B1_oRESET, , , , , , ); --Q1L231 is AUDIO_DAC:u11|SEL_Cont[1]~48 Q1L231 = Q1_SEL_Cont[1] $ Q1_SEL_Cont[0]; --Q1_oAUD_BCK is AUDIO_DAC:u11|oAUD_BCK Q1_oAUD_BCK = DFFEAS(Q1L237, S2__clk1, B1_oRESET, , , , , , ); --Q1_FLASH_Out_Tmp[6] is AUDIO_DAC:u11|FLASH_Out_Tmp[6] Q1_FLASH_Out_Tmp[6] = DFFEAS(W1L29, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[7] is AUDIO_DAC:u11|FLASH_Out_Tmp[7] Q1_FLASH_Out_Tmp[7] = DFFEAS(W1L30, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[4] is AUDIO_DAC:u11|FLASH_Out_Tmp[4] Q1_FLASH_Out_Tmp[4] = DFFEAS(W1L27, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1L235 is AUDIO_DAC:u11|SEL_Cont[3]~49 Q1L235 = Q1_SEL_Cont[3] $ (Q1_SEL_Cont[1] & Q1_SEL_Cont[0] & Q1_SEL_Cont[2]); --Q1_FLASH_Out_Tmp[10] is AUDIO_DAC:u11|FLASH_Out_Tmp[10] Q1_FLASH_Out_Tmp[10] = DFFEAS(W1L25, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[9] is AUDIO_DAC:u11|FLASH_Out_Tmp[9] Q1_FLASH_Out_Tmp[9] = DFFEAS(W1L24, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[11] is AUDIO_DAC:u11|FLASH_Out_Tmp[11] Q1_FLASH_Out_Tmp[11] = DFFEAS(W1L26, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[8] is AUDIO_DAC:u11|FLASH_Out_Tmp[8] Q1_FLASH_Out_Tmp[8] = DFFEAS(W1L23, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1L233 is AUDIO_DAC:u11|SEL_Cont[2]~50 Q1L233 = Q1_SEL_Cont[2] $ (Q1_SEL_Cont[1] & Q1_SEL_Cont[0]); --Q1_FLASH_Out_Tmp[14] is AUDIO_DAC:u11|FLASH_Out_Tmp[14] Q1_FLASH_Out_Tmp[14] = DFFEAS(W1L29, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[13] is AUDIO_DAC:u11|FLASH_Out_Tmp[13] Q1_FLASH_Out_Tmp[13] = DFFEAS(W1L28, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[15] is AUDIO_DAC:u11|FLASH_Out_Tmp[15] Q1_FLASH_Out_Tmp[15] = DFFEAS(W1L30, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[12] is AUDIO_DAC:u11|FLASH_Out_Tmp[12] Q1_FLASH_Out_Tmp[12] = DFFEAS(W1L27, Q1_LRCK_4X, B1_oRESET, , Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[1] is AUDIO_DAC:u11|FLASH_Out_Tmp[1] Q1_FLASH_Out_Tmp[1] = DFFEAS(W1L24, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[2] is AUDIO_DAC:u11|FLASH_Out_Tmp[2] Q1_FLASH_Out_Tmp[2] = DFFEAS(W1L25, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[3] is AUDIO_DAC:u11|FLASH_Out_Tmp[3] Q1_FLASH_Out_Tmp[3] = DFFEAS(W1L26, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1_FLASH_Out_Tmp[0] is AUDIO_DAC:u11|FLASH_Out_Tmp[0] Q1_FLASH_Out_Tmp[0] = DFFEAS(W1L23, Q1_LRCK_4X, B1_oRESET, , !Q1_FLASH_Cont[0], , , , ); --Q1L308 is AUDIO_DAC:u11|rom~2368 Q1L308 = Q1L239Q $ VCC; --Q1L309 is AUDIO_DAC:u11|rom~2369 Q1L309 = CARRY(Q1L239Q); --Q1L310 is AUDIO_DAC:u11|rom~2370 Q1L310 = Q1L240Q & !Q1L309 # !Q1L240Q & (Q1L309 # GND); --Q1L311 is AUDIO_DAC:u11|rom~2371 Q1L311 = CARRY(!Q1L309 # !Q1L240Q); --Q1L312 is AUDIO_DAC:u11|rom~2372 Q1L312 = Q1L241Q & (Q1L311 $ GND) # !Q1L241Q & !Q1L311 & VCC; --Q1L313 is AUDIO_DAC:u11|rom~2373 Q1L313 = CARRY(Q1L241Q & !Q1L311); --Q1L314 is AUDIO_DAC:u11|rom~2374 Q1L314 = Q1L242Q & !Q1L313 # !Q1L242Q & (Q1L313 # GND); --Q1L315 is AUDIO_DAC:u11|rom~2375 Q1L315 = CARRY(!Q1L313 # !Q1L242Q); --Q1L193 is AUDIO_DAC:u11|LessThan~867 Q1L193 = !Q1L241Q # !Q1L240Q # !Q1L239Q # !Q1L242Q; --Q1L194 is AUDIO_DAC:u11|LessThan~868 Q1L194 = Q1L244Q & (Q1L243Q # !Q1L193); --Q1L316 is AUDIO_DAC:u11|rom~2376 Q1L316 = Q1L243Q & (Q1L315 $ GND) # !Q1L243Q & !Q1L315 & VCC; --Q1L317 is AUDIO_DAC:u11|rom~2377 Q1L317 = CARRY(Q1L243Q & !Q1L315); --Q1L318 is AUDIO_DAC:u11|rom~2378 Q1L318 = Q1L244Q $ Q1L317; --F1_oRxD_Ready is USB_JTAG:u1|oRxD_Ready F1_oRxD_Ready = DFFEAS(F1L4, CLOCK_50, KEY[0], , , , , , ); --K1L192 is CMD_Decode:u5|f_VGA~53 K1L192 = K1_CMD_Tmp[40] & K1_CMD_Tmp[47] & F1_oRxD_Ready & !K1_CMD_Tmp[43]; --K1L180 is CMD_Decode:u5|f_SEG7~23 K1L180 = K1_CMD_Tmp[45] & K1L192 & !K1_CMD_Tmp[44] & !K1_CMD_Tmp[41]; --K1L189 is CMD_Decode:u5|f_SR_SEL~22 K1L189 = K1_CMD_Tmp[46] & !K1_CMD_Tmp[42]; --F1_oRxD_DATA[7] is USB_JTAG:u1|oRxD_DATA[7] F1_oRxD_DATA[7] = DFFEAS(U1_oRxD_DATA[7], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[3] is USB_JTAG:u1|oRxD_DATA[3] F1_oRxD_DATA[3] = DFFEAS(U1_oRxD_DATA[3], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[4] is USB_JTAG:u1|oRxD_DATA[4] F1_oRxD_DATA[4] = DFFEAS(U1_oRxD_DATA[4], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[0] is USB_JTAG:u1|oRxD_DATA[0] F1_oRxD_DATA[0] = DFFEAS(U1_oRxD_DATA[0], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[6] is USB_JTAG:u1|oRxD_DATA[6] F1_oRxD_DATA[6] = DFFEAS(U1_oRxD_DATA[6], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[2] is USB_JTAG:u1|oRxD_DATA[2] F1_oRxD_DATA[2] = DFFEAS(U1_oRxD_DATA[2], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[5] is USB_JTAG:u1|oRxD_DATA[5] F1_oRxD_DATA[5] = DFFEAS(U1_oRxD_DATA[5], CLOCK_50, , , F1L15, , , , ); --F1_oRxD_DATA[1] is USB_JTAG:u1|oRxD_DATA[1] F1_oRxD_DATA[1] = DFFEAS(U1_oRxD_DATA[1], CLOCK_50, , , F1L15, , , , ); --K1L193 is CMD_Decode:u5|f_VGA~54 K1L193 = K1_CMD_Tmp[47] & F1_oRxD_Ready & !K1_CMD_Tmp[43]; --K1L165 is CMD_Decode:u5|f_LED~32 K1L165 = K1L138 & K1_CMD_Tmp[45] & K1L193 & !K1_CMD_Tmp[41]; --BB1_SADDR[0] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[0] BB1_SADDR[0] = DFFEAS(Y1L13, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[8] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[8] BB1_SADDR[8] = DFFEAS(Y1L21, S1__clk0, KEY[0], , , , , , ); --AB1_do_writea is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_writea AB1_do_writea = DFFEAS(AB1L91, S1__clk0, KEY[0], , , , , , ); --AB1_do_reada is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_reada AB1_do_reada = DFFEAS(AB1L86, S1__clk0, KEY[0], , , , , , ); --AB1L61 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always4~0 AB1L61 = AB1_do_writea # AB1_do_reada; --AB1L22 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[0]~341 AB1L22 = AB1L61 & (BB1_SADDR[8]) # !AB1L61 & BB1_SADDR[0]; --AB1_do_load_mode is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_load_mode AB1_do_load_mode = DFFEAS(AB1L57, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1L43 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~784 AB1L43 = AB1_do_load_mode # !KEY[0]; --Z1L110 is Multi_Sdram:u3|Sdram_Controller:u1|add~736 Z1L110 = Z1_ST[0] $ VCC; --Z1L111 is Multi_Sdram:u3|Sdram_Controller:u1|add~737 Z1L111 = CARRY(Z1_ST[0]); --Z1L112 is Multi_Sdram:u3|Sdram_Controller:u1|add~738 Z1L112 = Z1_ST[1] & !Z1L111 # !Z1_ST[1] & (Z1L111 # GND); --Z1L113 is Multi_Sdram:u3|Sdram_Controller:u1|add~739 Z1L113 = CARRY(!Z1L111 # !Z1_ST[1]); --Z1L114 is Multi_Sdram:u3|Sdram_Controller:u1|add~740 Z1L114 = Z1_ST[2] & (Z1L113 $ GND) # !Z1_ST[2] & !Z1L113 & VCC; --Z1L115 is Multi_Sdram:u3|Sdram_Controller:u1|add~741 Z1L115 = CARRY(Z1_ST[2] & !Z1L113); --Z1L116 is Multi_Sdram:u3|Sdram_Controller:u1|add~742 Z1L116 = Z1_ST[3] & !Z1L115 # !Z1_ST[3] & (Z1L115 # GND); --Z1L117 is Multi_Sdram:u3|Sdram_Controller:u1|add~743 Z1L117 = CARRY(!Z1L115 # !Z1_ST[3]); --Z1L118 is Multi_Sdram:u3|Sdram_Controller:u1|add~744 Z1L118 = Z1_ST[4] & (Z1L117 $ GND) # !Z1_ST[4] & !Z1L117 & VCC; --Z1L119 is Multi_Sdram:u3|Sdram_Controller:u1|add~745 Z1L119 = CARRY(Z1_ST[4] & !Z1L117); --Z1L120 is Multi_Sdram:u3|Sdram_Controller:u1|add~746 Z1L120 = Z1_ST[5] & !Z1L119 # !Z1_ST[5] & (Z1L119 # GND); --Z1L121 is Multi_Sdram:u3|Sdram_Controller:u1|add~747 Z1L121 = CARRY(!Z1L119 # !Z1_ST[5]); --Z1L122 is Multi_Sdram:u3|Sdram_Controller:u1|add~748 Z1L122 = Z1_ST[6] & (Z1L121 $ GND) # !Z1_ST[6] & !Z1L121 & VCC; --Z1L123 is Multi_Sdram:u3|Sdram_Controller:u1|add~749 Z1L123 = CARRY(Z1_ST[6] & !Z1L121); --Z1L124 is Multi_Sdram:u3|Sdram_Controller:u1|add~750 Z1L124 = Z1_ST[7] & !Z1L123 # !Z1_ST[7] & (Z1L123 # GND); --Z1L125 is Multi_Sdram:u3|Sdram_Controller:u1|add~751 Z1L125 = CARRY(!Z1L123 # !Z1_ST[7]); --Z1L126 is Multi_Sdram:u3|Sdram_Controller:u1|add~752 Z1L126 = Z1_ST[8] $ !Z1L125; --Z1L36 is Multi_Sdram:u3|Sdram_Controller:u1|Decoder~1172 Z1L36 = Z1L38 & !Z1_ST[3] & !Z1_ST[2]; --Z1L41 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~496 Z1L41 = Z1L38 & Z1_ST[3] & !Z1_ST[1] & !Z1_ST[2]; --Z1L97 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1527 Z1L97 = Z1_ST[1] & (!Z1L41 # !Z1_ST[0]) # !Z1_ST[1] & !Z1L36 & (!Z1L41 # !Z1_ST[0]); --K1_mSDR_Start is CMD_Decode:u5|mSDR_Start K1_mSDR_Start = DFFEAS(K1L119, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --Z1_Pre_WR is Multi_Sdram:u3|Sdram_Controller:u1|Pre_WR Z1_Pre_WR = DFFEAS(Y1L52, S1__clk0, KEY[0], , , , , , ); --K1_oSDR_Select[1] is CMD_Decode:u5|oSDR_Select[1] K1_oSDR_Select[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, KEY[0], , K1L393, , , , ); --K1_oSDR_Select[0] is CMD_Decode:u5|oSDR_Select[0] K1_oSDR_Select[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, KEY[0], , K1L393, , , , ); --Y1L1 is Multi_Sdram:u3|Sdram_Multiplexer:u0|Equal~87 Y1L1 = K1_oSDR_Select[1] # K1_oSDR_Select[0]; --Z1L98 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1528 Z1L98 = K1_mSDR_WRn & K1_mSDR_Start & !Z1_Pre_WR & !Y1L1; --Y1_mSDR_RD is Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD Y1_mSDR_RD = DFFEAS(Y1L12, CLOCK_50, KEY[0], , , , , , ); --Y1L51 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~53 Y1L51 = Y1L1 & Y1_mSDR_RD # !Y1L1 & (K1_mSDR_Start & !K1_mSDR_WRn); --Z1_Pre_RD is Multi_Sdram:u3|Sdram_Controller:u1|Pre_RD Z1_Pre_RD = DFFEAS(Y1L51, S1__clk0, KEY[0], , , , , , ); --Z1L42 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~497 Z1L42 = Y1L51 & !Z1_Pre_RD; --BB1_CMD_ACK is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|CMD_ACK BB1_CMD_ACK = DFFEAS(BB1L58, S1__clk0, KEY[0], , , , , , ); --Z1L99 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1529 Z1L99 = Z1_ST[0] & (!BB1_CMD_ACK) # !Z1_ST[0] & !Z1L98 & !Z1L42; --Z1L100 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1530 Z1L100 = Z1L36 & Z1L99 & !Z1_ST[1]; --Z1L101 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1531 Z1L101 = Z1L126 & Z1L97 & !Z1L100; --Z1L95 is Multi_Sdram:u3|Sdram_Controller:u1|ST[7]~1532 Z1L95 = Z1L97 & Z1L124 & !Z1L100; --Z1L89 is Multi_Sdram:u3|Sdram_Controller:u1|ST[4]~1533 Z1L89 = Z1L97 & Z1L118 & !Z1L100; --Z1L93 is Multi_Sdram:u3|Sdram_Controller:u1|ST[6]~1534 Z1L93 = Z1L97 & Z1L122 & !Z1L100; --Z1L91 is Multi_Sdram:u3|Sdram_Controller:u1|ST[5]~1535 Z1L91 = Z1L97 & Z1L120 & !Z1L100; --Z1L128 is Multi_Sdram:u3|Sdram_Controller:u1|add~754 Z1L128 = Z1L97 & Z1L112 # !Z1L97 & (Z1_ST[0] & !Z1L41); --Z1L81 is Multi_Sdram:u3|Sdram_Controller:u1|ST[0]~969 Z1L81 = Z1L97 & Z1L110 # !Z1L97 & (!Z1_ST[0]); --Z1L85 is Multi_Sdram:u3|Sdram_Controller:u1|ST[2]~1536 Z1L85 = Z1L97 & Z1L114 & !Z1L100; --Z1L87 is Multi_Sdram:u3|Sdram_Controller:u1|ST[3]~1537 Z1L87 = Z1L97 & Z1L116 & !Z1L100; --BB1_SADDR[1] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[1] BB1_SADDR[1] = DFFEAS(Y1L14, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[9] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[9] BB1_SADDR[9] = DFFEAS(Y1L22, S1__clk0, KEY[0], , , , , , ); --AB1L25 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1]~342 AB1L25 = AB1L61 & (BB1_SADDR[9]) # !AB1L61 & BB1_SADDR[1]; --BB1_SADDR[2] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[2] BB1_SADDR[2] = DFFEAS(Y1L15, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[10] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[10] BB1_SADDR[10] = DFFEAS(Y1L23, S1__clk0, KEY[0], , , , , , ); --AB1L28 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[2]~343 AB1L28 = AB1L61 & (BB1_SADDR[10]) # !AB1L61 & BB1_SADDR[2]; --BB1_SADDR[11] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[11] BB1_SADDR[11] = DFFEAS(Y1L24, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[3] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[3] BB1_SADDR[3] = DFFEAS(Y1L16, S1__clk0, KEY[0], , , , , , ); --AB1L44 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~785 AB1L44 = !AB1L43 & (AB1L61 & BB1_SADDR[11] # !AB1L61 & (BB1_SADDR[3])); --BB1_SADDR[4] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[4] BB1_SADDR[4] = DFFEAS(Y1L17, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[12] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[12] BB1_SADDR[12] = DFFEAS(Y1L25, S1__clk0, KEY[0], , , , , , ); --AB1L32 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[4]~344 AB1L32 = AB1L61 & (BB1_SADDR[12]) # !AB1L61 & BB1_SADDR[4]; --BB1_SADDR[5] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[5] BB1_SADDR[5] = DFFEAS(Y1L18, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[13] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[13] BB1_SADDR[13] = DFFEAS(Y1L26, S1__clk0, KEY[0], , , , , , ); --AB1L35 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[5]~345 AB1L35 = AB1L61 & (BB1_SADDR[13]) # !AB1L61 & BB1_SADDR[5]; --BB1_SADDR[14] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[14] BB1_SADDR[14] = DFFEAS(Y1L27, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[6] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[6] BB1_SADDR[6] = DFFEAS(Y1L19, S1__clk0, KEY[0], , , , , , ); --AB1L45 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~786 AB1L45 = !AB1L43 & (AB1L61 & BB1_SADDR[14] # !AB1L61 & (BB1_SADDR[6])); --BB1_SADDR[15] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[15] BB1_SADDR[15] = DFFEAS(Y1L28, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[7] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[7] BB1_SADDR[7] = DFFEAS(Y1L20, S1__clk0, KEY[0], , , , , , ); --AB1L46 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~787 AB1L46 = !AB1L43 & (AB1L61 & BB1_SADDR[15] # !AB1L61 & (BB1_SADDR[7])); --BB1_SADDR[16] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[16] BB1_SADDR[16] = DFFEAS(Y1L29, S1__clk0, KEY[0], , , , , , ); --BB1_SADDR[17] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[17] BB1_SADDR[17] = DFFEAS(Y1L30, S1__clk0, KEY[0], , , , , , ); --AB1_do_precharge is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_precharge AB1_do_precharge = DFFEAS(AB1L58, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1L115 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag~35 AB1L115 = !AB1_do_load_mode & !AB1_do_precharge; --BB1_SADDR[18] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[18] BB1_SADDR[18] = DFFEAS(Y1L31, S1__clk0, KEY[0], , , , , , ); --AB1_do_rw is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_rw AB1_do_rw = DFFEAS(AB1L89, S1__clk0, KEY[0], , , , , , ); --AB1L47 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~788 AB1L47 = AB1L61 & AB1L115 & BB1_SADDR[18] & !AB1_do_rw; --BB1_SADDR[19] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[19] BB1_SADDR[19] = DFFEAS(Y1L32, S1__clk0, KEY[0], , , , , , ); --Z1L107 is Multi_Sdram:u3|Sdram_Controller:u1|Write~351 Z1L107 = Z1_Write & (Z1L109 & !Z1L42 # !Z1L53) # !Z1_Write & Z1L109 & (!Z1L42); --Z1L108 is Multi_Sdram:u3|Sdram_Controller:u1|Write~352 Z1L108 = Z1L107 $ (Z1L40 & Z1L36 & Z1_Write); --Z1L43 is Multi_Sdram:u3|Sdram_Controller:u1|Equal~498 Z1L43 = Z1_ST[0] & Z1L41; --Z1L52 is Multi_Sdram:u3|Sdram_Controller:u1|Read~349 Z1L52 = Z1_Read & (Z1L43 $ (Z1L53 # !Z1L109)) # !Z1_Read & (Z1L53); --AB1_do_refresh is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_refresh AB1_do_refresh = DFFEAS(AB1L59, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1_rw_flag is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag AB1_rw_flag = DFFEAS(AB1L117, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1L52 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|WE_N~73 AB1L52 = AB1_do_rw & !AB1_do_writea & !AB1_do_reada; --AB1L53 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|WE_N~74 AB1L53 = AB1_do_refresh # AB1L115 & (AB1_rw_flag # !AB1L52); --AB1L7 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CAS_N~114 AB1L7 = !AB1_do_refresh & (AB1_do_precharge # !AB1_do_load_mode & !AB1L52); --AB1_oe4 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|oe4 AB1_oe4 = DFFEAS(AB1L100, S1__clk0, , , KEY[0], , , , ); --AB1L15 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|RAS_N~164 AB1L15 = AB1_do_precharge & (AB1_rw_flag # AB1_oe4); --AB1L16 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|RAS_N~165 AB1L16 = !AB1_do_refresh & (AB1L15 # AB1L115 & !AB1L61); --BB1_SADDR[20] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[20] BB1_SADDR[20] = DFFEAS(Y1L33, S1__clk0, KEY[0], , , , , , ); --AB1L4 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA~43 AB1L4 = KEY[0] & BB1_SADDR[20] & !AB1_do_load_mode & !AB1_do_precharge; --BB1_SADDR[21] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[21] BB1_SADDR[21] = DFFEAS(Y1L34, S1__clk0, KEY[0], , , , , , ); --AB1L5 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA~44 AB1L5 = KEY[0] & BB1_SADDR[21] & !AB1_do_load_mode & !AB1_do_precharge; --Q1_LRCK_4X is AUDIO_DAC:u11|LRCK_4X Q1_LRCK_4X = DFFEAS(Q1L189, S2__clk1, B1_oRESET, , , , , , ); --Q1L10 is AUDIO_DAC:u11|FLASH_Cont[0]~426 Q1L10 = Q1_FLASH_Cont[0] $ VCC; --Q1L11 is AUDIO_DAC:u11|FLASH_Cont[0]~427 Q1L11 = CARRY(Q1_FLASH_Cont[0]); --Q1L195 is AUDIO_DAC:u11|LessThan~869 Q1L195 = !Q1_FLASH_Cont[3] # !Q1_FLASH_Cont[2] # !Q1_FLASH_Cont[1] # !Q1_FLASH_Cont[0]; --Q1L196 is AUDIO_DAC:u11|LessThan~870 Q1L196 = !Q1_FLASH_Cont[7] # !Q1_FLASH_Cont[6] # !Q1_FLASH_Cont[5] # !Q1_FLASH_Cont[4]; --Q1L197 is AUDIO_DAC:u11|LessThan~871 Q1L197 = !Q1_FLASH_Cont[11] # !Q1_FLASH_Cont[10] # !Q1_FLASH_Cont[9] # !Q1_FLASH_Cont[8]; --Q1L198 is AUDIO_DAC:u11|LessThan~872 Q1L198 = !Q1_FLASH_Cont[15] # !Q1_FLASH_Cont[14] # !Q1_FLASH_Cont[13] # !Q1_FLASH_Cont[12]; --Q1L199 is AUDIO_DAC:u11|LessThan~873 Q1L199 = Q1L195 # Q1L196 # Q1L197 # Q1L198; --Q1L200 is AUDIO_DAC:u11|LessThan~874 Q1L200 = !Q1_FLASH_Cont[19] # !Q1_FLASH_Cont[18] # !Q1_FLASH_Cont[17] # !Q1_FLASH_Cont[16]; --Q1L201 is AUDIO_DAC:u11|LessThan~875 Q1L201 = !Q1L199 & !Q1L200 & Q1_FLASH_Cont[20] & Q1_FLASH_Cont[21]; --K1_f_FLASH is CMD_Decode:u5|f_FLASH K1_f_FLASH = DFFEAS(K1L160, CLOCK_50, KEY[0], , , , , , ); --K1L152 is CMD_Decode:u5|always7~141 K1L152 = K1_CMD_Tmp[16] & K1_CMD_Tmp[17] & K1_CMD_Tmp[48] & !K1_CMD_Tmp[52]; --K1L153 is CMD_Decode:u5|always7~142 K1L153 = K1_CMD_Tmp[18] & K1_CMD_Tmp[19] & K1_CMD_Tmp[20] & K1_CMD_Tmp[21]; --K1L154 is CMD_Decode:u5|always7~143 K1L154 = K1_CMD_Tmp[22] & K1_CMD_Tmp[23] & K1_CMD_Tmp[54] & !K1_CMD_Tmp[53]; --K1L155 is CMD_Decode:u5|always7~144 K1L155 = K1_CMD_Tmp[49] & K1L154 & !K1_CMD_Tmp[50]; --K1L150 is CMD_Decode:u5|always7~2 K1L150 = K1L151 & K1L152 & K1L153 & K1L155; --K1_mFL_ST.000 is CMD_Decode:u5|mFL_ST.000 K1_mFL_ST.000 = DFFEAS(K1L122, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1L264 is CMD_Decode:u5|oFL_ADDR[0]~43 K1L264 = KEY[0] & K1_f_FLASH & K1L150 & !K1_mFL_ST.000; --K1_f_FL_SEL is CMD_Decode:u5|f_FL_SEL K1_f_FL_SEL = DFFEAS(K1L163, CLOCK_50, KEY[0], , , , , , ); --K1L301 is CMD_Decode:u5|oFL_Select[1]~2 K1L301 = K1L148 & K1_f_FL_SEL; --W1_ST.10 is Multi_Flash:u2|Flash_Multiplexer:u0|ST.10 W1_ST.10 = DFFEAS(W1L10, CLOCK_50, KEY[0], , , , , , ); --W1_ST.11 is Multi_Flash:u2|Flash_Multiplexer:u0|ST.11 W1_ST.11 = DFFEAS(W1L7, CLOCK_50, KEY[0], , , , , , ); --W1_ST.01 is Multi_Flash:u2|Flash_Multiplexer:u0|ST.01 W1_ST.01 = DFFEAS(W1L8, CLOCK_50, KEY[0], , , , , , ); --W1L21 is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_Start~146 W1L21 = !W1_ST.10 & !W1_ST.11 & !W1_ST.01; --X1_mFinish is Multi_Flash:u2|Flash_Controller:u1|mFinish X1_mFinish = DFFEAS(X1L203, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --W1L6 is Multi_Flash:u2|Flash_Multiplexer:u0|ST~164 W1L6 = W1_ST.01 & X1_mFinish & !X1_mStart; --W1L22 is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_Start~147 W1L22 = W1L1 & (W1L21 # W1_mFL_Start & !W1L6); --K1_mFL_ST.101 is CMD_Decode:u5|mFL_ST.101 K1_mFL_ST.101 = DFFEAS(K1L123, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1_mFL_ST.011 is CMD_Decode:u5|mFL_ST.011 K1_mFL_ST.011 = DFFEAS(K1L124, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1_mFL_ST.001 is CMD_Decode:u5|mFL_ST.001 K1_mFL_ST.001 = DFFEAS(K1L125, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1L84 is CMD_Decode:u5|Select~2909 K1L84 = !K1_mFL_ST.101 & !K1_mFL_ST.011 & !K1_mFL_ST.001; --K1_mFL_ST.110 is CMD_Decode:u5|mFL_ST.110 K1_mFL_ST.110 = DFFEAS(K1L126, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1_mFL_ST.111 is CMD_Decode:u5|mFL_ST.111 K1_mFL_ST.111 = DFFEAS(K1L127, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1L85 is CMD_Decode:u5|Select~2910 K1L85 = !K1_mFL_ST.110 & !K1_mFL_ST.111 & (K1_mFL_ST.000 # K1L150); --W1L72 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_Ready~14 W1L72 = K1_oFL_Select[0] # K1_oFL_Select[1] # X1_mFinish & !X1_mStart; --K1L86 is CMD_Decode:u5|Select~2911 K1L86 = K1L84 & (K1_oFL_Start # K1L85) # !K1L84 & K1_oFL_Start & (!W1L72); --W1L63 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_Start~40 W1L63 = K1_oFL_Select[0] & W1_mFL_Start # !K1_oFL_Select[0] & (K1_oFL_Select[1] & W1_mFL_Start # !K1_oFL_Select[1] & (K1_oFL_Start)); --X1_Start_Delay[3] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[3] X1_Start_Delay[3] = DFFEAS(X1L162, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[4] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[4] X1_Start_Delay[4] = DFFEAS(X1L165, CLOCK_50, KEY[0], , , , , X1L83, ); --X1L109 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1955 X1L109 = X1_Start_Delay[3] # X1_Start_Delay[4]; --X1_Start_Delay[5] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[5] X1_Start_Delay[5] = DFFEAS(X1L168, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[6] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[6] X1_Start_Delay[6] = DFFEAS(X1L171, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[7] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[7] X1_Start_Delay[7] = DFFEAS(X1L174, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[8] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[8] X1_Start_Delay[8] = DFFEAS(X1L177, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[9] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[9] X1_Start_Delay[9] = DFFEAS(X1L180, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[10] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[10] X1_Start_Delay[10] = DFFEAS(X1L183, CLOCK_50, KEY[0], , , , , X1L83, ); --X1L110 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1956 X1L110 = X1_Start_Delay[7] # X1_Start_Delay[8] # X1_Start_Delay[9] # X1_Start_Delay[10]; --X1L111 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1957 X1L111 = X1L109 # X1_Start_Delay[5] # X1_Start_Delay[6] # X1L110; --X1L205 is Multi_Flash:u2|Flash_Controller:u1|mStart~44 X1L205 = X1L83 # X1_mStart & !X1L111; --X1_mCLK is Multi_Flash:u2|Flash_Controller:u1|mCLK X1_mCLK = DFFEAS(X1_Cont_DIV[2], CLOCK_50, KEY[0], , , , , , ); --X1_WE_CLK_Delay[1] is Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[1] X1_WE_CLK_Delay[1] = DFFEAS(X1_mCLK, CLOCK_50, KEY[0], , , , , , ); --X1L84 is Multi_Flash:u2|Flash_Controller:u1|Equal~60 X1L84 = X1_mCLK & !X1_WE_CLK_Delay[1]; --K1_oFL_CMD[0] is CMD_Decode:u5|oFL_CMD[0] K1_oFL_CMD[0] = DFFEAS(K1L75, CLOCK_50, , , KEY[0], , , , ); --W1L53 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_CMD[0]~27 W1L53 = K1_oFL_CMD[0] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --K1_oFL_CMD[2] is CMD_Decode:u5|oFL_CMD[2] K1_oFL_CMD[2] = DFFEAS(K1L80, CLOCK_50, , , KEY[0], , , , ); --W1L54 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_CMD[2]~28 W1L54 = K1_oFL_CMD[2] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Q1L13 is AUDIO_DAC:u11|FLASH_Cont[1]~428 Q1L13 = Q1_FLASH_Cont[1] & !Q1L11 # !Q1_FLASH_Cont[1] & (Q1L11 # GND); --Q1L14 is AUDIO_DAC:u11|FLASH_Cont[1]~429 Q1L14 = CARRY(!Q1L11 # !Q1_FLASH_Cont[1]); --Q1L16 is AUDIO_DAC:u11|FLASH_Cont[2]~430 Q1L16 = Q1_FLASH_Cont[2] & (Q1L14 $ GND) # !Q1_FLASH_Cont[2] & !Q1L14 & VCC; --Q1L17 is AUDIO_DAC:u11|FLASH_Cont[2]~431 Q1L17 = CARRY(Q1_FLASH_Cont[2] & !Q1L14); --Q1L19 is AUDIO_DAC:u11|FLASH_Cont[3]~432 Q1L19 = Q1_FLASH_Cont[3] & !Q1L17 # !Q1_FLASH_Cont[3] & (Q1L17 # GND); --Q1L20 is AUDIO_DAC:u11|FLASH_Cont[3]~433 Q1L20 = CARRY(!Q1L17 # !Q1_FLASH_Cont[3]); --Q1L22 is AUDIO_DAC:u11|FLASH_Cont[4]~434 Q1L22 = Q1_FLASH_Cont[4] & (Q1L20 $ GND) # !Q1_FLASH_Cont[4] & !Q1L20 & VCC; --Q1L23 is AUDIO_DAC:u11|FLASH_Cont[4]~435 Q1L23 = CARRY(Q1_FLASH_Cont[4] & !Q1L20); --Q1L25 is AUDIO_DAC:u11|FLASH_Cont[5]~436 Q1L25 = Q1_FLASH_Cont[5] & !Q1L23 # !Q1_FLASH_Cont[5] & (Q1L23 # GND); --Q1L26 is AUDIO_DAC:u11|FLASH_Cont[5]~437 Q1L26 = CARRY(!Q1L23 # !Q1_FLASH_Cont[5]); --Q1L28 is AUDIO_DAC:u11|FLASH_Cont[6]~438 Q1L28 = Q1_FLASH_Cont[6] & (Q1L26 $ GND) # !Q1_FLASH_Cont[6] & !Q1L26 & VCC; --Q1L29 is AUDIO_DAC:u11|FLASH_Cont[6]~439 Q1L29 = CARRY(Q1_FLASH_Cont[6] & !Q1L26); --Q1L31 is AUDIO_DAC:u11|FLASH_Cont[7]~440 Q1L31 = Q1_FLASH_Cont[7] & !Q1L29 # !Q1_FLASH_Cont[7] & (Q1L29 # GND); --Q1L32 is AUDIO_DAC:u11|FLASH_Cont[7]~441 Q1L32 = CARRY(!Q1L29 # !Q1_FLASH_Cont[7]); --Q1L34 is AUDIO_DAC:u11|FLASH_Cont[8]~442 Q1L34 = Q1_FLASH_Cont[8] & (Q1L32 $ GND) # !Q1_FLASH_Cont[8] & !Q1L32 & VCC; --Q1L35 is AUDIO_DAC:u11|FLASH_Cont[8]~443 Q1L35 = CARRY(Q1_FLASH_Cont[8] & !Q1L32); --Q1L37 is AUDIO_DAC:u11|FLASH_Cont[9]~444 Q1L37 = Q1_FLASH_Cont[9] & !Q1L35 # !Q1_FLASH_Cont[9] & (Q1L35 # GND); --Q1L38 is AUDIO_DAC:u11|FLASH_Cont[9]~445 Q1L38 = CARRY(!Q1L35 # !Q1_FLASH_Cont[9]); --Q1L40 is AUDIO_DAC:u11|FLASH_Cont[10]~446 Q1L40 = Q1_FLASH_Cont[10] & (Q1L38 $ GND) # !Q1_FLASH_Cont[10] & !Q1L38 & VCC; --Q1L41 is AUDIO_DAC:u11|FLASH_Cont[10]~447 Q1L41 = CARRY(Q1_FLASH_Cont[10] & !Q1L38); --Q1L43 is AUDIO_DAC:u11|FLASH_Cont[11]~448 Q1L43 = Q1_FLASH_Cont[11] & !Q1L41 # !Q1_FLASH_Cont[11] & (Q1L41 # GND); --Q1L44 is AUDIO_DAC:u11|FLASH_Cont[11]~449 Q1L44 = CARRY(!Q1L41 # !Q1_FLASH_Cont[11]); --Q1L46 is AUDIO_DAC:u11|FLASH_Cont[12]~450 Q1L46 = Q1_FLASH_Cont[12] & (Q1L44 $ GND) # !Q1_FLASH_Cont[12] & !Q1L44 & VCC; --Q1L47 is AUDIO_DAC:u11|FLASH_Cont[12]~451 Q1L47 = CARRY(Q1_FLASH_Cont[12] & !Q1L44); --Q1L49 is AUDIO_DAC:u11|FLASH_Cont[13]~452 Q1L49 = Q1_FLASH_Cont[13] & !Q1L47 # !Q1_FLASH_Cont[13] & (Q1L47 # GND); --Q1L50 is AUDIO_DAC:u11|FLASH_Cont[13]~453 Q1L50 = CARRY(!Q1L47 # !Q1_FLASH_Cont[13]); --Q1L52 is AUDIO_DAC:u11|FLASH_Cont[14]~454 Q1L52 = Q1_FLASH_Cont[14] & (Q1L50 $ GND) # !Q1_FLASH_Cont[14] & !Q1L50 & VCC; --Q1L53 is AUDIO_DAC:u11|FLASH_Cont[14]~455 Q1L53 = CARRY(Q1_FLASH_Cont[14] & !Q1L50); --Q1L55 is AUDIO_DAC:u11|FLASH_Cont[15]~456 Q1L55 = Q1_FLASH_Cont[15] & !Q1L53 # !Q1_FLASH_Cont[15] & (Q1L53 # GND); --Q1L56 is AUDIO_DAC:u11|FLASH_Cont[15]~457 Q1L56 = CARRY(!Q1L53 # !Q1_FLASH_Cont[15]); --Q1L58 is AUDIO_DAC:u11|FLASH_Cont[16]~458 Q1L58 = Q1_FLASH_Cont[16] & (Q1L56 $ GND) # !Q1_FLASH_Cont[16] & !Q1L56 & VCC; --Q1L59 is AUDIO_DAC:u11|FLASH_Cont[16]~459 Q1L59 = CARRY(Q1_FLASH_Cont[16] & !Q1L56); --Q1L61 is AUDIO_DAC:u11|FLASH_Cont[17]~460 Q1L61 = Q1_FLASH_Cont[17] & !Q1L59 # !Q1_FLASH_Cont[17] & (Q1L59 # GND); --Q1L62 is AUDIO_DAC:u11|FLASH_Cont[17]~461 Q1L62 = CARRY(!Q1L59 # !Q1_FLASH_Cont[17]); --Q1L64 is AUDIO_DAC:u11|FLASH_Cont[18]~462 Q1L64 = Q1_FLASH_Cont[18] & (Q1L62 $ GND) # !Q1_FLASH_Cont[18] & !Q1L62 & VCC; --Q1L65 is AUDIO_DAC:u11|FLASH_Cont[18]~463 Q1L65 = CARRY(Q1_FLASH_Cont[18] & !Q1L62); --Q1L67 is AUDIO_DAC:u11|FLASH_Cont[19]~464 Q1L67 = Q1_FLASH_Cont[19] & !Q1L65 # !Q1_FLASH_Cont[19] & (Q1L65 # GND); --Q1L68 is AUDIO_DAC:u11|FLASH_Cont[19]~465 Q1L68 = CARRY(!Q1L65 # !Q1_FLASH_Cont[19]); --Q1L70 is AUDIO_DAC:u11|FLASH_Cont[20]~466 Q1L70 = Q1_FLASH_Cont[20] & (Q1L68 $ GND) # !Q1_FLASH_Cont[20] & !Q1L68 & VCC; --Q1L71 is AUDIO_DAC:u11|FLASH_Cont[20]~467 Q1L71 = CARRY(Q1_FLASH_Cont[20] & !Q1L68); --Q1L73 is AUDIO_DAC:u11|FLASH_Cont[21]~468 Q1L73 = Q1_FLASH_Cont[21] $ Q1L71; --X1_WE_CLK_Delay[2] is Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[2] X1_WE_CLK_Delay[2] = DFFEAS(X1_WE_CLK_Delay[1], CLOCK_50, KEY[0], , , , , , ); --B1_Cont[0] is Reset_Delay:d0|Cont[0] B1_Cont[0] = DFFEAS(B1L3, CLOCK_50, , , B1L68, , , , ); --B1_Cont[1] is Reset_Delay:d0|Cont[1] B1_Cont[1] = DFFEAS(B1L6, CLOCK_50, , , B1L68, , , , ); --B1L62 is Reset_Delay:d0|Equal~192 B1L62 = B1_Cont[0] & B1_Cont[1]; --B1_Cont[2] is Reset_Delay:d0|Cont[2] B1_Cont[2] = DFFEAS(B1L9, CLOCK_50, , , B1L68, , , , ); --B1_Cont[3] is Reset_Delay:d0|Cont[3] B1_Cont[3] = DFFEAS(B1L12, CLOCK_50, , , B1L68, , , , ); --B1_Cont[4] is Reset_Delay:d0|Cont[4] B1_Cont[4] = DFFEAS(B1L15, CLOCK_50, , , B1L68, , , , ); --B1_Cont[5] is Reset_Delay:d0|Cont[5] B1_Cont[5] = DFFEAS(B1L18, CLOCK_50, , , B1L68, , , , ); --B1_Cont[6] is Reset_Delay:d0|Cont[6] B1_Cont[6] = DFFEAS(B1L21, CLOCK_50, , , B1L68, , , , ); --B1_Cont[7] is Reset_Delay:d0|Cont[7] B1_Cont[7] = DFFEAS(B1L24, CLOCK_50, , , B1L68, , , , ); --B1L63 is Reset_Delay:d0|Equal~193 B1L63 = B1_Cont[4] & B1_Cont[5] & B1_Cont[6] & B1_Cont[7]; --B1L64 is Reset_Delay:d0|Equal~194 B1L64 = B1L62 & B1_Cont[2] & B1_Cont[3] & B1L63; --B1_Cont[8] is Reset_Delay:d0|Cont[8] B1_Cont[8] = DFFEAS(B1L27, CLOCK_50, , , B1L68, , , , ); --B1_Cont[9] is Reset_Delay:d0|Cont[9] B1_Cont[9] = DFFEAS(B1L30, CLOCK_50, , , B1L68, , , , ); --B1_Cont[10] is Reset_Delay:d0|Cont[10] B1_Cont[10] = DFFEAS(B1L33, CLOCK_50, , , B1L68, , , , ); --B1_Cont[11] is Reset_Delay:d0|Cont[11] B1_Cont[11] = DFFEAS(B1L36, CLOCK_50, , , B1L68, , , , ); --B1L65 is Reset_Delay:d0|Equal~195 B1L65 = B1_Cont[8] & B1_Cont[9] & B1_Cont[10] & B1_Cont[11]; --B1_Cont[12] is Reset_Delay:d0|Cont[12] B1_Cont[12] = DFFEAS(B1L39, CLOCK_50, , , B1L68, , , , ); --B1_Cont[13] is Reset_Delay:d0|Cont[13] B1_Cont[13] = DFFEAS(B1L42, CLOCK_50, , , B1L68, , , , ); --B1_Cont[14] is Reset_Delay:d0|Cont[14] B1_Cont[14] = DFFEAS(B1L45, CLOCK_50, , , B1L68, , , , ); --B1_Cont[15] is Reset_Delay:d0|Cont[15] B1_Cont[15] = DFFEAS(B1L48, CLOCK_50, , , B1L68, , , , ); --B1L66 is Reset_Delay:d0|Equal~196 B1L66 = B1_Cont[12] & B1_Cont[13] & B1_Cont[14] & B1_Cont[15]; --B1_Cont[16] is Reset_Delay:d0|Cont[16] B1_Cont[16] = DFFEAS(B1L51, CLOCK_50, , , B1L68, , , , ); --B1_Cont[17] is Reset_Delay:d0|Cont[17] B1_Cont[17] = DFFEAS(B1L54, CLOCK_50, , , B1L68, , , , ); --B1_Cont[18] is Reset_Delay:d0|Cont[18] B1_Cont[18] = DFFEAS(B1L57, CLOCK_50, , , B1L68, , , , ); --B1_Cont[19] is Reset_Delay:d0|Cont[19] B1_Cont[19] = DFFEAS(B1L60, CLOCK_50, , , B1L68, , , , ); --B1L67 is Reset_Delay:d0|Equal~197 B1L67 = B1_Cont[16] & B1_Cont[17] & B1_Cont[18] & B1_Cont[19]; --B1L68 is Reset_Delay:d0|Equal~198 B1L68 = !B1L67 # !B1L66 # !B1L65 # !B1L64; --K1L87 is CMD_Decode:u5|Select~2912 K1L87 = K1_mSDR_WRn & !K1_mSR_ST.001 & (!F1_oTxD_Done # !K1_mSR_ST.101) # !K1_mSDR_WRn & (!F1_oTxD_Done # !K1_mSR_ST.101); --K1L88 is CMD_Decode:u5|Select~2913 K1L88 = K1L87 & (K1_mSR_ST.000 # K1L158); --K1L175 is CMD_Decode:u5|f_SDR_SEL~53 K1L175 = K1_CMD_Tmp[42] & !K1_CMD_Tmp[46]; --K1L187 is CMD_Decode:u5|f_SRAM~91 K1L187 = K1_f_SRAM & K1L88 # !K1_f_SRAM & (K1L180 & K1L175); --K1L194 is CMD_Decode:u5|f_VGA~55 K1L194 = K1_CMD_Tmp[41] & !K1_CMD_Tmp[45]; --K1L176 is CMD_Decode:u5|f_SDR_SEL~54 K1L176 = K1_CMD_Tmp[43] & F1_oRxD_Ready & !K1_CMD_Tmp[47]; --K1L177 is CMD_Decode:u5|f_SDR_SEL~55 K1L177 = K1_CMD_Tmp[40] & K1_CMD_Tmp[44] & K1L194 & K1L176; --M1L396 is VGA_Controller:u8|oCoord_X[2]~1233 M1L396 = M1_H_Cont[2] $ VCC; --M1L397 is VGA_Controller:u8|oCoord_X[2]~1234 M1L397 = CARRY(M1_H_Cont[2]); --M1L399 is VGA_Controller:u8|oCoord_X[3]~1235 M1L399 = M1_H_Cont[3] & M1L397 & VCC # !M1_H_Cont[3] & !M1L397; --M1L400 is VGA_Controller:u8|oCoord_X[3]~1236 M1L400 = CARRY(!M1_H_Cont[3] & !M1L397); --M1L402 is VGA_Controller:u8|oCoord_X[4]~1237 M1L402 = M1_H_Cont[4] & (M1L400 $ GND) # !M1_H_Cont[4] & !M1L400 & VCC; --M1L403 is VGA_Controller:u8|oCoord_X[4]~1238 M1L403 = CARRY(M1_H_Cont[4] & !M1L400); --M1L405 is VGA_Controller:u8|oCoord_X[5]~1239 M1L405 = M1_H_Cont[5] & M1L403 & VCC # !M1_H_Cont[5] & !M1L403; --M1L406 is VGA_Controller:u8|oCoord_X[5]~1240 M1L406 = CARRY(!M1_H_Cont[5] & !M1L403); --M1L408 is VGA_Controller:u8|oCoord_X[6]~1241 M1L408 = M1_H_Cont[6] & (GND # !M1L406) # !M1_H_Cont[6] & (M1L406 $ GND); --M1L409 is VGA_Controller:u8|oCoord_X[6]~1242 M1L409 = CARRY(M1_H_Cont[6] # !M1L406); --M1L411 is VGA_Controller:u8|oCoord_X[7]~1243 M1L411 = M1_H_Cont[7] & !M1L409 # !M1_H_Cont[7] & (M1L409 # GND); --M1L412 is VGA_Controller:u8|oCoord_X[7]~1244 M1L412 = CARRY(!M1L409 # !M1_H_Cont[7]); --M1L422 is VGA_Controller:u8|oCoord_Y[1]~184 M1L422 = M1_V_Cont[1] $ VCC; --M1L423 is VGA_Controller:u8|oCoord_Y[1]~185 M1L423 = CARRY(M1_V_Cont[1]); --M1L414 is VGA_Controller:u8|oCoord_X[8]~1245 M1L414 = M1_H_Cont[8] & (GND # !M1L412) # !M1_H_Cont[8] & (M1L412 $ GND); --M1L415 is VGA_Controller:u8|oCoord_X[8]~1246 M1L415 = CARRY(M1_H_Cont[8] # !M1L412); --M1L425 is VGA_Controller:u8|oCoord_Y[2]~186 M1L425 = M1_V_Cont[2] & M1L423 & VCC # !M1_V_Cont[2] & !M1L423; --M1L426 is VGA_Controller:u8|oCoord_Y[2]~187 M1L426 = CARRY(!M1_V_Cont[2] & !M1L423); --M1L417 is VGA_Controller:u8|oCoord_X[9]~1247 M1L417 = M1_H_Cont[9] $ !M1L415; --M1L428 is VGA_Controller:u8|oCoord_Y[3]~188 M1L428 = M1_V_Cont[3] & (GND # !M1L426) # !M1_V_Cont[3] & (M1L426 $ GND); --M1L429 is VGA_Controller:u8|oCoord_Y[3]~189 M1L429 = CARRY(M1_V_Cont[3] # !M1L426); --M1L432 is VGA_Controller:u8|oCoord_Y[4]~190 M1L432 = M1_V_Cont[4] & M1L429 & VCC # !M1_V_Cont[4] & !M1L429; --M1L433 is VGA_Controller:u8|oCoord_Y[4]~191 M1L433 = CARRY(!M1_V_Cont[4] & !M1L429); --M1L435 is VGA_Controller:u8|oCoord_Y[5]~192 M1L435 = M1_V_Cont[5] & (M1L433 $ GND) # !M1_V_Cont[5] & !M1L433 & VCC; --M1L436 is VGA_Controller:u8|oCoord_Y[5]~193 M1L436 = CARRY(M1_V_Cont[5] & !M1L433); --M1L438 is VGA_Controller:u8|oCoord_Y[6]~194 M1L438 = M1_V_Cont[6] & M1L436 & VCC # !M1_V_Cont[6] & !M1L436; --M1L439 is VGA_Controller:u8|oCoord_Y[6]~195 M1L439 = CARRY(!M1_V_Cont[6] & !M1L436); --M1L441 is VGA_Controller:u8|oCoord_Y[7]~196 M1L441 = M1_V_Cont[7] & (GND # !M1L439) # !M1_V_Cont[7] & (M1L439 $ GND); --M1L442 is VGA_Controller:u8|oCoord_Y[7]~197 M1L442 = CARRY(M1_V_Cont[7] # !M1L439); --M1L444 is VGA_Controller:u8|oCoord_Y[8]~198 M1L444 = M1_V_Cont[8] & M1L442 & VCC # !M1_V_Cont[8] & !M1L442; --M1L445 is VGA_Controller:u8|oCoord_Y[8]~199 M1L445 = CARRY(!M1_V_Cont[8] & !M1L442); --M1L447 is VGA_Controller:u8|oCoord_Y[9]~200 M1L447 = M1_V_Cont[9] $ M1L445; --K1L89 is CMD_Decode:u5|Select~2914 K1L89 = F1_oTxD_Done & K1_mSR_ST.011; --K1L222 is CMD_Decode:u5|mSR_ST~167 K1L222 = K1_mSR_ST.100 # !F1_oTxD_Done & K1_mSR_ST.101; --V1_oTxD_Done is USB_JTAG:u1|JTAG_TRANS:u1|oTxD_Done V1_oTxD_Done = DFFEAS(V1L1, R1_wire_clkctrl1_outclk, !TCS, , , , , , ); --F1_Pre_TxD_Done is USB_JTAG:u1|Pre_TxD_Done F1_Pre_TxD_Done = DFFEAS(V1_oTxD_Done, CLOCK_50, KEY[0], , , , , , ); --F1L1 is USB_JTAG:u1|Equal~21 F1L1 = V1_oTxD_Done & !F1_Pre_TxD_Done; --K1L223 is CMD_Decode:u5|mSR_ST~168 K1L223 = K1_mSR_ST.010 # K1_mSR_ST.011 & !F1_oTxD_Done; --K1L90 is CMD_Decode:u5|Select~2915 K1L90 = K1_mSR_ST.001 & !K1_mSDR_WRn; --K1L91 is CMD_Decode:u5|Select~2916 K1L91 = K1_oFL_TXD_Start & (!K1_mFL_ST.111 # !F1_oTxD_Done) # !K1_oFL_TXD_Start & K1_mFL_ST.110 & (!K1_mFL_ST.111); --K1_mSDR_ST.000 is CMD_Decode:u5|mSDR_ST.000 K1_mSDR_ST.000 = DFFEAS(K1L129, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1_mSDR_ST.001 is CMD_Decode:u5|mSDR_ST.001 K1_mSDR_ST.001 = DFFEAS(K1L131, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1_mSDR_ST.101 is CMD_Decode:u5|mSDR_ST.101 K1_mSDR_ST.101 = DFFEAS(K1L115, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1L92 is CMD_Decode:u5|Select~2917 K1L92 = !K1_mSDR_ST.101 & (K1_oSDR_TXD_Start # K1_mSDR_ST.000 & !K1_mSDR_ST.001); --K1_mSDR_ST.011 is CMD_Decode:u5|mSDR_ST.011 K1_mSDR_ST.011 = DFFEAS(K1L132, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1L93 is CMD_Decode:u5|Select~2918 K1L93 = K1_oSDR_TXD_Start & (K1L92 & !K1_mSDR_ST.011 # !F1_oTxD_Done) # !K1_oSDR_TXD_Start & K1L92 & (!K1_mSDR_ST.011); --K1_f_SDRAM is CMD_Decode:u5|f_SDRAM K1_f_SDRAM = DFFEAS(K1L173, CLOCK_50, KEY[0], , , , , , ); --K1L94 is CMD_Decode:u5|Select~2919 K1L94 = !K1_mSR_ST.011 & (K1_oSR_TXD_Start # K1_mSR_ST.000 & !K1_mSR_ST.001); --K1L95 is CMD_Decode:u5|Select~2920 K1L95 = K1L94 & (K1_oSR_TXD_Start & !F1_oTxD_Done # !K1_mSR_ST.101) # !K1L94 & K1_oSR_TXD_Start & (!F1_oTxD_Done); --K1_f_PS2 is CMD_Decode:u5|f_PS2 K1_f_PS2 = DFFEAS(K1L171, CLOCK_50, KEY[0], , , , , , ); --K1_mPS2_ST.001 is CMD_Decode:u5|mPS2_ST.001 K1_mPS2_ST.001 = DFFEAS(K1L206, CLOCK_50, KEY[0], , , , , , ); --K1L348 is CMD_Decode:u5|oPS2_TXD_Start~60 K1L348 = K1_f_PS2 & (K1_oPS2_TXD_Start & !F1_oTxD_Done # !K1_mPS2_ST.001) # !K1_f_PS2 & K1_oPS2_TXD_Start; --K1L96 is CMD_Decode:u5|Select~2921 K1L96 = !K1_CMD_Tmp[9] & K1_CMD_Tmp[8]; --K1L505 is CMD_Decode:u5|sel_SR~141 K1L505 = K1_CMD_Tmp[9] & !K1_CMD_Tmp[10] & !K1_CMD_Tmp[13] & K1_CMD_Tmp[14] # !K1_CMD_Tmp[9] & K1_CMD_Tmp[10] & K1_CMD_Tmp[13] & !K1_CMD_Tmp[14]; --K1_f_SETUP is CMD_Decode:u5|f_SETUP K1_f_SETUP = DFFEAS(K1L185, CLOCK_50, KEY[0], , , , , , ); --K1L506 is CMD_Decode:u5|sel_SR~142 K1L506 = K1_CMD_Tmp[15] & !K1_CMD_Tmp[11] & (K1_CMD_Tmp[8] $ K1_CMD_Tmp[12]); --K1L507 is CMD_Decode:u5|sel_SR~143 K1L507 = K1L148 & K1L505 & K1_f_SETUP & K1L506; --K1L97 is CMD_Decode:u5|Select~2922 K1L97 = !K1_CMD_Tmp[8] & !K1_CMD_Tmp[9]; --K1L98 is CMD_Decode:u5|Select~2923 K1L98 = K1_CMD_Tmp[8] & K1_CMD_Tmp[9]; --X1_oDATA[5] is Multi_Flash:u2|Flash_Controller:u1|oDATA[5] X1_oDATA[5] = DFFEAS(A1L107, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L69 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[5]~104 W1L69 = X1_oDATA[5] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --K1L312 is CMD_Decode:u5|oFL_TXD_DATA[7]~0 K1L312 = KEY[0] & K1_f_FLASH & K1_mFL_ST.110; --Z1_DATAOUT[13] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[13] Z1_DATAOUT[13] = DFFEAS(Z1_mDATAOUT[13], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[5] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[5] Z1_DATAOUT[5] = DFFEAS(Z1_mDATAOUT[5], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1_mSDR_ST.100 is CMD_Decode:u5|mSDR_ST.100 K1_mSDR_ST.100 = DFFEAS(K1L133, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1L99 is CMD_Decode:u5|Select~2924 K1L99 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[13] # !K1_mSDR_ST.100 & (Z1_DATAOUT[5])); --K1_mSDR_ST.010 is CMD_Decode:u5|mSDR_ST.010 K1_mSDR_ST.010 = DFFEAS(K1L134, CLOCK_50, KEY[0], , K1_f_SDRAM, , , , ); --K1L403 is CMD_Decode:u5|oSDR_TXD_DATA[7]~62 K1L403 = KEY[0] & K1_f_SDRAM & (K1_mSDR_ST.100 # K1_mSDR_ST.010); --L1L2 is Multi_Sram:u6|Equal~144 L1L2 = K1_oSR_Select[1] # K1_oSR_Select[0]; --K1L100 is CMD_Decode:u5|Select~2925 K1L100 = !L1L2 & (K1_mSR_ST.100 & A1L303 # !K1_mSR_ST.100 & (A1L287)); --K1L474 is CMD_Decode:u5|oSR_TXD_DATA[7]~62 K1L474 = KEY[0] & K1_f_SRAM & (K1_mSR_ST.100 # K1_mSR_ST.010); --J1_rx_ascii[5] is ps2_keyboard:u4|rx_ascii[5] J1_rx_ascii[5] = DFFEAS(J1L185, CLOCK_50, , , J1L249, , , !KEY[0], ); --J1_m2_state is ps2_keyboard:u4|m2_state J1_m2_state = DFFEAS(J1L115, CLOCK_50, , , , , , !KEY[0], ); --J1_rx_ascii[6] is ps2_keyboard:u4|rx_ascii[6] J1_rx_ascii[6] = DFFEAS(J1L184, CLOCK_50, , , J1L249, , , !KEY[0], ); --J1_rx_ascii[4] is ps2_keyboard:u4|rx_ascii[4] J1_rx_ascii[4] = DFFEAS(J1L231, CLOCK_50, , , J1L249, , , !KEY[0], ); --J1_rx_ascii[2] is ps2_keyboard:u4|rx_ascii[2] J1_rx_ascii[2] = DFFEAS(J1L186, CLOCK_50, , , J1L249, , , !KEY[0], ); --K1L168 is CMD_Decode:u5|f_PS2~215 K1L168 = J1_rx_ascii[6] # J1_rx_ascii[4] # !J1_rx_ascii[2] # !J1_rx_ascii[5]; --J1_rx_ascii[0] is ps2_keyboard:u4|rx_ascii[0] J1_rx_ascii[0] = DFFEAS(J1L187, CLOCK_50, , , J1L249, , , !KEY[0], ); --J1_rx_ascii[1] is ps2_keyboard:u4|rx_ascii[1] J1_rx_ascii[1] = DFFEAS(J1L233, CLOCK_50, , , J1L249, , , !KEY[0], ); --K1L169 is CMD_Decode:u5|f_PS2~216 K1L169 = J1_rx_ascii[0] # !J1_rx_ascii[1]; --J1_rx_ascii[3] is ps2_keyboard:u4|rx_ascii[3] J1_rx_ascii[3] = DFFEAS(J1L241, CLOCK_50, , , J1L249, , , !KEY[0], ); --K1L170 is CMD_Decode:u5|f_PS2~217 K1L170 = J1_m2_state & (K1L168 # K1L169 # !J1_rx_ascii[3]); --K1L346 is CMD_Decode:u5|oPS2_TXD_DATA[6]~1 K1L346 = KEY[0] & K1L170; --V1L13 is USB_JTAG:u1|JTAG_TRANS:u1|rCont~150 V1L13 = !V1_rCont[0] & (K1_sel_FL & (K1_oFL_TXD_Start) # !K1_sel_FL & K1L500); --X1_oDATA[6] is Multi_Flash:u2|Flash_Controller:u1|oDATA[6] X1_oDATA[6] = DFFEAS(A1L109, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L70 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[6]~105 W1L70 = X1_oDATA[6] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[14] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[14] Z1_DATAOUT[14] = DFFEAS(Z1_mDATAOUT[14], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[6] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[6] Z1_DATAOUT[6] = DFFEAS(Z1_mDATAOUT[6], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L101 is CMD_Decode:u5|Select~2926 K1L101 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[14] # !K1_mSDR_ST.100 & (Z1_DATAOUT[6])); --K1L102 is CMD_Decode:u5|Select~2927 K1L102 = !L1L2 & (K1_mSR_ST.100 & A1L305 # !K1_mSR_ST.100 & (A1L289)); --V1L14 is USB_JTAG:u1|JTAG_TRANS:u1|rCont~151 V1L14 = K1L501 & (V1_rCont[0] $ V1_rCont[1]); --X1_oDATA[4] is Multi_Flash:u2|Flash_Controller:u1|oDATA[4] X1_oDATA[4] = DFFEAS(A1L105, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L68 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[4]~106 W1L68 = X1_oDATA[4] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[12] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[12] Z1_DATAOUT[12] = DFFEAS(Z1_mDATAOUT[12], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[4] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[4] Z1_DATAOUT[4] = DFFEAS(Z1_mDATAOUT[4], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L103 is CMD_Decode:u5|Select~2928 K1L103 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[12] # !K1_mSDR_ST.100 & (Z1_DATAOUT[4])); --K1L104 is CMD_Decode:u5|Select~2929 K1L104 = !L1L2 & (K1_mSR_ST.100 & A1L301 # !K1_mSR_ST.100 & (A1L285)); --X1_oDATA[7] is Multi_Flash:u2|Flash_Controller:u1|oDATA[7] X1_oDATA[7] = DFFEAS(A1L111, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L71 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[7]~107 W1L71 = X1_oDATA[7] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[15] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[15] Z1_DATAOUT[15] = DFFEAS(Z1_mDATAOUT[15], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[7] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[7] Z1_DATAOUT[7] = DFFEAS(Z1_mDATAOUT[7], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L105 is CMD_Decode:u5|Select~2930 K1L105 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[15] # !K1_mSDR_ST.100 & (Z1_DATAOUT[7])); --K1L106 is CMD_Decode:u5|Select~2931 K1L106 = !L1L2 & (K1_mSR_ST.100 & A1L307 # !K1_mSR_ST.100 & (A1L291)); --X1_oDATA[2] is Multi_Flash:u2|Flash_Controller:u1|oDATA[2] X1_oDATA[2] = DFFEAS(A1L101, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L66 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[2]~108 W1L66 = X1_oDATA[2] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[10] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[10] Z1_DATAOUT[10] = DFFEAS(Z1_mDATAOUT[10], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[2] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[2] Z1_DATAOUT[2] = DFFEAS(Z1_mDATAOUT[2], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L107 is CMD_Decode:u5|Select~2932 K1L107 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[10] # !K1_mSDR_ST.100 & (Z1_DATAOUT[2])); --K1L108 is CMD_Decode:u5|Select~2933 K1L108 = !L1L2 & (K1_mSR_ST.100 & A1L297 # !K1_mSR_ST.100 & (A1L281)); --X1_oDATA[1] is Multi_Flash:u2|Flash_Controller:u1|oDATA[1] X1_oDATA[1] = DFFEAS(A1L99, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L65 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[1]~109 W1L65 = X1_oDATA[1] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[9] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[9] Z1_DATAOUT[9] = DFFEAS(Z1_mDATAOUT[9], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[1] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[1] Z1_DATAOUT[1] = DFFEAS(Z1_mDATAOUT[1], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L109 is CMD_Decode:u5|Select~2934 K1L109 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[9] # !K1_mSDR_ST.100 & (Z1_DATAOUT[1])); --K1L110 is CMD_Decode:u5|Select~2935 K1L110 = !L1L2 & (K1_mSR_ST.100 & A1L295 # !K1_mSR_ST.100 & (A1L279)); --X1_oDATA[0] is Multi_Flash:u2|Flash_Controller:u1|oDATA[0] X1_oDATA[0] = DFFEAS(A1L97, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L64 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[0]~110 W1L64 = X1_oDATA[0] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[8] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[8] Z1_DATAOUT[8] = DFFEAS(Z1_mDATAOUT[8], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[0] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[0] Z1_DATAOUT[0] = DFFEAS(Z1_mDATAOUT[0], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L111 is CMD_Decode:u5|Select~2936 K1L111 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[8] # !K1_mSDR_ST.100 & (Z1_DATAOUT[0])); --K1L112 is CMD_Decode:u5|Select~2937 K1L112 = !L1L2 & (K1_mSR_ST.100 & A1L293 # !K1_mSR_ST.100 & (A1L277)); --X1_oDATA[3] is Multi_Flash:u2|Flash_Controller:u1|oDATA[3] X1_oDATA[3] = DFFEAS(A1L103, CLOCK_50, KEY[0], , X1L190, , , , ); --W1L67 is Multi_Flash:u2|Flash_Multiplexer:u0|oHS_DATA[3]~111 W1L67 = X1_oDATA[3] & !K1_oFL_Select[0] & !K1_oFL_Select[1]; --Z1_DATAOUT[11] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[11] Z1_DATAOUT[11] = DFFEAS(Z1_mDATAOUT[11], CLOCK_50, KEY[0], , Y1L51, , , , ); --Z1_DATAOUT[3] is Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[3] Z1_DATAOUT[3] = DFFEAS(Z1_mDATAOUT[3], CLOCK_50, KEY[0], , Y1L51, , , , ); --K1L113 is CMD_Decode:u5|Select~2938 K1L113 = !Y1L1 & (K1_mSDR_ST.100 & Z1_DATAOUT[11] # !K1_mSDR_ST.100 & (Z1_DATAOUT[3])); --K1L114 is CMD_Decode:u5|Select~2939 K1L114 = !L1L2 & (K1_mSR_ST.100 & A1L299 # !K1_mSR_ST.100 & (A1L283)); --V1L15 is USB_JTAG:u1|JTAG_TRANS:u1|rCont~152 V1L15 = K1L501 & (V1_rCont[2] $ (V1_rCont[0] & V1_rCont[1])); --MB1_END is I2C_AV_Config:u10|I2C_Controller:u0|END MB1_END = DFFEAS(MB1L14, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1_mSetup_ST.10 is I2C_AV_Config:u10|mSetup_ST.10 P1_mSetup_ST.10 = DFFEAS(P1L90, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1_mSetup_ST.01 is I2C_AV_Config:u10|mSetup_ST.01 P1_mSetup_ST.01 = DFFEAS(P1L20, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1L19 is I2C_AV_Config:u10|Select~135 P1L19 = P1_mI2C_GO & (MB1_END # !P1_mSetup_ST.01) # !P1_mI2C_GO & (!P1_mSetup_ST.10 & !P1_mSetup_ST.01); --P1_mI2C_CLK_DIV[1] is I2C_AV_Config:u10|mI2C_CLK_DIV[1] P1_mI2C_CLK_DIV[1] = DFFEAS(P1L27, CLOCK_50, KEY[0], , , , , P1L18, ); --P1_mI2C_CLK_DIV[0] is I2C_AV_Config:u10|mI2C_CLK_DIV[0] P1_mI2C_CLK_DIV[0] = DFFEAS(P1L24, CLOCK_50, KEY[0], , , , , P1L18, ); --P1L24 is I2C_AV_Config:u10|mI2C_CLK_DIV[0]~239 P1L24 = P1_mI2C_CLK_DIV[0] $ VCC; --P1L25 is I2C_AV_Config:u10|mI2C_CLK_DIV[0]~240 P1L25 = CARRY(P1_mI2C_CLK_DIV[0]); --P1L27 is I2C_AV_Config:u10|mI2C_CLK_DIV[1]~241 P1L27 = P1_mI2C_CLK_DIV[1] & !P1L25 # !P1_mI2C_CLK_DIV[1] & (P1L25 # GND); --P1L28 is I2C_AV_Config:u10|mI2C_CLK_DIV[1]~242 P1L28 = CARRY(!P1L25 # !P1_mI2C_CLK_DIV[1]); --P1L30 is I2C_AV_Config:u10|mI2C_CLK_DIV[2]~243 P1L30 = P1_mI2C_CLK_DIV[2] & (P1L28 $ GND) # !P1_mI2C_CLK_DIV[2] & !P1L28 & VCC; --P1L31 is I2C_AV_Config:u10|mI2C_CLK_DIV[2]~244 P1L31 = CARRY(P1_mI2C_CLK_DIV[2] & !P1L28); --P1L33 is I2C_AV_Config:u10|mI2C_CLK_DIV[3]~245 P1L33 = P1_mI2C_CLK_DIV[3] & !P1L31 # !P1_mI2C_CLK_DIV[3] & (P1L31 # GND); --P1L34 is I2C_AV_Config:u10|mI2C_CLK_DIV[3]~246 P1L34 = CARRY(!P1L31 # !P1_mI2C_CLK_DIV[3]); --P1L36 is I2C_AV_Config:u10|mI2C_CLK_DIV[4]~247 P1L36 = P1_mI2C_CLK_DIV[4] & (P1L34 $ GND) # !P1_mI2C_CLK_DIV[4] & !P1L34 & VCC; --P1L37 is I2C_AV_Config:u10|mI2C_CLK_DIV[4]~248 P1L37 = CARRY(P1_mI2C_CLK_DIV[4] & !P1L34); --P1L39 is I2C_AV_Config:u10|mI2C_CLK_DIV[5]~249 P1L39 = P1_mI2C_CLK_DIV[5] & !P1L37 # !P1_mI2C_CLK_DIV[5] & (P1L37 # GND); --P1L40 is I2C_AV_Config:u10|mI2C_CLK_DIV[5]~250 P1L40 = CARRY(!P1L37 # !P1_mI2C_CLK_DIV[5]); --P1L42 is I2C_AV_Config:u10|mI2C_CLK_DIV[6]~251 P1L42 = P1_mI2C_CLK_DIV[6] & (P1L40 $ GND) # !P1_mI2C_CLK_DIV[6] & !P1L40 & VCC; --P1L43 is I2C_AV_Config:u10|mI2C_CLK_DIV[6]~252 P1L43 = CARRY(P1_mI2C_CLK_DIV[6] & !P1L40); --P1L45 is I2C_AV_Config:u10|mI2C_CLK_DIV[7]~253 P1L45 = P1_mI2C_CLK_DIV[7] & !P1L43 # !P1_mI2C_CLK_DIV[7] & (P1L43 # GND); --P1L46 is I2C_AV_Config:u10|mI2C_CLK_DIV[7]~254 P1L46 = CARRY(!P1L43 # !P1_mI2C_CLK_DIV[7]); --P1L48 is I2C_AV_Config:u10|mI2C_CLK_DIV[8]~255 P1L48 = P1_mI2C_CLK_DIV[8] & (P1L46 $ GND) # !P1_mI2C_CLK_DIV[8] & !P1L46 & VCC; --P1L49 is I2C_AV_Config:u10|mI2C_CLK_DIV[8]~256 P1L49 = CARRY(P1_mI2C_CLK_DIV[8] & !P1L46); --P1L51 is I2C_AV_Config:u10|mI2C_CLK_DIV[9]~257 P1L51 = P1_mI2C_CLK_DIV[9] & !P1L49 # !P1_mI2C_CLK_DIV[9] & (P1L49 # GND); --P1L52 is I2C_AV_Config:u10|mI2C_CLK_DIV[9]~258 P1L52 = CARRY(!P1L49 # !P1_mI2C_CLK_DIV[9]); --P1L54 is I2C_AV_Config:u10|mI2C_CLK_DIV[10]~259 P1L54 = P1_mI2C_CLK_DIV[10] & (P1L52 $ GND) # !P1_mI2C_CLK_DIV[10] & !P1L52 & VCC; --P1L55 is I2C_AV_Config:u10|mI2C_CLK_DIV[10]~260 P1L55 = CARRY(P1_mI2C_CLK_DIV[10] & !P1L52); --P1L57 is I2C_AV_Config:u10|mI2C_CLK_DIV[11]~261 P1L57 = P1_mI2C_CLK_DIV[11] & !P1L55 # !P1_mI2C_CLK_DIV[11] & (P1L55 # GND); --P1L58 is I2C_AV_Config:u10|mI2C_CLK_DIV[11]~262 P1L58 = CARRY(!P1L55 # !P1_mI2C_CLK_DIV[11]); --P1L60 is I2C_AV_Config:u10|mI2C_CLK_DIV[12]~263 P1L60 = P1_mI2C_CLK_DIV[12] & (P1L58 $ GND) # !P1_mI2C_CLK_DIV[12] & !P1L58 & VCC; --P1L61 is I2C_AV_Config:u10|mI2C_CLK_DIV[12]~264 P1L61 = CARRY(P1_mI2C_CLK_DIV[12] & !P1L58); --P1L63 is I2C_AV_Config:u10|mI2C_CLK_DIV[13]~265 P1L63 = P1_mI2C_CLK_DIV[13] & !P1L61 # !P1_mI2C_CLK_DIV[13] & (P1L61 # GND); --P1L64 is I2C_AV_Config:u10|mI2C_CLK_DIV[13]~266 P1L64 = CARRY(!P1L61 # !P1_mI2C_CLK_DIV[13]); --P1L66 is I2C_AV_Config:u10|mI2C_CLK_DIV[14]~267 P1L66 = P1_mI2C_CLK_DIV[14] & (P1L64 $ GND) # !P1_mI2C_CLK_DIV[14] & !P1L64 & VCC; --P1L67 is I2C_AV_Config:u10|mI2C_CLK_DIV[14]~268 P1L67 = CARRY(P1_mI2C_CLK_DIV[14] & !P1L64); --P1L69 is I2C_AV_Config:u10|mI2C_CLK_DIV[15]~269 P1L69 = P1_mI2C_CLK_DIV[15] $ P1L67; --N1L12 is VGA_OSD_RAM:u9|LessThan~477 N1L12 = !M1_oCoord_X[2] & !M1_oCoord_X[3] & !M1_oCoord_X[4] & !M1_oCoord_X[5]; --N1L13 is VGA_OSD_RAM:u9|LessThan~478 N1L13 = !M1_oCoord_X[7] & !M1_oCoord_X[8] & (N1L12 # !M1_oCoord_X[6]); --N1L14 is VGA_OSD_RAM:u9|LessThan~479 N1L14 = !M1_oCoord_Y[6] & !M1_oCoord_Y[7] & !M1_oCoord_Y[8]; --M1L430 is VGA_Controller:u8|oCoord_Y[3]~202 M1L430 = !M1_oCoord_Y[1] & !M1_oCoord_Y[2] & !M1_oCoord_Y[3]; --N1L15 is VGA_OSD_RAM:u9|LessThan~480 N1L15 = N1L14 & (M1L430 # !M1_oCoord_Y[5] # !M1_oCoord_Y[4]); --N1L138 is VGA_OSD_RAM:u9|oRed~81 N1L138 = !M1_oCoord_Y[9] & !N1L15 & (N1L13 # !M1_oCoord_X[9]); --N1L16 is VGA_OSD_RAM:u9|LessThan~481 N1L16 = !M1_oCoord_Y[8] # !M1_oCoord_Y[7] # !M1_oCoord_Y[6]; --N1L17 is VGA_OSD_RAM:u9|LessThan~482 N1L17 = N1L16 # M1L430 & !M1_oCoord_Y[4] & !M1_oCoord_Y[5]; --N1L18 is VGA_OSD_RAM:u9|LessThan~483 N1L18 = !M1_oCoord_X[5] # !M1_oCoord_X[4] # !M1_oCoord_X[3] # !M1_oCoord_X[2]; --N1L19 is VGA_OSD_RAM:u9|LessThan~484 N1L19 = !M1_oCoord_X[6] & !M1_oCoord_X[7] & !M1_oCoord_X[8] & !M1_oCoord_X[9]; --N1L139 is VGA_OSD_RAM:u9|oRed~82 N1L139 = N1L138 & N1L17 & (!N1L19 # !N1L18); --HB1_address_reg_a[9] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[9] HB1_address_reg_a[9] = DFFEAS(HB1_address_reg_a[3], S2__clk0, , , , , , , ); --HB1_address_reg_a[8] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[8] HB1_address_reg_a[8] = DFFEAS(HB1_address_reg_a[2], S2__clk0, , , , , , , ); --HB1_address_reg_a[7] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[7] HB1_address_reg_a[7] = DFFEAS(HB1_address_reg_a[1], S2__clk0, , , , , , , ); --HB1_ram_block2a50 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 400, Port A Width: 8, Port B Depth: 3200, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50 = HB1_ram_block2a50_PORT_A_data_out_reg[0]; --HB1M2542Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT1 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2542Q = HB1_ram_block2a50_PORT_A_data_out_reg[1]; --HB1M2543Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT2 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2543Q = HB1_ram_block2a50_PORT_A_data_out_reg[2]; --HB1M2544Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT3 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2544Q = HB1_ram_block2a50_PORT_A_data_out_reg[3]; --HB1M2545Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT4 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2545Q = HB1_ram_block2a50_PORT_A_data_out_reg[4]; --HB1M2546Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT5 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2546Q = HB1_ram_block2a50_PORT_A_data_out_reg[5]; --HB1M2547Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT6 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2547Q = HB1_ram_block2a50_PORT_A_data_out_reg[6]; --HB1M2548Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT7 HB1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a50_PORT_A_data_in_reg = DFFE(HB1_ram_block2a50_PORT_A_data_in, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_data_in = ~GND; HB1_ram_block2a50_PORT_B_data_in_reg = DFFE(HB1_ram_block2a50_PORT_B_data_in, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a50_PORT_A_address_reg = DFFE(HB1_ram_block2a50_PORT_A_address, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a50_PORT_B_address_reg = DFFE(HB1_ram_block2a50_PORT_B_address, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_PORT_A_write_enable = GND; HB1_ram_block2a50_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_A_write_enable, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1_ram_block2a50_PORT_B_write_enable = GND; HB1_ram_block2a50_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a50_PORT_B_write_enable, HB1_ram_block2a50_clock_1, , , HB1_ram_block2a50_clock_enable_1); HB1_ram_block2a50_clock_0 = S2__clk0; HB1_ram_block2a50_clock_1 = GND; HB1_ram_block2a50_clock_enable_0 = JB3L106; HB1_ram_block2a50_clock_enable_1 = GND; HB1_ram_block2a50_PORT_A_data_out = MEMORY(HB1_ram_block2a50_PORT_A_data_in_reg, HB1_ram_block2a50_PORT_B_data_in_reg, HB1_ram_block2a50_PORT_A_address_reg, HB1_ram_block2a50_PORT_B_address_reg, HB1_ram_block2a50_PORT_A_write_enable_reg, HB1_ram_block2a50_PORT_B_write_enable_reg, , , HB1_ram_block2a50_clock_0, HB1_ram_block2a50_clock_1, HB1_ram_block2a50_clock_enable_0, HB1_ram_block2a50_clock_enable_1, , ); HB1_ram_block2a50_PORT_A_data_out_reg = DFFE(HB1_ram_block2a50_PORT_A_data_out, HB1_ram_block2a50_clock_0, , , HB1_ram_block2a50_clock_enable_0); HB1M2548Q = HB1_ram_block2a50_PORT_A_data_out_reg[7]; --KB1L46 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5031 KB1L46 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2546Q; --HB1_ram_block2a49 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49 = HB1_ram_block2a49_PORT_A_data_out_reg[0]; --HB1M2492Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT1 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2492Q = HB1_ram_block2a49_PORT_A_data_out_reg[1]; --HB1M2493Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT2 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2493Q = HB1_ram_block2a49_PORT_A_data_out_reg[2]; --HB1M2494Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT3 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2494Q = HB1_ram_block2a49_PORT_A_data_out_reg[3]; --HB1M2495Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT4 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2495Q = HB1_ram_block2a49_PORT_A_data_out_reg[4]; --HB1M2496Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT5 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2496Q = HB1_ram_block2a49_PORT_A_data_out_reg[5]; --HB1M2497Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT6 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2497Q = HB1_ram_block2a49_PORT_A_data_out_reg[6]; --HB1M2498Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT7 HB1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a49_PORT_A_data_in_reg = DFFE(HB1_ram_block2a49_PORT_A_data_in, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_data_in = ~GND; HB1_ram_block2a49_PORT_B_data_in_reg = DFFE(HB1_ram_block2a49_PORT_B_data_in, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a49_PORT_A_address_reg = DFFE(HB1_ram_block2a49_PORT_A_address, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a49_PORT_B_address_reg = DFFE(HB1_ram_block2a49_PORT_B_address, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_PORT_A_write_enable = GND; HB1_ram_block2a49_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_A_write_enable, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1_ram_block2a49_PORT_B_write_enable = GND; HB1_ram_block2a49_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a49_PORT_B_write_enable, HB1_ram_block2a49_clock_1, , , HB1_ram_block2a49_clock_enable_1); HB1_ram_block2a49_clock_0 = S2__clk0; HB1_ram_block2a49_clock_1 = GND; HB1_ram_block2a49_clock_enable_0 = JB3L105; HB1_ram_block2a49_clock_enable_1 = GND; HB1_ram_block2a49_PORT_A_data_out = MEMORY(HB1_ram_block2a49_PORT_A_data_in_reg, HB1_ram_block2a49_PORT_B_data_in_reg, HB1_ram_block2a49_PORT_A_address_reg, HB1_ram_block2a49_PORT_B_address_reg, HB1_ram_block2a49_PORT_A_write_enable_reg, HB1_ram_block2a49_PORT_B_write_enable_reg, , , HB1_ram_block2a49_clock_0, HB1_ram_block2a49_clock_1, HB1_ram_block2a49_clock_enable_0, HB1_ram_block2a49_clock_enable_1, , ); HB1_ram_block2a49_PORT_A_data_out_reg = DFFE(HB1_ram_block2a49_PORT_A_data_out, HB1_ram_block2a49_clock_0, , , HB1_ram_block2a49_clock_enable_0); HB1M2498Q = HB1_ram_block2a49_PORT_A_data_out_reg[7]; --HB1_ram_block2a48 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48 = HB1_ram_block2a48_PORT_A_data_out_reg[0]; --HB1M2442Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT1 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2442Q = HB1_ram_block2a48_PORT_A_data_out_reg[1]; --HB1M2443Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT2 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2443Q = HB1_ram_block2a48_PORT_A_data_out_reg[2]; --HB1M2444Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT3 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2444Q = HB1_ram_block2a48_PORT_A_data_out_reg[3]; --HB1M2445Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT4 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2445Q = HB1_ram_block2a48_PORT_A_data_out_reg[4]; --HB1M2446Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT5 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2446Q = HB1_ram_block2a48_PORT_A_data_out_reg[5]; --HB1M2447Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT6 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2447Q = HB1_ram_block2a48_PORT_A_data_out_reg[6]; --HB1M2448Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT7 HB1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a48_PORT_A_data_in_reg = DFFE(HB1_ram_block2a48_PORT_A_data_in, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_data_in = ~GND; HB1_ram_block2a48_PORT_B_data_in_reg = DFFE(HB1_ram_block2a48_PORT_B_data_in, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a48_PORT_A_address_reg = DFFE(HB1_ram_block2a48_PORT_A_address, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a48_PORT_B_address_reg = DFFE(HB1_ram_block2a48_PORT_B_address, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_PORT_A_write_enable = GND; HB1_ram_block2a48_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_A_write_enable, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1_ram_block2a48_PORT_B_write_enable = GND; HB1_ram_block2a48_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a48_PORT_B_write_enable, HB1_ram_block2a48_clock_1, , , HB1_ram_block2a48_clock_enable_1); HB1_ram_block2a48_clock_0 = S2__clk0; HB1_ram_block2a48_clock_1 = GND; HB1_ram_block2a48_clock_enable_0 = JB3L104; HB1_ram_block2a48_clock_enable_1 = GND; HB1_ram_block2a48_PORT_A_data_out = MEMORY(HB1_ram_block2a48_PORT_A_data_in_reg, HB1_ram_block2a48_PORT_B_data_in_reg, HB1_ram_block2a48_PORT_A_address_reg, HB1_ram_block2a48_PORT_B_address_reg, HB1_ram_block2a48_PORT_A_write_enable_reg, HB1_ram_block2a48_PORT_B_write_enable_reg, , , HB1_ram_block2a48_clock_0, HB1_ram_block2a48_clock_1, HB1_ram_block2a48_clock_enable_0, HB1_ram_block2a48_clock_enable_1, , ); HB1_ram_block2a48_PORT_A_data_out_reg = DFFE(HB1_ram_block2a48_PORT_A_data_out, HB1_ram_block2a48_clock_0, , , HB1_ram_block2a48_clock_enable_0); HB1M2448Q = HB1_ram_block2a48_PORT_A_data_out_reg[7]; --HB1_address_reg_a[6] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[6] HB1_address_reg_a[6] = DFFEAS(HB1_address_reg_a[0], S2__clk0, , , , , , , ); --KB1L47 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5032 KB1L47 = HB1_address_reg_a[6] & (HB1M2496Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2446Q & !HB1_address_reg_a[7]); --KB1L48 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5033 KB1L48 = !HB1_address_reg_a[9] & (KB1L46 & HB1_address_reg_a[7] & !KB1L47 # !KB1L46 & !HB1_address_reg_a[7] & KB1L47); --HB1_ram_block2a30 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30 = HB1_ram_block2a30_PORT_A_data_out_reg[0]; --HB1M1542Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT1 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1542Q = HB1_ram_block2a30_PORT_A_data_out_reg[1]; --HB1M1543Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT2 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1543Q = HB1_ram_block2a30_PORT_A_data_out_reg[2]; --HB1M1544Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT3 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1544Q = HB1_ram_block2a30_PORT_A_data_out_reg[3]; --HB1M1545Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT4 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1545Q = HB1_ram_block2a30_PORT_A_data_out_reg[4]; --HB1M1546Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT5 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1546Q = HB1_ram_block2a30_PORT_A_data_out_reg[5]; --HB1M1547Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT6 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1547Q = HB1_ram_block2a30_PORT_A_data_out_reg[6]; --HB1M1548Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT7 HB1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a30_PORT_A_data_in_reg = DFFE(HB1_ram_block2a30_PORT_A_data_in, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_data_in = ~GND; HB1_ram_block2a30_PORT_B_data_in_reg = DFFE(HB1_ram_block2a30_PORT_B_data_in, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a30_PORT_A_address_reg = DFFE(HB1_ram_block2a30_PORT_A_address, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a30_PORT_B_address_reg = DFFE(HB1_ram_block2a30_PORT_B_address, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_PORT_A_write_enable = GND; HB1_ram_block2a30_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_A_write_enable, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1_ram_block2a30_PORT_B_write_enable = GND; HB1_ram_block2a30_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a30_PORT_B_write_enable, HB1_ram_block2a30_clock_1, , , HB1_ram_block2a30_clock_enable_1); HB1_ram_block2a30_clock_0 = S2__clk0; HB1_ram_block2a30_clock_1 = GND; HB1_ram_block2a30_clock_enable_0 = JB3_w_anode3199w[3]; HB1_ram_block2a30_clock_enable_1 = GND; HB1_ram_block2a30_PORT_A_data_out = MEMORY(HB1_ram_block2a30_PORT_A_data_in_reg, HB1_ram_block2a30_PORT_B_data_in_reg, HB1_ram_block2a30_PORT_A_address_reg, HB1_ram_block2a30_PORT_B_address_reg, HB1_ram_block2a30_PORT_A_write_enable_reg, HB1_ram_block2a30_PORT_B_write_enable_reg, , , HB1_ram_block2a30_clock_0, HB1_ram_block2a30_clock_1, HB1_ram_block2a30_clock_enable_0, HB1_ram_block2a30_clock_enable_1, , ); HB1_ram_block2a30_PORT_A_data_out_reg = DFFE(HB1_ram_block2a30_PORT_A_data_out, HB1_ram_block2a30_clock_0, , , HB1_ram_block2a30_clock_enable_0); HB1M1548Q = HB1_ram_block2a30_PORT_A_data_out_reg[7]; --HB1_ram_block2a29 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29 = HB1_ram_block2a29_PORT_A_data_out_reg[0]; --HB1M1492Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT1 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1492Q = HB1_ram_block2a29_PORT_A_data_out_reg[1]; --HB1M1493Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT2 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1493Q = HB1_ram_block2a29_PORT_A_data_out_reg[2]; --HB1M1494Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT3 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1494Q = HB1_ram_block2a29_PORT_A_data_out_reg[3]; --HB1M1495Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT4 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1495Q = HB1_ram_block2a29_PORT_A_data_out_reg[4]; --HB1M1496Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT5 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1496Q = HB1_ram_block2a29_PORT_A_data_out_reg[5]; --HB1M1497Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT6 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1497Q = HB1_ram_block2a29_PORT_A_data_out_reg[6]; --HB1M1498Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT7 HB1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a29_PORT_A_data_in_reg = DFFE(HB1_ram_block2a29_PORT_A_data_in, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_data_in = ~GND; HB1_ram_block2a29_PORT_B_data_in_reg = DFFE(HB1_ram_block2a29_PORT_B_data_in, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a29_PORT_A_address_reg = DFFE(HB1_ram_block2a29_PORT_A_address, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a29_PORT_B_address_reg = DFFE(HB1_ram_block2a29_PORT_B_address, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_PORT_A_write_enable = GND; HB1_ram_block2a29_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_A_write_enable, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1_ram_block2a29_PORT_B_write_enable = GND; HB1_ram_block2a29_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a29_PORT_B_write_enable, HB1_ram_block2a29_clock_1, , , HB1_ram_block2a29_clock_enable_1); HB1_ram_block2a29_clock_0 = S2__clk0; HB1_ram_block2a29_clock_1 = GND; HB1_ram_block2a29_clock_enable_0 = JB3_w_anode3189w[3]; HB1_ram_block2a29_clock_enable_1 = GND; HB1_ram_block2a29_PORT_A_data_out = MEMORY(HB1_ram_block2a29_PORT_A_data_in_reg, HB1_ram_block2a29_PORT_B_data_in_reg, HB1_ram_block2a29_PORT_A_address_reg, HB1_ram_block2a29_PORT_B_address_reg, HB1_ram_block2a29_PORT_A_write_enable_reg, HB1_ram_block2a29_PORT_B_write_enable_reg, , , HB1_ram_block2a29_clock_0, HB1_ram_block2a29_clock_1, HB1_ram_block2a29_clock_enable_0, HB1_ram_block2a29_clock_enable_1, , ); HB1_ram_block2a29_PORT_A_data_out_reg = DFFE(HB1_ram_block2a29_PORT_A_data_out, HB1_ram_block2a29_clock_0, , , HB1_ram_block2a29_clock_enable_0); HB1M1498Q = HB1_ram_block2a29_PORT_A_data_out_reg[7]; --HB1_ram_block2a28 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28 = HB1_ram_block2a28_PORT_A_data_out_reg[0]; --HB1M1442Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT1 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1442Q = HB1_ram_block2a28_PORT_A_data_out_reg[1]; --HB1M1443Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT2 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1443Q = HB1_ram_block2a28_PORT_A_data_out_reg[2]; --HB1M1444Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT3 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1444Q = HB1_ram_block2a28_PORT_A_data_out_reg[3]; --HB1M1445Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT4 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1445Q = HB1_ram_block2a28_PORT_A_data_out_reg[4]; --HB1M1446Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT5 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1446Q = HB1_ram_block2a28_PORT_A_data_out_reg[5]; --HB1M1447Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT6 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1447Q = HB1_ram_block2a28_PORT_A_data_out_reg[6]; --HB1M1448Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT7 HB1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a28_PORT_A_data_in_reg = DFFE(HB1_ram_block2a28_PORT_A_data_in, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_data_in = ~GND; HB1_ram_block2a28_PORT_B_data_in_reg = DFFE(HB1_ram_block2a28_PORT_B_data_in, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a28_PORT_A_address_reg = DFFE(HB1_ram_block2a28_PORT_A_address, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a28_PORT_B_address_reg = DFFE(HB1_ram_block2a28_PORT_B_address, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_PORT_A_write_enable = GND; HB1_ram_block2a28_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_A_write_enable, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1_ram_block2a28_PORT_B_write_enable = GND; HB1_ram_block2a28_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a28_PORT_B_write_enable, HB1_ram_block2a28_clock_1, , , HB1_ram_block2a28_clock_enable_1); HB1_ram_block2a28_clock_0 = S2__clk0; HB1_ram_block2a28_clock_1 = GND; HB1_ram_block2a28_clock_enable_0 = JB3_w_anode3179w[3]; HB1_ram_block2a28_clock_enable_1 = GND; HB1_ram_block2a28_PORT_A_data_out = MEMORY(HB1_ram_block2a28_PORT_A_data_in_reg, HB1_ram_block2a28_PORT_B_data_in_reg, HB1_ram_block2a28_PORT_A_address_reg, HB1_ram_block2a28_PORT_B_address_reg, HB1_ram_block2a28_PORT_A_write_enable_reg, HB1_ram_block2a28_PORT_B_write_enable_reg, , , HB1_ram_block2a28_clock_0, HB1_ram_block2a28_clock_1, HB1_ram_block2a28_clock_enable_0, HB1_ram_block2a28_clock_enable_1, , ); HB1_ram_block2a28_PORT_A_data_out_reg = DFFE(HB1_ram_block2a28_PORT_A_data_out, HB1_ram_block2a28_clock_0, , , HB1_ram_block2a28_clock_enable_0); HB1M1448Q = HB1_ram_block2a28_PORT_A_data_out_reg[7]; --KB1L222 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~49 KB1L222 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1496Q # !HB1_address_reg_a[6] & (HB1M1446Q)); --HB1_ram_block2a31 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31 = HB1_ram_block2a31_PORT_A_data_out_reg[0]; --HB1M1592Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT1 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1592Q = HB1_ram_block2a31_PORT_A_data_out_reg[1]; --HB1M1593Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT2 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1593Q = HB1_ram_block2a31_PORT_A_data_out_reg[2]; --HB1M1594Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT3 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1594Q = HB1_ram_block2a31_PORT_A_data_out_reg[3]; --HB1M1595Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT4 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1595Q = HB1_ram_block2a31_PORT_A_data_out_reg[4]; --HB1M1596Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT5 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1596Q = HB1_ram_block2a31_PORT_A_data_out_reg[5]; --HB1M1597Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT6 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1597Q = HB1_ram_block2a31_PORT_A_data_out_reg[6]; --HB1M1598Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT7 HB1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a31_PORT_A_data_in_reg = DFFE(HB1_ram_block2a31_PORT_A_data_in, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_data_in = ~GND; HB1_ram_block2a31_PORT_B_data_in_reg = DFFE(HB1_ram_block2a31_PORT_B_data_in, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a31_PORT_A_address_reg = DFFE(HB1_ram_block2a31_PORT_A_address, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a31_PORT_B_address_reg = DFFE(HB1_ram_block2a31_PORT_B_address, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_PORT_A_write_enable = GND; HB1_ram_block2a31_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_A_write_enable, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1_ram_block2a31_PORT_B_write_enable = GND; HB1_ram_block2a31_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a31_PORT_B_write_enable, HB1_ram_block2a31_clock_1, , , HB1_ram_block2a31_clock_enable_1); HB1_ram_block2a31_clock_0 = S2__clk0; HB1_ram_block2a31_clock_1 = GND; HB1_ram_block2a31_clock_enable_0 = JB3_w_anode3209w[3]; HB1_ram_block2a31_clock_enable_1 = GND; HB1_ram_block2a31_PORT_A_data_out = MEMORY(HB1_ram_block2a31_PORT_A_data_in_reg, HB1_ram_block2a31_PORT_B_data_in_reg, HB1_ram_block2a31_PORT_A_address_reg, HB1_ram_block2a31_PORT_B_address_reg, HB1_ram_block2a31_PORT_A_write_enable_reg, HB1_ram_block2a31_PORT_B_write_enable_reg, , , HB1_ram_block2a31_clock_0, HB1_ram_block2a31_clock_1, HB1_ram_block2a31_clock_enable_0, HB1_ram_block2a31_clock_enable_1, , ); HB1_ram_block2a31_PORT_A_data_out_reg = DFFE(HB1_ram_block2a31_PORT_A_data_out, HB1_ram_block2a31_clock_0, , , HB1_ram_block2a31_clock_enable_0); HB1M1598Q = HB1_ram_block2a31_PORT_A_data_out_reg[7]; --KB1L223 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~50 KB1L223 = HB1_address_reg_a[7] & (KB1L222 & (HB1M1596Q) # !KB1L222 & HB1M1546Q) # !HB1_address_reg_a[7] & (KB1L222); --HB1_ram_block2a21 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21 = HB1_ram_block2a21_PORT_A_data_out_reg[0]; --HB1M1092Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT1 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1092Q = HB1_ram_block2a21_PORT_A_data_out_reg[1]; --HB1M1093Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT2 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1093Q = HB1_ram_block2a21_PORT_A_data_out_reg[2]; --HB1M1094Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT3 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1094Q = HB1_ram_block2a21_PORT_A_data_out_reg[3]; --HB1M1095Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT4 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1095Q = HB1_ram_block2a21_PORT_A_data_out_reg[4]; --HB1M1096Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT5 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1096Q = HB1_ram_block2a21_PORT_A_data_out_reg[5]; --HB1M1097Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT6 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1097Q = HB1_ram_block2a21_PORT_A_data_out_reg[6]; --HB1M1098Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT7 HB1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a21_PORT_A_data_in_reg = DFFE(HB1_ram_block2a21_PORT_A_data_in, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_data_in = ~GND; HB1_ram_block2a21_PORT_B_data_in_reg = DFFE(HB1_ram_block2a21_PORT_B_data_in, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a21_PORT_A_address_reg = DFFE(HB1_ram_block2a21_PORT_A_address, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a21_PORT_B_address_reg = DFFE(HB1_ram_block2a21_PORT_B_address, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_PORT_A_write_enable = GND; HB1_ram_block2a21_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_A_write_enable, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1_ram_block2a21_PORT_B_write_enable = GND; HB1_ram_block2a21_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a21_PORT_B_write_enable, HB1_ram_block2a21_clock_1, , , HB1_ram_block2a21_clock_enable_1); HB1_ram_block2a21_clock_0 = S2__clk0; HB1_ram_block2a21_clock_1 = GND; HB1_ram_block2a21_clock_enable_0 = JB3_w_anode3096w[3]; HB1_ram_block2a21_clock_enable_1 = GND; HB1_ram_block2a21_PORT_A_data_out = MEMORY(HB1_ram_block2a21_PORT_A_data_in_reg, HB1_ram_block2a21_PORT_B_data_in_reg, HB1_ram_block2a21_PORT_A_address_reg, HB1_ram_block2a21_PORT_B_address_reg, HB1_ram_block2a21_PORT_A_write_enable_reg, HB1_ram_block2a21_PORT_B_write_enable_reg, , , HB1_ram_block2a21_clock_0, HB1_ram_block2a21_clock_1, HB1_ram_block2a21_clock_enable_0, HB1_ram_block2a21_clock_enable_1, , ); HB1_ram_block2a21_PORT_A_data_out_reg = DFFE(HB1_ram_block2a21_PORT_A_data_out, HB1_ram_block2a21_clock_0, , , HB1_ram_block2a21_clock_enable_0); HB1M1098Q = HB1_ram_block2a21_PORT_A_data_out_reg[7]; --HB1_ram_block2a22 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22 = HB1_ram_block2a22_PORT_A_data_out_reg[0]; --HB1M1142Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT1 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1142Q = HB1_ram_block2a22_PORT_A_data_out_reg[1]; --HB1M1143Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT2 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1143Q = HB1_ram_block2a22_PORT_A_data_out_reg[2]; --HB1M1144Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT3 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1144Q = HB1_ram_block2a22_PORT_A_data_out_reg[3]; --HB1M1145Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT4 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1145Q = HB1_ram_block2a22_PORT_A_data_out_reg[4]; --HB1M1146Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT5 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1146Q = HB1_ram_block2a22_PORT_A_data_out_reg[5]; --HB1M1147Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT6 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1147Q = HB1_ram_block2a22_PORT_A_data_out_reg[6]; --HB1M1148Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT7 HB1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a22_PORT_A_data_in_reg = DFFE(HB1_ram_block2a22_PORT_A_data_in, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_data_in = ~GND; HB1_ram_block2a22_PORT_B_data_in_reg = DFFE(HB1_ram_block2a22_PORT_B_data_in, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a22_PORT_A_address_reg = DFFE(HB1_ram_block2a22_PORT_A_address, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a22_PORT_B_address_reg = DFFE(HB1_ram_block2a22_PORT_B_address, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_PORT_A_write_enable = GND; HB1_ram_block2a22_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_A_write_enable, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1_ram_block2a22_PORT_B_write_enable = GND; HB1_ram_block2a22_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a22_PORT_B_write_enable, HB1_ram_block2a22_clock_1, , , HB1_ram_block2a22_clock_enable_1); HB1_ram_block2a22_clock_0 = S2__clk0; HB1_ram_block2a22_clock_1 = GND; HB1_ram_block2a22_clock_enable_0 = JB3_w_anode3106w[3]; HB1_ram_block2a22_clock_enable_1 = GND; HB1_ram_block2a22_PORT_A_data_out = MEMORY(HB1_ram_block2a22_PORT_A_data_in_reg, HB1_ram_block2a22_PORT_B_data_in_reg, HB1_ram_block2a22_PORT_A_address_reg, HB1_ram_block2a22_PORT_B_address_reg, HB1_ram_block2a22_PORT_A_write_enable_reg, HB1_ram_block2a22_PORT_B_write_enable_reg, , , HB1_ram_block2a22_clock_0, HB1_ram_block2a22_clock_1, HB1_ram_block2a22_clock_enable_0, HB1_ram_block2a22_clock_enable_1, , ); HB1_ram_block2a22_PORT_A_data_out_reg = DFFE(HB1_ram_block2a22_PORT_A_data_out, HB1_ram_block2a22_clock_0, , , HB1_ram_block2a22_clock_enable_0); HB1M1148Q = HB1_ram_block2a22_PORT_A_data_out_reg[7]; --HB1_ram_block2a20 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20 = HB1_ram_block2a20_PORT_A_data_out_reg[0]; --HB1M1042Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT1 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1042Q = HB1_ram_block2a20_PORT_A_data_out_reg[1]; --HB1M1043Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT2 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1043Q = HB1_ram_block2a20_PORT_A_data_out_reg[2]; --HB1M1044Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT3 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1044Q = HB1_ram_block2a20_PORT_A_data_out_reg[3]; --HB1M1045Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT4 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1045Q = HB1_ram_block2a20_PORT_A_data_out_reg[4]; --HB1M1046Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT5 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1046Q = HB1_ram_block2a20_PORT_A_data_out_reg[5]; --HB1M1047Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT6 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1047Q = HB1_ram_block2a20_PORT_A_data_out_reg[6]; --HB1M1048Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT7 HB1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a20_PORT_A_data_in_reg = DFFE(HB1_ram_block2a20_PORT_A_data_in, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_data_in = ~GND; HB1_ram_block2a20_PORT_B_data_in_reg = DFFE(HB1_ram_block2a20_PORT_B_data_in, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a20_PORT_A_address_reg = DFFE(HB1_ram_block2a20_PORT_A_address, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a20_PORT_B_address_reg = DFFE(HB1_ram_block2a20_PORT_B_address, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_PORT_A_write_enable = GND; HB1_ram_block2a20_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_A_write_enable, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1_ram_block2a20_PORT_B_write_enable = GND; HB1_ram_block2a20_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a20_PORT_B_write_enable, HB1_ram_block2a20_clock_1, , , HB1_ram_block2a20_clock_enable_1); HB1_ram_block2a20_clock_0 = S2__clk0; HB1_ram_block2a20_clock_1 = GND; HB1_ram_block2a20_clock_enable_0 = JB3_w_anode3086w[3]; HB1_ram_block2a20_clock_enable_1 = GND; HB1_ram_block2a20_PORT_A_data_out = MEMORY(HB1_ram_block2a20_PORT_A_data_in_reg, HB1_ram_block2a20_PORT_B_data_in_reg, HB1_ram_block2a20_PORT_A_address_reg, HB1_ram_block2a20_PORT_B_address_reg, HB1_ram_block2a20_PORT_A_write_enable_reg, HB1_ram_block2a20_PORT_B_write_enable_reg, , , HB1_ram_block2a20_clock_0, HB1_ram_block2a20_clock_1, HB1_ram_block2a20_clock_enable_0, HB1_ram_block2a20_clock_enable_1, , ); HB1_ram_block2a20_PORT_A_data_out_reg = DFFE(HB1_ram_block2a20_PORT_A_data_out, HB1_ram_block2a20_clock_0, , , HB1_ram_block2a20_clock_enable_0); HB1M1048Q = HB1_ram_block2a20_PORT_A_data_out_reg[7]; --KB1L220 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~44 KB1L220 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1146Q # !HB1_address_reg_a[7] & (HB1M1046Q)); --HB1_ram_block2a23 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23 = HB1_ram_block2a23_PORT_A_data_out_reg[0]; --HB1M1192Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT1 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1192Q = HB1_ram_block2a23_PORT_A_data_out_reg[1]; --HB1M1193Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT2 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1193Q = HB1_ram_block2a23_PORT_A_data_out_reg[2]; --HB1M1194Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT3 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1194Q = HB1_ram_block2a23_PORT_A_data_out_reg[3]; --HB1M1195Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT4 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1195Q = HB1_ram_block2a23_PORT_A_data_out_reg[4]; --HB1M1196Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT5 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1196Q = HB1_ram_block2a23_PORT_A_data_out_reg[5]; --HB1M1197Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT6 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1197Q = HB1_ram_block2a23_PORT_A_data_out_reg[6]; --HB1M1198Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT7 HB1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a23_PORT_A_data_in_reg = DFFE(HB1_ram_block2a23_PORT_A_data_in, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_data_in = ~GND; HB1_ram_block2a23_PORT_B_data_in_reg = DFFE(HB1_ram_block2a23_PORT_B_data_in, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a23_PORT_A_address_reg = DFFE(HB1_ram_block2a23_PORT_A_address, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a23_PORT_B_address_reg = DFFE(HB1_ram_block2a23_PORT_B_address, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_PORT_A_write_enable = GND; HB1_ram_block2a23_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_A_write_enable, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1_ram_block2a23_PORT_B_write_enable = GND; HB1_ram_block2a23_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a23_PORT_B_write_enable, HB1_ram_block2a23_clock_1, , , HB1_ram_block2a23_clock_enable_1); HB1_ram_block2a23_clock_0 = S2__clk0; HB1_ram_block2a23_clock_1 = GND; HB1_ram_block2a23_clock_enable_0 = JB3_w_anode3116w[3]; HB1_ram_block2a23_clock_enable_1 = GND; HB1_ram_block2a23_PORT_A_data_out = MEMORY(HB1_ram_block2a23_PORT_A_data_in_reg, HB1_ram_block2a23_PORT_B_data_in_reg, HB1_ram_block2a23_PORT_A_address_reg, HB1_ram_block2a23_PORT_B_address_reg, HB1_ram_block2a23_PORT_A_write_enable_reg, HB1_ram_block2a23_PORT_B_write_enable_reg, , , HB1_ram_block2a23_clock_0, HB1_ram_block2a23_clock_1, HB1_ram_block2a23_clock_enable_0, HB1_ram_block2a23_clock_enable_1, , ); HB1_ram_block2a23_PORT_A_data_out_reg = DFFE(HB1_ram_block2a23_PORT_A_data_out, HB1_ram_block2a23_clock_0, , , HB1_ram_block2a23_clock_enable_0); HB1M1198Q = HB1_ram_block2a23_PORT_A_data_out_reg[7]; --KB1L221 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~45 KB1L221 = HB1_address_reg_a[6] & (KB1L220 & (HB1M1196Q) # !KB1L220 & HB1M1096Q) # !HB1_address_reg_a[6] & (KB1L220); --KB1L49 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5034 KB1L49 = HB1_address_reg_a[9] & KB1L223 # !HB1_address_reg_a[9] & (KB1L221); --HB1_ram_block2a17 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17 = HB1_ram_block2a17_PORT_A_data_out_reg[0]; --HB1M892Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT1 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M892Q = HB1_ram_block2a17_PORT_A_data_out_reg[1]; --HB1M893Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT2 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M893Q = HB1_ram_block2a17_PORT_A_data_out_reg[2]; --HB1M894Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT3 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M894Q = HB1_ram_block2a17_PORT_A_data_out_reg[3]; --HB1M895Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT4 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M895Q = HB1_ram_block2a17_PORT_A_data_out_reg[4]; --HB1M896Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT5 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M896Q = HB1_ram_block2a17_PORT_A_data_out_reg[5]; --HB1M897Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT6 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M897Q = HB1_ram_block2a17_PORT_A_data_out_reg[6]; --HB1M898Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT7 HB1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a17_PORT_A_data_in_reg = DFFE(HB1_ram_block2a17_PORT_A_data_in, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_data_in = ~GND; HB1_ram_block2a17_PORT_B_data_in_reg = DFFE(HB1_ram_block2a17_PORT_B_data_in, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a17_PORT_A_address_reg = DFFE(HB1_ram_block2a17_PORT_A_address, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a17_PORT_B_address_reg = DFFE(HB1_ram_block2a17_PORT_B_address, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_PORT_A_write_enable = GND; HB1_ram_block2a17_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_A_write_enable, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1_ram_block2a17_PORT_B_write_enable = GND; HB1_ram_block2a17_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a17_PORT_B_write_enable, HB1_ram_block2a17_clock_1, , , HB1_ram_block2a17_clock_enable_1); HB1_ram_block2a17_clock_0 = S2__clk0; HB1_ram_block2a17_clock_1 = GND; HB1_ram_block2a17_clock_enable_0 = JB3_w_anode3056w[3]; HB1_ram_block2a17_clock_enable_1 = GND; HB1_ram_block2a17_PORT_A_data_out = MEMORY(HB1_ram_block2a17_PORT_A_data_in_reg, HB1_ram_block2a17_PORT_B_data_in_reg, HB1_ram_block2a17_PORT_A_address_reg, HB1_ram_block2a17_PORT_B_address_reg, HB1_ram_block2a17_PORT_A_write_enable_reg, HB1_ram_block2a17_PORT_B_write_enable_reg, , , HB1_ram_block2a17_clock_0, HB1_ram_block2a17_clock_1, HB1_ram_block2a17_clock_enable_0, HB1_ram_block2a17_clock_enable_1, , ); HB1_ram_block2a17_PORT_A_data_out_reg = DFFE(HB1_ram_block2a17_PORT_A_data_out, HB1_ram_block2a17_clock_0, , , HB1_ram_block2a17_clock_enable_0); HB1M898Q = HB1_ram_block2a17_PORT_A_data_out_reg[7]; --HB1_ram_block2a18 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18 = HB1_ram_block2a18_PORT_A_data_out_reg[0]; --HB1M942Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT1 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M942Q = HB1_ram_block2a18_PORT_A_data_out_reg[1]; --HB1M943Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT2 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M943Q = HB1_ram_block2a18_PORT_A_data_out_reg[2]; --HB1M944Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT3 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M944Q = HB1_ram_block2a18_PORT_A_data_out_reg[3]; --HB1M945Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT4 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M945Q = HB1_ram_block2a18_PORT_A_data_out_reg[4]; --HB1M946Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT5 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M946Q = HB1_ram_block2a18_PORT_A_data_out_reg[5]; --HB1M947Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT6 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M947Q = HB1_ram_block2a18_PORT_A_data_out_reg[6]; --HB1M948Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT7 HB1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a18_PORT_A_data_in_reg = DFFE(HB1_ram_block2a18_PORT_A_data_in, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_data_in = ~GND; HB1_ram_block2a18_PORT_B_data_in_reg = DFFE(HB1_ram_block2a18_PORT_B_data_in, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a18_PORT_A_address_reg = DFFE(HB1_ram_block2a18_PORT_A_address, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a18_PORT_B_address_reg = DFFE(HB1_ram_block2a18_PORT_B_address, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_PORT_A_write_enable = GND; HB1_ram_block2a18_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_A_write_enable, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1_ram_block2a18_PORT_B_write_enable = GND; HB1_ram_block2a18_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a18_PORT_B_write_enable, HB1_ram_block2a18_clock_1, , , HB1_ram_block2a18_clock_enable_1); HB1_ram_block2a18_clock_0 = S2__clk0; HB1_ram_block2a18_clock_1 = GND; HB1_ram_block2a18_clock_enable_0 = JB3_w_anode3066w[3]; HB1_ram_block2a18_clock_enable_1 = GND; HB1_ram_block2a18_PORT_A_data_out = MEMORY(HB1_ram_block2a18_PORT_A_data_in_reg, HB1_ram_block2a18_PORT_B_data_in_reg, HB1_ram_block2a18_PORT_A_address_reg, HB1_ram_block2a18_PORT_B_address_reg, HB1_ram_block2a18_PORT_A_write_enable_reg, HB1_ram_block2a18_PORT_B_write_enable_reg, , , HB1_ram_block2a18_clock_0, HB1_ram_block2a18_clock_1, HB1_ram_block2a18_clock_enable_0, HB1_ram_block2a18_clock_enable_1, , ); HB1_ram_block2a18_PORT_A_data_out_reg = DFFE(HB1_ram_block2a18_PORT_A_data_out, HB1_ram_block2a18_clock_0, , , HB1_ram_block2a18_clock_enable_0); HB1M948Q = HB1_ram_block2a18_PORT_A_data_out_reg[7]; --HB1_ram_block2a16 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16 = HB1_ram_block2a16_PORT_A_data_out_reg[0]; --HB1M842Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT1 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M842Q = HB1_ram_block2a16_PORT_A_data_out_reg[1]; --HB1M843Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT2 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M843Q = HB1_ram_block2a16_PORT_A_data_out_reg[2]; --HB1M844Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT3 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M844Q = HB1_ram_block2a16_PORT_A_data_out_reg[3]; --HB1M845Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT4 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M845Q = HB1_ram_block2a16_PORT_A_data_out_reg[4]; --HB1M846Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT5 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M846Q = HB1_ram_block2a16_PORT_A_data_out_reg[5]; --HB1M847Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT6 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M847Q = HB1_ram_block2a16_PORT_A_data_out_reg[6]; --HB1M848Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT7 HB1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a16_PORT_A_data_in_reg = DFFE(HB1_ram_block2a16_PORT_A_data_in, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_data_in = ~GND; HB1_ram_block2a16_PORT_B_data_in_reg = DFFE(HB1_ram_block2a16_PORT_B_data_in, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a16_PORT_A_address_reg = DFFE(HB1_ram_block2a16_PORT_A_address, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a16_PORT_B_address_reg = DFFE(HB1_ram_block2a16_PORT_B_address, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_PORT_A_write_enable = GND; HB1_ram_block2a16_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_A_write_enable, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1_ram_block2a16_PORT_B_write_enable = GND; HB1_ram_block2a16_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a16_PORT_B_write_enable, HB1_ram_block2a16_clock_1, , , HB1_ram_block2a16_clock_enable_1); HB1_ram_block2a16_clock_0 = S2__clk0; HB1_ram_block2a16_clock_1 = GND; HB1_ram_block2a16_clock_enable_0 = JB3_w_anode3045w[3]; HB1_ram_block2a16_clock_enable_1 = GND; HB1_ram_block2a16_PORT_A_data_out = MEMORY(HB1_ram_block2a16_PORT_A_data_in_reg, HB1_ram_block2a16_PORT_B_data_in_reg, HB1_ram_block2a16_PORT_A_address_reg, HB1_ram_block2a16_PORT_B_address_reg, HB1_ram_block2a16_PORT_A_write_enable_reg, HB1_ram_block2a16_PORT_B_write_enable_reg, , , HB1_ram_block2a16_clock_0, HB1_ram_block2a16_clock_1, HB1_ram_block2a16_clock_enable_0, HB1_ram_block2a16_clock_enable_1, , ); HB1_ram_block2a16_PORT_A_data_out_reg = DFFE(HB1_ram_block2a16_PORT_A_data_out, HB1_ram_block2a16_clock_0, , , HB1_ram_block2a16_clock_enable_0); HB1M848Q = HB1_ram_block2a16_PORT_A_data_out_reg[7]; --KB1L224 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~407 KB1L224 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M946Q # !HB1_address_reg_a[7] & (HB1M846Q)); --HB1_ram_block2a19 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19 = HB1_ram_block2a19_PORT_A_data_out_reg[0]; --HB1M992Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT1 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M992Q = HB1_ram_block2a19_PORT_A_data_out_reg[1]; --HB1M993Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT2 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M993Q = HB1_ram_block2a19_PORT_A_data_out_reg[2]; --HB1M994Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT3 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M994Q = HB1_ram_block2a19_PORT_A_data_out_reg[3]; --HB1M995Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT4 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M995Q = HB1_ram_block2a19_PORT_A_data_out_reg[4]; --HB1M996Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT5 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M996Q = HB1_ram_block2a19_PORT_A_data_out_reg[5]; --HB1M997Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT6 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M997Q = HB1_ram_block2a19_PORT_A_data_out_reg[6]; --HB1M998Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT7 HB1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a19_PORT_A_data_in_reg = DFFE(HB1_ram_block2a19_PORT_A_data_in, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_data_in = ~GND; HB1_ram_block2a19_PORT_B_data_in_reg = DFFE(HB1_ram_block2a19_PORT_B_data_in, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a19_PORT_A_address_reg = DFFE(HB1_ram_block2a19_PORT_A_address, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a19_PORT_B_address_reg = DFFE(HB1_ram_block2a19_PORT_B_address, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_PORT_A_write_enable = GND; HB1_ram_block2a19_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_A_write_enable, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1_ram_block2a19_PORT_B_write_enable = GND; HB1_ram_block2a19_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a19_PORT_B_write_enable, HB1_ram_block2a19_clock_1, , , HB1_ram_block2a19_clock_enable_1); HB1_ram_block2a19_clock_0 = S2__clk0; HB1_ram_block2a19_clock_1 = GND; HB1_ram_block2a19_clock_enable_0 = JB3_w_anode3076w[3]; HB1_ram_block2a19_clock_enable_1 = GND; HB1_ram_block2a19_PORT_A_data_out = MEMORY(HB1_ram_block2a19_PORT_A_data_in_reg, HB1_ram_block2a19_PORT_B_data_in_reg, HB1_ram_block2a19_PORT_A_address_reg, HB1_ram_block2a19_PORT_B_address_reg, HB1_ram_block2a19_PORT_A_write_enable_reg, HB1_ram_block2a19_PORT_B_write_enable_reg, , , HB1_ram_block2a19_clock_0, HB1_ram_block2a19_clock_1, HB1_ram_block2a19_clock_enable_0, HB1_ram_block2a19_clock_enable_1, , ); HB1_ram_block2a19_PORT_A_data_out_reg = DFFE(HB1_ram_block2a19_PORT_A_data_out, HB1_ram_block2a19_clock_0, , , HB1_ram_block2a19_clock_enable_0); HB1M998Q = HB1_ram_block2a19_PORT_A_data_out_reg[7]; --KB1L225 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~408 KB1L225 = HB1_address_reg_a[6] & (KB1L224 & (HB1M996Q) # !KB1L224 & HB1M896Q) # !HB1_address_reg_a[6] & (KB1L224); --HB1_ram_block2a27 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27 = HB1_ram_block2a27_PORT_A_data_out_reg[0]; --HB1M1392Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT1 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1392Q = HB1_ram_block2a27_PORT_A_data_out_reg[1]; --HB1M1393Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT2 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1393Q = HB1_ram_block2a27_PORT_A_data_out_reg[2]; --HB1M1394Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT3 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1394Q = HB1_ram_block2a27_PORT_A_data_out_reg[3]; --HB1M1395Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT4 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1395Q = HB1_ram_block2a27_PORT_A_data_out_reg[4]; --HB1M1396Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT5 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1396Q = HB1_ram_block2a27_PORT_A_data_out_reg[5]; --HB1M1397Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT6 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1397Q = HB1_ram_block2a27_PORT_A_data_out_reg[6]; --HB1M1398Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT7 HB1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a27_PORT_A_data_in_reg = DFFE(HB1_ram_block2a27_PORT_A_data_in, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_data_in = ~GND; HB1_ram_block2a27_PORT_B_data_in_reg = DFFE(HB1_ram_block2a27_PORT_B_data_in, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a27_PORT_A_address_reg = DFFE(HB1_ram_block2a27_PORT_A_address, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a27_PORT_B_address_reg = DFFE(HB1_ram_block2a27_PORT_B_address, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_PORT_A_write_enable = GND; HB1_ram_block2a27_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_A_write_enable, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1_ram_block2a27_PORT_B_write_enable = GND; HB1_ram_block2a27_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a27_PORT_B_write_enable, HB1_ram_block2a27_clock_1, , , HB1_ram_block2a27_clock_enable_1); HB1_ram_block2a27_clock_0 = S2__clk0; HB1_ram_block2a27_clock_1 = GND; HB1_ram_block2a27_clock_enable_0 = JB3_w_anode3169w[3]; HB1_ram_block2a27_clock_enable_1 = GND; HB1_ram_block2a27_PORT_A_data_out = MEMORY(HB1_ram_block2a27_PORT_A_data_in_reg, HB1_ram_block2a27_PORT_B_data_in_reg, HB1_ram_block2a27_PORT_A_address_reg, HB1_ram_block2a27_PORT_B_address_reg, HB1_ram_block2a27_PORT_A_write_enable_reg, HB1_ram_block2a27_PORT_B_write_enable_reg, , , HB1_ram_block2a27_clock_0, HB1_ram_block2a27_clock_1, HB1_ram_block2a27_clock_enable_0, HB1_ram_block2a27_clock_enable_1, , ); HB1_ram_block2a27_PORT_A_data_out_reg = DFFE(HB1_ram_block2a27_PORT_A_data_out, HB1_ram_block2a27_clock_0, , , HB1_ram_block2a27_clock_enable_0); HB1M1398Q = HB1_ram_block2a27_PORT_A_data_out_reg[7]; --HB1_ram_block2a26 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26 = HB1_ram_block2a26_PORT_A_data_out_reg[0]; --HB1M1342Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT1 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1342Q = HB1_ram_block2a26_PORT_A_data_out_reg[1]; --HB1M1343Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT2 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1343Q = HB1_ram_block2a26_PORT_A_data_out_reg[2]; --HB1M1344Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT3 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1344Q = HB1_ram_block2a26_PORT_A_data_out_reg[3]; --HB1M1345Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT4 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1345Q = HB1_ram_block2a26_PORT_A_data_out_reg[4]; --HB1M1346Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT5 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1346Q = HB1_ram_block2a26_PORT_A_data_out_reg[5]; --HB1M1347Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT6 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1347Q = HB1_ram_block2a26_PORT_A_data_out_reg[6]; --HB1M1348Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT7 HB1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a26_PORT_A_data_in_reg = DFFE(HB1_ram_block2a26_PORT_A_data_in, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_data_in = ~GND; HB1_ram_block2a26_PORT_B_data_in_reg = DFFE(HB1_ram_block2a26_PORT_B_data_in, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a26_PORT_A_address_reg = DFFE(HB1_ram_block2a26_PORT_A_address, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a26_PORT_B_address_reg = DFFE(HB1_ram_block2a26_PORT_B_address, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_PORT_A_write_enable = GND; HB1_ram_block2a26_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_A_write_enable, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1_ram_block2a26_PORT_B_write_enable = GND; HB1_ram_block2a26_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a26_PORT_B_write_enable, HB1_ram_block2a26_clock_1, , , HB1_ram_block2a26_clock_enable_1); HB1_ram_block2a26_clock_0 = S2__clk0; HB1_ram_block2a26_clock_1 = GND; HB1_ram_block2a26_clock_enable_0 = JB3_w_anode3159w[3]; HB1_ram_block2a26_clock_enable_1 = GND; HB1_ram_block2a26_PORT_A_data_out = MEMORY(HB1_ram_block2a26_PORT_A_data_in_reg, HB1_ram_block2a26_PORT_B_data_in_reg, HB1_ram_block2a26_PORT_A_address_reg, HB1_ram_block2a26_PORT_B_address_reg, HB1_ram_block2a26_PORT_A_write_enable_reg, HB1_ram_block2a26_PORT_B_write_enable_reg, , , HB1_ram_block2a26_clock_0, HB1_ram_block2a26_clock_1, HB1_ram_block2a26_clock_enable_0, HB1_ram_block2a26_clock_enable_1, , ); HB1_ram_block2a26_PORT_A_data_out_reg = DFFE(HB1_ram_block2a26_PORT_A_data_out, HB1_ram_block2a26_clock_0, , , HB1_ram_block2a26_clock_enable_0); HB1M1348Q = HB1_ram_block2a26_PORT_A_data_out_reg[7]; --KB1L50 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5035 KB1L50 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1396Q # !HB1_address_reg_a[6] & (HB1M1346Q)); --HB1_ram_block2a25 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25 = HB1_ram_block2a25_PORT_A_data_out_reg[0]; --HB1M1292Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT1 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1292Q = HB1_ram_block2a25_PORT_A_data_out_reg[1]; --HB1M1293Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT2 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1293Q = HB1_ram_block2a25_PORT_A_data_out_reg[2]; --HB1M1294Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT3 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1294Q = HB1_ram_block2a25_PORT_A_data_out_reg[3]; --HB1M1295Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT4 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1295Q = HB1_ram_block2a25_PORT_A_data_out_reg[4]; --HB1M1296Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT5 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1296Q = HB1_ram_block2a25_PORT_A_data_out_reg[5]; --HB1M1297Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT6 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1297Q = HB1_ram_block2a25_PORT_A_data_out_reg[6]; --HB1M1298Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT7 HB1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a25_PORT_A_data_in_reg = DFFE(HB1_ram_block2a25_PORT_A_data_in, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_data_in = ~GND; HB1_ram_block2a25_PORT_B_data_in_reg = DFFE(HB1_ram_block2a25_PORT_B_data_in, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a25_PORT_A_address_reg = DFFE(HB1_ram_block2a25_PORT_A_address, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a25_PORT_B_address_reg = DFFE(HB1_ram_block2a25_PORT_B_address, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_PORT_A_write_enable = GND; HB1_ram_block2a25_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_A_write_enable, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1_ram_block2a25_PORT_B_write_enable = GND; HB1_ram_block2a25_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a25_PORT_B_write_enable, HB1_ram_block2a25_clock_1, , , HB1_ram_block2a25_clock_enable_1); HB1_ram_block2a25_clock_0 = S2__clk0; HB1_ram_block2a25_clock_1 = GND; HB1_ram_block2a25_clock_enable_0 = JB3_w_anode3149w[3]; HB1_ram_block2a25_clock_enable_1 = GND; HB1_ram_block2a25_PORT_A_data_out = MEMORY(HB1_ram_block2a25_PORT_A_data_in_reg, HB1_ram_block2a25_PORT_B_data_in_reg, HB1_ram_block2a25_PORT_A_address_reg, HB1_ram_block2a25_PORT_B_address_reg, HB1_ram_block2a25_PORT_A_write_enable_reg, HB1_ram_block2a25_PORT_B_write_enable_reg, , , HB1_ram_block2a25_clock_0, HB1_ram_block2a25_clock_1, HB1_ram_block2a25_clock_enable_0, HB1_ram_block2a25_clock_enable_1, , ); HB1_ram_block2a25_PORT_A_data_out_reg = DFFE(HB1_ram_block2a25_PORT_A_data_out, HB1_ram_block2a25_clock_0, , , HB1_ram_block2a25_clock_enable_0); HB1M1298Q = HB1_ram_block2a25_PORT_A_data_out_reg[7]; --HB1_ram_block2a24 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24 = HB1_ram_block2a24_PORT_A_data_out_reg[0]; --HB1M1242Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT1 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1242Q = HB1_ram_block2a24_PORT_A_data_out_reg[1]; --HB1M1243Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT2 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1243Q = HB1_ram_block2a24_PORT_A_data_out_reg[2]; --HB1M1244Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT3 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1244Q = HB1_ram_block2a24_PORT_A_data_out_reg[3]; --HB1M1245Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT4 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1245Q = HB1_ram_block2a24_PORT_A_data_out_reg[4]; --HB1M1246Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT5 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1246Q = HB1_ram_block2a24_PORT_A_data_out_reg[5]; --HB1M1247Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT6 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1247Q = HB1_ram_block2a24_PORT_A_data_out_reg[6]; --HB1M1248Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT7 HB1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a24_PORT_A_data_in_reg = DFFE(HB1_ram_block2a24_PORT_A_data_in, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_data_in = ~GND; HB1_ram_block2a24_PORT_B_data_in_reg = DFFE(HB1_ram_block2a24_PORT_B_data_in, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a24_PORT_A_address_reg = DFFE(HB1_ram_block2a24_PORT_A_address, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a24_PORT_B_address_reg = DFFE(HB1_ram_block2a24_PORT_B_address, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_PORT_A_write_enable = GND; HB1_ram_block2a24_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_A_write_enable, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1_ram_block2a24_PORT_B_write_enable = GND; HB1_ram_block2a24_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a24_PORT_B_write_enable, HB1_ram_block2a24_clock_1, , , HB1_ram_block2a24_clock_enable_1); HB1_ram_block2a24_clock_0 = S2__clk0; HB1_ram_block2a24_clock_1 = GND; HB1_ram_block2a24_clock_enable_0 = JB3_w_anode3138w[3]; HB1_ram_block2a24_clock_enable_1 = GND; HB1_ram_block2a24_PORT_A_data_out = MEMORY(HB1_ram_block2a24_PORT_A_data_in_reg, HB1_ram_block2a24_PORT_B_data_in_reg, HB1_ram_block2a24_PORT_A_address_reg, HB1_ram_block2a24_PORT_B_address_reg, HB1_ram_block2a24_PORT_A_write_enable_reg, HB1_ram_block2a24_PORT_B_write_enable_reg, , , HB1_ram_block2a24_clock_0, HB1_ram_block2a24_clock_1, HB1_ram_block2a24_clock_enable_0, HB1_ram_block2a24_clock_enable_1, , ); HB1_ram_block2a24_PORT_A_data_out_reg = DFFE(HB1_ram_block2a24_PORT_A_data_out, HB1_ram_block2a24_clock_0, , , HB1_ram_block2a24_clock_enable_0); HB1M1248Q = HB1_ram_block2a24_PORT_A_data_out_reg[7]; --KB1L51 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5036 KB1L51 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1296Q # !HB1_address_reg_a[6] & (HB1M1246Q)); --KB1L52 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5037 KB1L52 = HB1_address_reg_a[9] & (KB1L50 # KB1L51) # !HB1_address_reg_a[9] & KB1L225; --KB1L53 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5038 KB1L53 = HB1_address_reg_a[8] & KB1L49 # !HB1_address_reg_a[8] & (KB1L52); --HB1_address_reg_a[11] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[11] HB1_address_reg_a[11] = DFFEAS(HB1_address_reg_a[5], S2__clk0, , , , , , , ); --HB1_address_reg_a[10] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[10] HB1_address_reg_a[10] = DFFEAS(HB1_address_reg_a[4], S2__clk0, , , , , , , ); --KB1L147 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~608 KB1L147 = HB1_address_reg_a[11] & HB1_address_reg_a[10]; --KB1L232 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~573 KB1L232 = HB1_address_reg_a[8] & !HB1_address_reg_a[10]; --HB1_ram_block2a46 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46 = HB1_ram_block2a46_PORT_A_data_out_reg[0]; --HB1M2342Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT1 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2342Q = HB1_ram_block2a46_PORT_A_data_out_reg[1]; --HB1M2343Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT2 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2343Q = HB1_ram_block2a46_PORT_A_data_out_reg[2]; --HB1M2344Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT3 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2344Q = HB1_ram_block2a46_PORT_A_data_out_reg[3]; --HB1M2345Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT4 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2345Q = HB1_ram_block2a46_PORT_A_data_out_reg[4]; --HB1M2346Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT5 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2346Q = HB1_ram_block2a46_PORT_A_data_out_reg[5]; --HB1M2347Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT6 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2347Q = HB1_ram_block2a46_PORT_A_data_out_reg[6]; --HB1M2348Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT7 HB1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a46_PORT_A_data_in_reg = DFFE(HB1_ram_block2a46_PORT_A_data_in, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_data_in = ~GND; HB1_ram_block2a46_PORT_B_data_in_reg = DFFE(HB1_ram_block2a46_PORT_B_data_in, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a46_PORT_A_address_reg = DFFE(HB1_ram_block2a46_PORT_A_address, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a46_PORT_B_address_reg = DFFE(HB1_ram_block2a46_PORT_B_address, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_PORT_A_write_enable = GND; HB1_ram_block2a46_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_A_write_enable, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1_ram_block2a46_PORT_B_write_enable = GND; HB1_ram_block2a46_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a46_PORT_B_write_enable, HB1_ram_block2a46_clock_1, , , HB1_ram_block2a46_clock_enable_1); HB1_ram_block2a46_clock_0 = S2__clk0; HB1_ram_block2a46_clock_1 = GND; HB1_ram_block2a46_clock_enable_0 = JB3_w_anode3385w[3]; HB1_ram_block2a46_clock_enable_1 = GND; HB1_ram_block2a46_PORT_A_data_out = MEMORY(HB1_ram_block2a46_PORT_A_data_in_reg, HB1_ram_block2a46_PORT_B_data_in_reg, HB1_ram_block2a46_PORT_A_address_reg, HB1_ram_block2a46_PORT_B_address_reg, HB1_ram_block2a46_PORT_A_write_enable_reg, HB1_ram_block2a46_PORT_B_write_enable_reg, , , HB1_ram_block2a46_clock_0, HB1_ram_block2a46_clock_1, HB1_ram_block2a46_clock_enable_0, HB1_ram_block2a46_clock_enable_1, , ); HB1_ram_block2a46_PORT_A_data_out_reg = DFFE(HB1_ram_block2a46_PORT_A_data_out, HB1_ram_block2a46_clock_0, , , HB1_ram_block2a46_clock_enable_0); HB1M2348Q = HB1_ram_block2a46_PORT_A_data_out_reg[7]; --HB1_ram_block2a45 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45 = HB1_ram_block2a45_PORT_A_data_out_reg[0]; --HB1M2292Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT1 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2292Q = HB1_ram_block2a45_PORT_A_data_out_reg[1]; --HB1M2293Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT2 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2293Q = HB1_ram_block2a45_PORT_A_data_out_reg[2]; --HB1M2294Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT3 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2294Q = HB1_ram_block2a45_PORT_A_data_out_reg[3]; --HB1M2295Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT4 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2295Q = HB1_ram_block2a45_PORT_A_data_out_reg[4]; --HB1M2296Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT5 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2296Q = HB1_ram_block2a45_PORT_A_data_out_reg[5]; --HB1M2297Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT6 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2297Q = HB1_ram_block2a45_PORT_A_data_out_reg[6]; --HB1M2298Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT7 HB1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a45_PORT_A_data_in_reg = DFFE(HB1_ram_block2a45_PORT_A_data_in, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_data_in = ~GND; HB1_ram_block2a45_PORT_B_data_in_reg = DFFE(HB1_ram_block2a45_PORT_B_data_in, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a45_PORT_A_address_reg = DFFE(HB1_ram_block2a45_PORT_A_address, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a45_PORT_B_address_reg = DFFE(HB1_ram_block2a45_PORT_B_address, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_PORT_A_write_enable = GND; HB1_ram_block2a45_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_A_write_enable, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1_ram_block2a45_PORT_B_write_enable = GND; HB1_ram_block2a45_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a45_PORT_B_write_enable, HB1_ram_block2a45_clock_1, , , HB1_ram_block2a45_clock_enable_1); HB1_ram_block2a45_clock_0 = S2__clk0; HB1_ram_block2a45_clock_1 = GND; HB1_ram_block2a45_clock_enable_0 = JB3_w_anode3375w[3]; HB1_ram_block2a45_clock_enable_1 = GND; HB1_ram_block2a45_PORT_A_data_out = MEMORY(HB1_ram_block2a45_PORT_A_data_in_reg, HB1_ram_block2a45_PORT_B_data_in_reg, HB1_ram_block2a45_PORT_A_address_reg, HB1_ram_block2a45_PORT_B_address_reg, HB1_ram_block2a45_PORT_A_write_enable_reg, HB1_ram_block2a45_PORT_B_write_enable_reg, , , HB1_ram_block2a45_clock_0, HB1_ram_block2a45_clock_1, HB1_ram_block2a45_clock_enable_0, HB1_ram_block2a45_clock_enable_1, , ); HB1_ram_block2a45_PORT_A_data_out_reg = DFFE(HB1_ram_block2a45_PORT_A_data_out, HB1_ram_block2a45_clock_0, , , HB1_ram_block2a45_clock_enable_0); HB1M2298Q = HB1_ram_block2a45_PORT_A_data_out_reg[7]; --HB1_ram_block2a44 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44 = HB1_ram_block2a44_PORT_A_data_out_reg[0]; --HB1M2242Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT1 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2242Q = HB1_ram_block2a44_PORT_A_data_out_reg[1]; --HB1M2243Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT2 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2243Q = HB1_ram_block2a44_PORT_A_data_out_reg[2]; --HB1M2244Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT3 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2244Q = HB1_ram_block2a44_PORT_A_data_out_reg[3]; --HB1M2245Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT4 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2245Q = HB1_ram_block2a44_PORT_A_data_out_reg[4]; --HB1M2246Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT5 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2246Q = HB1_ram_block2a44_PORT_A_data_out_reg[5]; --HB1M2247Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT6 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2247Q = HB1_ram_block2a44_PORT_A_data_out_reg[6]; --HB1M2248Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT7 HB1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a44_PORT_A_data_in_reg = DFFE(HB1_ram_block2a44_PORT_A_data_in, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_data_in = ~GND; HB1_ram_block2a44_PORT_B_data_in_reg = DFFE(HB1_ram_block2a44_PORT_B_data_in, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a44_PORT_A_address_reg = DFFE(HB1_ram_block2a44_PORT_A_address, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a44_PORT_B_address_reg = DFFE(HB1_ram_block2a44_PORT_B_address, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_PORT_A_write_enable = GND; HB1_ram_block2a44_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_A_write_enable, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1_ram_block2a44_PORT_B_write_enable = GND; HB1_ram_block2a44_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a44_PORT_B_write_enable, HB1_ram_block2a44_clock_1, , , HB1_ram_block2a44_clock_enable_1); HB1_ram_block2a44_clock_0 = S2__clk0; HB1_ram_block2a44_clock_1 = GND; HB1_ram_block2a44_clock_enable_0 = JB3_w_anode3365w[3]; HB1_ram_block2a44_clock_enable_1 = GND; HB1_ram_block2a44_PORT_A_data_out = MEMORY(HB1_ram_block2a44_PORT_A_data_in_reg, HB1_ram_block2a44_PORT_B_data_in_reg, HB1_ram_block2a44_PORT_A_address_reg, HB1_ram_block2a44_PORT_B_address_reg, HB1_ram_block2a44_PORT_A_write_enable_reg, HB1_ram_block2a44_PORT_B_write_enable_reg, , , HB1_ram_block2a44_clock_0, HB1_ram_block2a44_clock_1, HB1_ram_block2a44_clock_enable_0, HB1_ram_block2a44_clock_enable_1, , ); HB1_ram_block2a44_PORT_A_data_out_reg = DFFE(HB1_ram_block2a44_PORT_A_data_out, HB1_ram_block2a44_clock_0, , , HB1_ram_block2a44_clock_enable_0); HB1M2248Q = HB1_ram_block2a44_PORT_A_data_out_reg[7]; --KB1L228 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~47 KB1L228 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M2296Q # !HB1_address_reg_a[6] & (HB1M2246Q)); --HB1_ram_block2a47 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47 = HB1_ram_block2a47_PORT_A_data_out_reg[0]; --HB1M2392Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT1 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2392Q = HB1_ram_block2a47_PORT_A_data_out_reg[1]; --HB1M2393Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT2 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2393Q = HB1_ram_block2a47_PORT_A_data_out_reg[2]; --HB1M2394Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT3 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2394Q = HB1_ram_block2a47_PORT_A_data_out_reg[3]; --HB1M2395Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT4 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2395Q = HB1_ram_block2a47_PORT_A_data_out_reg[4]; --HB1M2396Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT5 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2396Q = HB1_ram_block2a47_PORT_A_data_out_reg[5]; --HB1M2397Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT6 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2397Q = HB1_ram_block2a47_PORT_A_data_out_reg[6]; --HB1M2398Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT7 HB1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a47_PORT_A_data_in_reg = DFFE(HB1_ram_block2a47_PORT_A_data_in, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_data_in = ~GND; HB1_ram_block2a47_PORT_B_data_in_reg = DFFE(HB1_ram_block2a47_PORT_B_data_in, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a47_PORT_A_address_reg = DFFE(HB1_ram_block2a47_PORT_A_address, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a47_PORT_B_address_reg = DFFE(HB1_ram_block2a47_PORT_B_address, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_PORT_A_write_enable = GND; HB1_ram_block2a47_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_A_write_enable, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1_ram_block2a47_PORT_B_write_enable = GND; HB1_ram_block2a47_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a47_PORT_B_write_enable, HB1_ram_block2a47_clock_1, , , HB1_ram_block2a47_clock_enable_1); HB1_ram_block2a47_clock_0 = S2__clk0; HB1_ram_block2a47_clock_1 = GND; HB1_ram_block2a47_clock_enable_0 = JB3_w_anode3395w[3]; HB1_ram_block2a47_clock_enable_1 = GND; HB1_ram_block2a47_PORT_A_data_out = MEMORY(HB1_ram_block2a47_PORT_A_data_in_reg, HB1_ram_block2a47_PORT_B_data_in_reg, HB1_ram_block2a47_PORT_A_address_reg, HB1_ram_block2a47_PORT_B_address_reg, HB1_ram_block2a47_PORT_A_write_enable_reg, HB1_ram_block2a47_PORT_B_write_enable_reg, , , HB1_ram_block2a47_clock_0, HB1_ram_block2a47_clock_1, HB1_ram_block2a47_clock_enable_0, HB1_ram_block2a47_clock_enable_1, , ); HB1_ram_block2a47_PORT_A_data_out_reg = DFFE(HB1_ram_block2a47_PORT_A_data_out, HB1_ram_block2a47_clock_0, , , HB1_ram_block2a47_clock_enable_0); HB1M2398Q = HB1_ram_block2a47_PORT_A_data_out_reg[7]; --KB1L229 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~48 KB1L229 = HB1_address_reg_a[7] & (KB1L228 & (HB1M2396Q) # !KB1L228 & HB1M2346Q) # !HB1_address_reg_a[7] & (KB1L228); --HB1_ram_block2a13 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13 = HB1_ram_block2a13_PORT_A_data_out_reg[0]; --HB1M692Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT1 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M692Q = HB1_ram_block2a13_PORT_A_data_out_reg[1]; --HB1M693Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT2 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M693Q = HB1_ram_block2a13_PORT_A_data_out_reg[2]; --HB1M694Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT3 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M694Q = HB1_ram_block2a13_PORT_A_data_out_reg[3]; --HB1M695Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT4 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M695Q = HB1_ram_block2a13_PORT_A_data_out_reg[4]; --HB1M696Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT5 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M696Q = HB1_ram_block2a13_PORT_A_data_out_reg[5]; --HB1M697Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT6 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M697Q = HB1_ram_block2a13_PORT_A_data_out_reg[6]; --HB1M698Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT7 HB1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a13_PORT_A_data_in_reg = DFFE(HB1_ram_block2a13_PORT_A_data_in, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_data_in = ~GND; HB1_ram_block2a13_PORT_B_data_in_reg = DFFE(HB1_ram_block2a13_PORT_B_data_in, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a13_PORT_A_address_reg = DFFE(HB1_ram_block2a13_PORT_A_address, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a13_PORT_B_address_reg = DFFE(HB1_ram_block2a13_PORT_B_address, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_PORT_A_write_enable = GND; HB1_ram_block2a13_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_A_write_enable, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1_ram_block2a13_PORT_B_write_enable = GND; HB1_ram_block2a13_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a13_PORT_B_write_enable, HB1_ram_block2a13_clock_1, , , HB1_ram_block2a13_clock_enable_1); HB1_ram_block2a13_clock_0 = S2__clk0; HB1_ram_block2a13_clock_1 = GND; HB1_ram_block2a13_clock_enable_0 = JB3_w_anode3003w[3]; HB1_ram_block2a13_clock_enable_1 = GND; HB1_ram_block2a13_PORT_A_data_out = MEMORY(HB1_ram_block2a13_PORT_A_data_in_reg, HB1_ram_block2a13_PORT_B_data_in_reg, HB1_ram_block2a13_PORT_A_address_reg, HB1_ram_block2a13_PORT_B_address_reg, HB1_ram_block2a13_PORT_A_write_enable_reg, HB1_ram_block2a13_PORT_B_write_enable_reg, , , HB1_ram_block2a13_clock_0, HB1_ram_block2a13_clock_1, HB1_ram_block2a13_clock_enable_0, HB1_ram_block2a13_clock_enable_1, , ); HB1_ram_block2a13_PORT_A_data_out_reg = DFFE(HB1_ram_block2a13_PORT_A_data_out, HB1_ram_block2a13_clock_0, , , HB1_ram_block2a13_clock_enable_0); HB1M698Q = HB1_ram_block2a13_PORT_A_data_out_reg[7]; --HB1_ram_block2a14 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14 = HB1_ram_block2a14_PORT_A_data_out_reg[0]; --HB1M742Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT1 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M742Q = HB1_ram_block2a14_PORT_A_data_out_reg[1]; --HB1M743Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT2 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M743Q = HB1_ram_block2a14_PORT_A_data_out_reg[2]; --HB1M744Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT3 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M744Q = HB1_ram_block2a14_PORT_A_data_out_reg[3]; --HB1M745Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT4 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M745Q = HB1_ram_block2a14_PORT_A_data_out_reg[4]; --HB1M746Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT5 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M746Q = HB1_ram_block2a14_PORT_A_data_out_reg[5]; --HB1M747Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT6 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M747Q = HB1_ram_block2a14_PORT_A_data_out_reg[6]; --HB1M748Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT7 HB1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a14_PORT_A_data_in_reg = DFFE(HB1_ram_block2a14_PORT_A_data_in, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_data_in = ~GND; HB1_ram_block2a14_PORT_B_data_in_reg = DFFE(HB1_ram_block2a14_PORT_B_data_in, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a14_PORT_A_address_reg = DFFE(HB1_ram_block2a14_PORT_A_address, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a14_PORT_B_address_reg = DFFE(HB1_ram_block2a14_PORT_B_address, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_PORT_A_write_enable = GND; HB1_ram_block2a14_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_A_write_enable, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1_ram_block2a14_PORT_B_write_enable = GND; HB1_ram_block2a14_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a14_PORT_B_write_enable, HB1_ram_block2a14_clock_1, , , HB1_ram_block2a14_clock_enable_1); HB1_ram_block2a14_clock_0 = S2__clk0; HB1_ram_block2a14_clock_1 = GND; HB1_ram_block2a14_clock_enable_0 = JB3_w_anode3013w[3]; HB1_ram_block2a14_clock_enable_1 = GND; HB1_ram_block2a14_PORT_A_data_out = MEMORY(HB1_ram_block2a14_PORT_A_data_in_reg, HB1_ram_block2a14_PORT_B_data_in_reg, HB1_ram_block2a14_PORT_A_address_reg, HB1_ram_block2a14_PORT_B_address_reg, HB1_ram_block2a14_PORT_A_write_enable_reg, HB1_ram_block2a14_PORT_B_write_enable_reg, , , HB1_ram_block2a14_clock_0, HB1_ram_block2a14_clock_1, HB1_ram_block2a14_clock_enable_0, HB1_ram_block2a14_clock_enable_1, , ); HB1_ram_block2a14_PORT_A_data_out_reg = DFFE(HB1_ram_block2a14_PORT_A_data_out, HB1_ram_block2a14_clock_0, , , HB1_ram_block2a14_clock_enable_0); HB1M748Q = HB1_ram_block2a14_PORT_A_data_out_reg[7]; --HB1_ram_block2a12 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12 = HB1_ram_block2a12_PORT_A_data_out_reg[0]; --HB1M642Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT1 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M642Q = HB1_ram_block2a12_PORT_A_data_out_reg[1]; --HB1M643Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT2 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M643Q = HB1_ram_block2a12_PORT_A_data_out_reg[2]; --HB1M644Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT3 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M644Q = HB1_ram_block2a12_PORT_A_data_out_reg[3]; --HB1M645Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT4 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M645Q = HB1_ram_block2a12_PORT_A_data_out_reg[4]; --HB1M646Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT5 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M646Q = HB1_ram_block2a12_PORT_A_data_out_reg[5]; --HB1M647Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT6 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M647Q = HB1_ram_block2a12_PORT_A_data_out_reg[6]; --HB1M648Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT7 HB1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a12_PORT_A_data_in_reg = DFFE(HB1_ram_block2a12_PORT_A_data_in, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_data_in = ~GND; HB1_ram_block2a12_PORT_B_data_in_reg = DFFE(HB1_ram_block2a12_PORT_B_data_in, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a12_PORT_A_address_reg = DFFE(HB1_ram_block2a12_PORT_A_address, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a12_PORT_B_address_reg = DFFE(HB1_ram_block2a12_PORT_B_address, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_PORT_A_write_enable = GND; HB1_ram_block2a12_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_A_write_enable, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1_ram_block2a12_PORT_B_write_enable = GND; HB1_ram_block2a12_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a12_PORT_B_write_enable, HB1_ram_block2a12_clock_1, , , HB1_ram_block2a12_clock_enable_1); HB1_ram_block2a12_clock_0 = S2__clk0; HB1_ram_block2a12_clock_1 = GND; HB1_ram_block2a12_clock_enable_0 = JB3_w_anode2993w[3]; HB1_ram_block2a12_clock_enable_1 = GND; HB1_ram_block2a12_PORT_A_data_out = MEMORY(HB1_ram_block2a12_PORT_A_data_in_reg, HB1_ram_block2a12_PORT_B_data_in_reg, HB1_ram_block2a12_PORT_A_address_reg, HB1_ram_block2a12_PORT_B_address_reg, HB1_ram_block2a12_PORT_A_write_enable_reg, HB1_ram_block2a12_PORT_B_write_enable_reg, , , HB1_ram_block2a12_clock_0, HB1_ram_block2a12_clock_1, HB1_ram_block2a12_clock_enable_0, HB1_ram_block2a12_clock_enable_1, , ); HB1_ram_block2a12_PORT_A_data_out_reg = DFFE(HB1_ram_block2a12_PORT_A_data_out, HB1_ram_block2a12_clock_0, , , HB1_ram_block2a12_clock_enable_0); HB1M648Q = HB1_ram_block2a12_PORT_A_data_out_reg[7]; --KB1L216 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~47 KB1L216 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M746Q # !HB1_address_reg_a[7] & (HB1M646Q)); --HB1_ram_block2a15 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15 = HB1_ram_block2a15_PORT_A_data_out_reg[0]; --HB1M792Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT1 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M792Q = HB1_ram_block2a15_PORT_A_data_out_reg[1]; --HB1M793Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT2 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M793Q = HB1_ram_block2a15_PORT_A_data_out_reg[2]; --HB1M794Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT3 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M794Q = HB1_ram_block2a15_PORT_A_data_out_reg[3]; --HB1M795Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT4 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M795Q = HB1_ram_block2a15_PORT_A_data_out_reg[4]; --HB1M796Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT5 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M796Q = HB1_ram_block2a15_PORT_A_data_out_reg[5]; --HB1M797Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT6 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M797Q = HB1_ram_block2a15_PORT_A_data_out_reg[6]; --HB1M798Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT7 HB1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a15_PORT_A_data_in_reg = DFFE(HB1_ram_block2a15_PORT_A_data_in, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_data_in = ~GND; HB1_ram_block2a15_PORT_B_data_in_reg = DFFE(HB1_ram_block2a15_PORT_B_data_in, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a15_PORT_A_address_reg = DFFE(HB1_ram_block2a15_PORT_A_address, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a15_PORT_B_address_reg = DFFE(HB1_ram_block2a15_PORT_B_address, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_PORT_A_write_enable = GND; HB1_ram_block2a15_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_A_write_enable, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1_ram_block2a15_PORT_B_write_enable = GND; HB1_ram_block2a15_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a15_PORT_B_write_enable, HB1_ram_block2a15_clock_1, , , HB1_ram_block2a15_clock_enable_1); HB1_ram_block2a15_clock_0 = S2__clk0; HB1_ram_block2a15_clock_1 = GND; HB1_ram_block2a15_clock_enable_0 = JB3_w_anode3023w[3]; HB1_ram_block2a15_clock_enable_1 = GND; HB1_ram_block2a15_PORT_A_data_out = MEMORY(HB1_ram_block2a15_PORT_A_data_in_reg, HB1_ram_block2a15_PORT_B_data_in_reg, HB1_ram_block2a15_PORT_A_address_reg, HB1_ram_block2a15_PORT_B_address_reg, HB1_ram_block2a15_PORT_A_write_enable_reg, HB1_ram_block2a15_PORT_B_write_enable_reg, , , HB1_ram_block2a15_clock_0, HB1_ram_block2a15_clock_1, HB1_ram_block2a15_clock_enable_0, HB1_ram_block2a15_clock_enable_1, , ); HB1_ram_block2a15_PORT_A_data_out_reg = DFFE(HB1_ram_block2a15_PORT_A_data_out, HB1_ram_block2a15_clock_0, , , HB1_ram_block2a15_clock_enable_0); HB1M798Q = HB1_ram_block2a15_PORT_A_data_out_reg[7]; --KB1L217 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~48 KB1L217 = HB1_address_reg_a[6] & (KB1L216 & (HB1M796Q) # !KB1L216 & HB1M696Q) # !HB1_address_reg_a[6] & (KB1L216); --KB1L233 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~574 KB1L233 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L229 # !HB1_address_reg_a[11] & (KB1L217)); --HB1_ram_block2a37 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37 = HB1_ram_block2a37_PORT_A_data_out_reg[0]; --HB1M1892Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT1 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1892Q = HB1_ram_block2a37_PORT_A_data_out_reg[1]; --HB1M1893Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT2 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1893Q = HB1_ram_block2a37_PORT_A_data_out_reg[2]; --HB1M1894Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT3 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1894Q = HB1_ram_block2a37_PORT_A_data_out_reg[3]; --HB1M1895Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT4 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1895Q = HB1_ram_block2a37_PORT_A_data_out_reg[4]; --HB1M1896Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT5 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1896Q = HB1_ram_block2a37_PORT_A_data_out_reg[5]; --HB1M1897Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT6 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1897Q = HB1_ram_block2a37_PORT_A_data_out_reg[6]; --HB1M1898Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT7 HB1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a37_PORT_A_data_in_reg = DFFE(HB1_ram_block2a37_PORT_A_data_in, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_data_in = ~GND; HB1_ram_block2a37_PORT_B_data_in_reg = DFFE(HB1_ram_block2a37_PORT_B_data_in, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a37_PORT_A_address_reg = DFFE(HB1_ram_block2a37_PORT_A_address, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a37_PORT_B_address_reg = DFFE(HB1_ram_block2a37_PORT_B_address, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_PORT_A_write_enable = GND; HB1_ram_block2a37_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_A_write_enable, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1_ram_block2a37_PORT_B_write_enable = GND; HB1_ram_block2a37_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a37_PORT_B_write_enable, HB1_ram_block2a37_clock_1, , , HB1_ram_block2a37_clock_enable_1); HB1_ram_block2a37_clock_0 = S2__clk0; HB1_ram_block2a37_clock_1 = GND; HB1_ram_block2a37_clock_enable_0 = JB3_w_anode3282w[3]; HB1_ram_block2a37_clock_enable_1 = GND; HB1_ram_block2a37_PORT_A_data_out = MEMORY(HB1_ram_block2a37_PORT_A_data_in_reg, HB1_ram_block2a37_PORT_B_data_in_reg, HB1_ram_block2a37_PORT_A_address_reg, HB1_ram_block2a37_PORT_B_address_reg, HB1_ram_block2a37_PORT_A_write_enable_reg, HB1_ram_block2a37_PORT_B_write_enable_reg, , , HB1_ram_block2a37_clock_0, HB1_ram_block2a37_clock_1, HB1_ram_block2a37_clock_enable_0, HB1_ram_block2a37_clock_enable_1, , ); HB1_ram_block2a37_PORT_A_data_out_reg = DFFE(HB1_ram_block2a37_PORT_A_data_out, HB1_ram_block2a37_clock_0, , , HB1_ram_block2a37_clock_enable_0); HB1M1898Q = HB1_ram_block2a37_PORT_A_data_out_reg[7]; --HB1_ram_block2a38 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38 = HB1_ram_block2a38_PORT_A_data_out_reg[0]; --HB1M1942Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT1 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1942Q = HB1_ram_block2a38_PORT_A_data_out_reg[1]; --HB1M1943Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT2 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1943Q = HB1_ram_block2a38_PORT_A_data_out_reg[2]; --HB1M1944Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT3 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1944Q = HB1_ram_block2a38_PORT_A_data_out_reg[3]; --HB1M1945Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT4 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1945Q = HB1_ram_block2a38_PORT_A_data_out_reg[4]; --HB1M1946Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT5 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1946Q = HB1_ram_block2a38_PORT_A_data_out_reg[5]; --HB1M1947Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT6 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1947Q = HB1_ram_block2a38_PORT_A_data_out_reg[6]; --HB1M1948Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT7 HB1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a38_PORT_A_data_in_reg = DFFE(HB1_ram_block2a38_PORT_A_data_in, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_data_in = ~GND; HB1_ram_block2a38_PORT_B_data_in_reg = DFFE(HB1_ram_block2a38_PORT_B_data_in, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a38_PORT_A_address_reg = DFFE(HB1_ram_block2a38_PORT_A_address, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a38_PORT_B_address_reg = DFFE(HB1_ram_block2a38_PORT_B_address, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_PORT_A_write_enable = GND; HB1_ram_block2a38_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_A_write_enable, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1_ram_block2a38_PORT_B_write_enable = GND; HB1_ram_block2a38_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a38_PORT_B_write_enable, HB1_ram_block2a38_clock_1, , , HB1_ram_block2a38_clock_enable_1); HB1_ram_block2a38_clock_0 = S2__clk0; HB1_ram_block2a38_clock_1 = GND; HB1_ram_block2a38_clock_enable_0 = JB3_w_anode3292w[3]; HB1_ram_block2a38_clock_enable_1 = GND; HB1_ram_block2a38_PORT_A_data_out = MEMORY(HB1_ram_block2a38_PORT_A_data_in_reg, HB1_ram_block2a38_PORT_B_data_in_reg, HB1_ram_block2a38_PORT_A_address_reg, HB1_ram_block2a38_PORT_B_address_reg, HB1_ram_block2a38_PORT_A_write_enable_reg, HB1_ram_block2a38_PORT_B_write_enable_reg, , , HB1_ram_block2a38_clock_0, HB1_ram_block2a38_clock_1, HB1_ram_block2a38_clock_enable_0, HB1_ram_block2a38_clock_enable_1, , ); HB1_ram_block2a38_PORT_A_data_out_reg = DFFE(HB1_ram_block2a38_PORT_A_data_out, HB1_ram_block2a38_clock_0, , , HB1_ram_block2a38_clock_enable_0); HB1M1948Q = HB1_ram_block2a38_PORT_A_data_out_reg[7]; --HB1_ram_block2a36 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36 = HB1_ram_block2a36_PORT_A_data_out_reg[0]; --HB1M1842Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT1 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1842Q = HB1_ram_block2a36_PORT_A_data_out_reg[1]; --HB1M1843Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT2 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1843Q = HB1_ram_block2a36_PORT_A_data_out_reg[2]; --HB1M1844Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT3 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1844Q = HB1_ram_block2a36_PORT_A_data_out_reg[3]; --HB1M1845Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT4 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1845Q = HB1_ram_block2a36_PORT_A_data_out_reg[4]; --HB1M1846Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT5 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1846Q = HB1_ram_block2a36_PORT_A_data_out_reg[5]; --HB1M1847Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT6 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1847Q = HB1_ram_block2a36_PORT_A_data_out_reg[6]; --HB1M1848Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT7 HB1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a36_PORT_A_data_in_reg = DFFE(HB1_ram_block2a36_PORT_A_data_in, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_data_in = ~GND; HB1_ram_block2a36_PORT_B_data_in_reg = DFFE(HB1_ram_block2a36_PORT_B_data_in, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a36_PORT_A_address_reg = DFFE(HB1_ram_block2a36_PORT_A_address, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a36_PORT_B_address_reg = DFFE(HB1_ram_block2a36_PORT_B_address, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_PORT_A_write_enable = GND; HB1_ram_block2a36_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_A_write_enable, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1_ram_block2a36_PORT_B_write_enable = GND; HB1_ram_block2a36_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a36_PORT_B_write_enable, HB1_ram_block2a36_clock_1, , , HB1_ram_block2a36_clock_enable_1); HB1_ram_block2a36_clock_0 = S2__clk0; HB1_ram_block2a36_clock_1 = GND; HB1_ram_block2a36_clock_enable_0 = JB3_w_anode3272w[3]; HB1_ram_block2a36_clock_enable_1 = GND; HB1_ram_block2a36_PORT_A_data_out = MEMORY(HB1_ram_block2a36_PORT_A_data_in_reg, HB1_ram_block2a36_PORT_B_data_in_reg, HB1_ram_block2a36_PORT_A_address_reg, HB1_ram_block2a36_PORT_B_address_reg, HB1_ram_block2a36_PORT_A_write_enable_reg, HB1_ram_block2a36_PORT_B_write_enable_reg, , , HB1_ram_block2a36_clock_0, HB1_ram_block2a36_clock_1, HB1_ram_block2a36_clock_enable_0, HB1_ram_block2a36_clock_enable_1, , ); HB1_ram_block2a36_PORT_A_data_out_reg = DFFE(HB1_ram_block2a36_PORT_A_data_out, HB1_ram_block2a36_clock_0, , , HB1_ram_block2a36_clock_enable_0); HB1M1848Q = HB1_ram_block2a36_PORT_A_data_out_reg[7]; --KB1L226 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~44 KB1L226 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1946Q # !HB1_address_reg_a[7] & (HB1M1846Q)); --HB1_ram_block2a39 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39 = HB1_ram_block2a39_PORT_A_data_out_reg[0]; --HB1M1992Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT1 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1992Q = HB1_ram_block2a39_PORT_A_data_out_reg[1]; --HB1M1993Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT2 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1993Q = HB1_ram_block2a39_PORT_A_data_out_reg[2]; --HB1M1994Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT3 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1994Q = HB1_ram_block2a39_PORT_A_data_out_reg[3]; --HB1M1995Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT4 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1995Q = HB1_ram_block2a39_PORT_A_data_out_reg[4]; --HB1M1996Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT5 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1996Q = HB1_ram_block2a39_PORT_A_data_out_reg[5]; --HB1M1997Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT6 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1997Q = HB1_ram_block2a39_PORT_A_data_out_reg[6]; --HB1M1998Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT7 HB1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a39_PORT_A_data_in_reg = DFFE(HB1_ram_block2a39_PORT_A_data_in, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_data_in = ~GND; HB1_ram_block2a39_PORT_B_data_in_reg = DFFE(HB1_ram_block2a39_PORT_B_data_in, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a39_PORT_A_address_reg = DFFE(HB1_ram_block2a39_PORT_A_address, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a39_PORT_B_address_reg = DFFE(HB1_ram_block2a39_PORT_B_address, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_PORT_A_write_enable = GND; HB1_ram_block2a39_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_A_write_enable, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1_ram_block2a39_PORT_B_write_enable = GND; HB1_ram_block2a39_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a39_PORT_B_write_enable, HB1_ram_block2a39_clock_1, , , HB1_ram_block2a39_clock_enable_1); HB1_ram_block2a39_clock_0 = S2__clk0; HB1_ram_block2a39_clock_1 = GND; HB1_ram_block2a39_clock_enable_0 = JB3_w_anode3302w[3]; HB1_ram_block2a39_clock_enable_1 = GND; HB1_ram_block2a39_PORT_A_data_out = MEMORY(HB1_ram_block2a39_PORT_A_data_in_reg, HB1_ram_block2a39_PORT_B_data_in_reg, HB1_ram_block2a39_PORT_A_address_reg, HB1_ram_block2a39_PORT_B_address_reg, HB1_ram_block2a39_PORT_A_write_enable_reg, HB1_ram_block2a39_PORT_B_write_enable_reg, , , HB1_ram_block2a39_clock_0, HB1_ram_block2a39_clock_1, HB1_ram_block2a39_clock_enable_0, HB1_ram_block2a39_clock_enable_1, , ); HB1_ram_block2a39_PORT_A_data_out_reg = DFFE(HB1_ram_block2a39_PORT_A_data_out, HB1_ram_block2a39_clock_0, , , HB1_ram_block2a39_clock_enable_0); HB1M1998Q = HB1_ram_block2a39_PORT_A_data_out_reg[7]; --KB1L227 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~45 KB1L227 = HB1_address_reg_a[6] & (KB1L226 & (HB1M1996Q) # !KB1L226 & HB1M1896Q) # !HB1_address_reg_a[6] & (KB1L226); --HB1_ram_block2a6 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6 = HB1_ram_block2a6_PORT_A_data_out_reg[0]; --HB1M342Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT1 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M342Q = HB1_ram_block2a6_PORT_A_data_out_reg[1]; --HB1M343Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT2 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M343Q = HB1_ram_block2a6_PORT_A_data_out_reg[2]; --HB1M344Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT3 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M344Q = HB1_ram_block2a6_PORT_A_data_out_reg[3]; --HB1M345Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT4 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M345Q = HB1_ram_block2a6_PORT_A_data_out_reg[4]; --HB1M346Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT5 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M346Q = HB1_ram_block2a6_PORT_A_data_out_reg[5]; --HB1M347Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT6 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M347Q = HB1_ram_block2a6_PORT_A_data_out_reg[6]; --HB1M348Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT7 HB1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a6_PORT_A_data_in_reg = DFFE(HB1_ram_block2a6_PORT_A_data_in, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_data_in = ~GND; HB1_ram_block2a6_PORT_B_data_in_reg = DFFE(HB1_ram_block2a6_PORT_B_data_in, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a6_PORT_A_address_reg = DFFE(HB1_ram_block2a6_PORT_A_address, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a6_PORT_B_address_reg = DFFE(HB1_ram_block2a6_PORT_B_address, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_PORT_A_write_enable = GND; HB1_ram_block2a6_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_A_write_enable, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1_ram_block2a6_PORT_B_write_enable = GND; HB1_ram_block2a6_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a6_PORT_B_write_enable, HB1_ram_block2a6_clock_1, , , HB1_ram_block2a6_clock_enable_1); HB1_ram_block2a6_clock_0 = S2__clk0; HB1_ram_block2a6_clock_1 = GND; HB1_ram_block2a6_clock_enable_0 = JB3L14; HB1_ram_block2a6_clock_enable_1 = GND; HB1_ram_block2a6_PORT_A_data_out = MEMORY(HB1_ram_block2a6_PORT_A_data_in_reg, HB1_ram_block2a6_PORT_B_data_in_reg, HB1_ram_block2a6_PORT_A_address_reg, HB1_ram_block2a6_PORT_B_address_reg, HB1_ram_block2a6_PORT_A_write_enable_reg, HB1_ram_block2a6_PORT_B_write_enable_reg, , , HB1_ram_block2a6_clock_0, HB1_ram_block2a6_clock_1, HB1_ram_block2a6_clock_enable_0, HB1_ram_block2a6_clock_enable_1, , ); HB1_ram_block2a6_PORT_A_data_out_reg = DFFE(HB1_ram_block2a6_PORT_A_data_out, HB1_ram_block2a6_clock_0, , , HB1_ram_block2a6_clock_enable_0); HB1M348Q = HB1_ram_block2a6_PORT_A_data_out_reg[7]; --HB1_ram_block2a5 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5 = HB1_ram_block2a5_PORT_A_data_out_reg[0]; --HB1M292Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT1 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M292Q = HB1_ram_block2a5_PORT_A_data_out_reg[1]; --HB1M293Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT2 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M293Q = HB1_ram_block2a5_PORT_A_data_out_reg[2]; --HB1M294Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT3 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M294Q = HB1_ram_block2a5_PORT_A_data_out_reg[3]; --HB1M295Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT4 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M295Q = HB1_ram_block2a5_PORT_A_data_out_reg[4]; --HB1M296Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT5 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M296Q = HB1_ram_block2a5_PORT_A_data_out_reg[5]; --HB1M297Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT6 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M297Q = HB1_ram_block2a5_PORT_A_data_out_reg[6]; --HB1M298Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT7 HB1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a5_PORT_A_data_in_reg = DFFE(HB1_ram_block2a5_PORT_A_data_in, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_data_in = ~GND; HB1_ram_block2a5_PORT_B_data_in_reg = DFFE(HB1_ram_block2a5_PORT_B_data_in, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a5_PORT_A_address_reg = DFFE(HB1_ram_block2a5_PORT_A_address, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a5_PORT_B_address_reg = DFFE(HB1_ram_block2a5_PORT_B_address, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_PORT_A_write_enable = GND; HB1_ram_block2a5_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_A_write_enable, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1_ram_block2a5_PORT_B_write_enable = GND; HB1_ram_block2a5_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a5_PORT_B_write_enable, HB1_ram_block2a5_clock_1, , , HB1_ram_block2a5_clock_enable_1); HB1_ram_block2a5_clock_0 = S2__clk0; HB1_ram_block2a5_clock_1 = GND; HB1_ram_block2a5_clock_enable_0 = JB3_w_anode2909w[3]; HB1_ram_block2a5_clock_enable_1 = GND; HB1_ram_block2a5_PORT_A_data_out = MEMORY(HB1_ram_block2a5_PORT_A_data_in_reg, HB1_ram_block2a5_PORT_B_data_in_reg, HB1_ram_block2a5_PORT_A_address_reg, HB1_ram_block2a5_PORT_B_address_reg, HB1_ram_block2a5_PORT_A_write_enable_reg, HB1_ram_block2a5_PORT_B_write_enable_reg, , , HB1_ram_block2a5_clock_0, HB1_ram_block2a5_clock_1, HB1_ram_block2a5_clock_enable_0, HB1_ram_block2a5_clock_enable_1, , ); HB1_ram_block2a5_PORT_A_data_out_reg = DFFE(HB1_ram_block2a5_PORT_A_data_out, HB1_ram_block2a5_clock_0, , , HB1_ram_block2a5_clock_enable_0); HB1M298Q = HB1_ram_block2a5_PORT_A_data_out_reg[7]; --HB1_ram_block2a4 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4 = HB1_ram_block2a4_PORT_A_data_out_reg[0]; --HB1M242Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT1 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M242Q = HB1_ram_block2a4_PORT_A_data_out_reg[1]; --HB1M243Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT2 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M243Q = HB1_ram_block2a4_PORT_A_data_out_reg[2]; --HB1M244Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT3 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M244Q = HB1_ram_block2a4_PORT_A_data_out_reg[3]; --HB1M245Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT4 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M245Q = HB1_ram_block2a4_PORT_A_data_out_reg[4]; --HB1M246Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT5 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M246Q = HB1_ram_block2a4_PORT_A_data_out_reg[5]; --HB1M247Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT6 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M247Q = HB1_ram_block2a4_PORT_A_data_out_reg[6]; --HB1M248Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT7 HB1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a4_PORT_A_data_in_reg = DFFE(HB1_ram_block2a4_PORT_A_data_in, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_data_in = ~GND; HB1_ram_block2a4_PORT_B_data_in_reg = DFFE(HB1_ram_block2a4_PORT_B_data_in, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a4_PORT_A_address_reg = DFFE(HB1_ram_block2a4_PORT_A_address, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a4_PORT_B_address_reg = DFFE(HB1_ram_block2a4_PORT_B_address, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_PORT_A_write_enable = GND; HB1_ram_block2a4_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_A_write_enable, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1_ram_block2a4_PORT_B_write_enable = GND; HB1_ram_block2a4_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a4_PORT_B_write_enable, HB1_ram_block2a4_clock_1, , , HB1_ram_block2a4_clock_enable_1); HB1_ram_block2a4_clock_0 = S2__clk0; HB1_ram_block2a4_clock_1 = GND; HB1_ram_block2a4_clock_enable_0 = JB3L10; HB1_ram_block2a4_clock_enable_1 = GND; HB1_ram_block2a4_PORT_A_data_out = MEMORY(HB1_ram_block2a4_PORT_A_data_in_reg, HB1_ram_block2a4_PORT_B_data_in_reg, HB1_ram_block2a4_PORT_A_address_reg, HB1_ram_block2a4_PORT_B_address_reg, HB1_ram_block2a4_PORT_A_write_enable_reg, HB1_ram_block2a4_PORT_B_write_enable_reg, , , HB1_ram_block2a4_clock_0, HB1_ram_block2a4_clock_1, HB1_ram_block2a4_clock_enable_0, HB1_ram_block2a4_clock_enable_1, , ); HB1_ram_block2a4_PORT_A_data_out_reg = DFFE(HB1_ram_block2a4_PORT_A_data_out, HB1_ram_block2a4_clock_0, , , HB1_ram_block2a4_clock_enable_0); HB1M248Q = HB1_ram_block2a4_PORT_A_data_out_reg[7]; --KB1L214 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~44 KB1L214 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M296Q # !HB1_address_reg_a[6] & (HB1M246Q)); --HB1_ram_block2a7 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7 = HB1_ram_block2a7_PORT_A_data_out_reg[0]; --HB1M392Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT1 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M392Q = HB1_ram_block2a7_PORT_A_data_out_reg[1]; --HB1M393Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT2 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M393Q = HB1_ram_block2a7_PORT_A_data_out_reg[2]; --HB1M394Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT3 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M394Q = HB1_ram_block2a7_PORT_A_data_out_reg[3]; --HB1M395Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT4 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M395Q = HB1_ram_block2a7_PORT_A_data_out_reg[4]; --HB1M396Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT5 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M396Q = HB1_ram_block2a7_PORT_A_data_out_reg[5]; --HB1M397Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT6 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M397Q = HB1_ram_block2a7_PORT_A_data_out_reg[6]; --HB1M398Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT7 HB1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a7_PORT_A_data_in_reg = DFFE(HB1_ram_block2a7_PORT_A_data_in, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_data_in = ~GND; HB1_ram_block2a7_PORT_B_data_in_reg = DFFE(HB1_ram_block2a7_PORT_B_data_in, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a7_PORT_A_address_reg = DFFE(HB1_ram_block2a7_PORT_A_address, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a7_PORT_B_address_reg = DFFE(HB1_ram_block2a7_PORT_B_address, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_PORT_A_write_enable = GND; HB1_ram_block2a7_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_A_write_enable, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1_ram_block2a7_PORT_B_write_enable = GND; HB1_ram_block2a7_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a7_PORT_B_write_enable, HB1_ram_block2a7_clock_1, , , HB1_ram_block2a7_clock_enable_1); HB1_ram_block2a7_clock_0 = S2__clk0; HB1_ram_block2a7_clock_1 = GND; HB1_ram_block2a7_clock_enable_0 = JB3_w_anode2929w[3]; HB1_ram_block2a7_clock_enable_1 = GND; HB1_ram_block2a7_PORT_A_data_out = MEMORY(HB1_ram_block2a7_PORT_A_data_in_reg, HB1_ram_block2a7_PORT_B_data_in_reg, HB1_ram_block2a7_PORT_A_address_reg, HB1_ram_block2a7_PORT_B_address_reg, HB1_ram_block2a7_PORT_A_write_enable_reg, HB1_ram_block2a7_PORT_B_write_enable_reg, , , HB1_ram_block2a7_clock_0, HB1_ram_block2a7_clock_1, HB1_ram_block2a7_clock_enable_0, HB1_ram_block2a7_clock_enable_1, , ); HB1_ram_block2a7_PORT_A_data_out_reg = DFFE(HB1_ram_block2a7_PORT_A_data_out, HB1_ram_block2a7_clock_0, , , HB1_ram_block2a7_clock_enable_0); HB1M398Q = HB1_ram_block2a7_PORT_A_data_out_reg[7]; --KB1L215 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~45 KB1L215 = HB1_address_reg_a[7] & (KB1L214 & (HB1M396Q) # !KB1L214 & HB1M346Q) # !HB1_address_reg_a[7] & (KB1L214); --KB1L234 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~575 KB1L234 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L227 # !HB1_address_reg_a[11] & (KB1L215)); --KB1L235 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~576 KB1L235 = KB1L147 # KB1L232 & (KB1L233 # KB1L234); --KB1L236 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~577 KB1L236 = !HB1_address_reg_a[9] & !HB1_address_reg_a[10] & !HB1_address_reg_a[8]; --HB1_ram_block2a33 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33 = HB1_ram_block2a33_PORT_A_data_out_reg[0]; --HB1M1692Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT1 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1692Q = HB1_ram_block2a33_PORT_A_data_out_reg[1]; --HB1M1693Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT2 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1693Q = HB1_ram_block2a33_PORT_A_data_out_reg[2]; --HB1M1694Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT3 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1694Q = HB1_ram_block2a33_PORT_A_data_out_reg[3]; --HB1M1695Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT4 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1695Q = HB1_ram_block2a33_PORT_A_data_out_reg[4]; --HB1M1696Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT5 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1696Q = HB1_ram_block2a33_PORT_A_data_out_reg[5]; --HB1M1697Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT6 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1697Q = HB1_ram_block2a33_PORT_A_data_out_reg[6]; --HB1M1698Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT7 HB1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a33_PORT_A_data_in_reg = DFFE(HB1_ram_block2a33_PORT_A_data_in, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_data_in = ~GND; HB1_ram_block2a33_PORT_B_data_in_reg = DFFE(HB1_ram_block2a33_PORT_B_data_in, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a33_PORT_A_address_reg = DFFE(HB1_ram_block2a33_PORT_A_address, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a33_PORT_B_address_reg = DFFE(HB1_ram_block2a33_PORT_B_address, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_PORT_A_write_enable = GND; HB1_ram_block2a33_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_A_write_enable, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1_ram_block2a33_PORT_B_write_enable = GND; HB1_ram_block2a33_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a33_PORT_B_write_enable, HB1_ram_block2a33_clock_1, , , HB1_ram_block2a33_clock_enable_1); HB1_ram_block2a33_clock_0 = S2__clk0; HB1_ram_block2a33_clock_1 = GND; HB1_ram_block2a33_clock_enable_0 = JB3_w_anode3242w[3]; HB1_ram_block2a33_clock_enable_1 = GND; HB1_ram_block2a33_PORT_A_data_out = MEMORY(HB1_ram_block2a33_PORT_A_data_in_reg, HB1_ram_block2a33_PORT_B_data_in_reg, HB1_ram_block2a33_PORT_A_address_reg, HB1_ram_block2a33_PORT_B_address_reg, HB1_ram_block2a33_PORT_A_write_enable_reg, HB1_ram_block2a33_PORT_B_write_enable_reg, , , HB1_ram_block2a33_clock_0, HB1_ram_block2a33_clock_1, HB1_ram_block2a33_clock_enable_0, HB1_ram_block2a33_clock_enable_1, , ); HB1_ram_block2a33_PORT_A_data_out_reg = DFFE(HB1_ram_block2a33_PORT_A_data_out, HB1_ram_block2a33_clock_0, , , HB1_ram_block2a33_clock_enable_0); HB1M1698Q = HB1_ram_block2a33_PORT_A_data_out_reg[7]; --HB1_ram_block2a34 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34 = HB1_ram_block2a34_PORT_A_data_out_reg[0]; --HB1M1742Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT1 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1742Q = HB1_ram_block2a34_PORT_A_data_out_reg[1]; --HB1M1743Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT2 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1743Q = HB1_ram_block2a34_PORT_A_data_out_reg[2]; --HB1M1744Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT3 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1744Q = HB1_ram_block2a34_PORT_A_data_out_reg[3]; --HB1M1745Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT4 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1745Q = HB1_ram_block2a34_PORT_A_data_out_reg[4]; --HB1M1746Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT5 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1746Q = HB1_ram_block2a34_PORT_A_data_out_reg[5]; --HB1M1747Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT6 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1747Q = HB1_ram_block2a34_PORT_A_data_out_reg[6]; --HB1M1748Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT7 HB1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a34_PORT_A_data_in_reg = DFFE(HB1_ram_block2a34_PORT_A_data_in, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_data_in = ~GND; HB1_ram_block2a34_PORT_B_data_in_reg = DFFE(HB1_ram_block2a34_PORT_B_data_in, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a34_PORT_A_address_reg = DFFE(HB1_ram_block2a34_PORT_A_address, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a34_PORT_B_address_reg = DFFE(HB1_ram_block2a34_PORT_B_address, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_PORT_A_write_enable = GND; HB1_ram_block2a34_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_A_write_enable, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1_ram_block2a34_PORT_B_write_enable = GND; HB1_ram_block2a34_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a34_PORT_B_write_enable, HB1_ram_block2a34_clock_1, , , HB1_ram_block2a34_clock_enable_1); HB1_ram_block2a34_clock_0 = S2__clk0; HB1_ram_block2a34_clock_1 = GND; HB1_ram_block2a34_clock_enable_0 = JB3_w_anode3252w[3]; HB1_ram_block2a34_clock_enable_1 = GND; HB1_ram_block2a34_PORT_A_data_out = MEMORY(HB1_ram_block2a34_PORT_A_data_in_reg, HB1_ram_block2a34_PORT_B_data_in_reg, HB1_ram_block2a34_PORT_A_address_reg, HB1_ram_block2a34_PORT_B_address_reg, HB1_ram_block2a34_PORT_A_write_enable_reg, HB1_ram_block2a34_PORT_B_write_enable_reg, , , HB1_ram_block2a34_clock_0, HB1_ram_block2a34_clock_1, HB1_ram_block2a34_clock_enable_0, HB1_ram_block2a34_clock_enable_1, , ); HB1_ram_block2a34_PORT_A_data_out_reg = DFFE(HB1_ram_block2a34_PORT_A_data_out, HB1_ram_block2a34_clock_0, , , HB1_ram_block2a34_clock_enable_0); HB1M1748Q = HB1_ram_block2a34_PORT_A_data_out_reg[7]; --HB1_ram_block2a32 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32 = HB1_ram_block2a32_PORT_A_data_out_reg[0]; --HB1M1642Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT1 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1642Q = HB1_ram_block2a32_PORT_A_data_out_reg[1]; --HB1M1643Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT2 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1643Q = HB1_ram_block2a32_PORT_A_data_out_reg[2]; --HB1M1644Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT3 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1644Q = HB1_ram_block2a32_PORT_A_data_out_reg[3]; --HB1M1645Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT4 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1645Q = HB1_ram_block2a32_PORT_A_data_out_reg[4]; --HB1M1646Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT5 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1646Q = HB1_ram_block2a32_PORT_A_data_out_reg[5]; --HB1M1647Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT6 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1647Q = HB1_ram_block2a32_PORT_A_data_out_reg[6]; --HB1M1648Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT7 HB1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a32_PORT_A_data_in_reg = DFFE(HB1_ram_block2a32_PORT_A_data_in, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_data_in = ~GND; HB1_ram_block2a32_PORT_B_data_in_reg = DFFE(HB1_ram_block2a32_PORT_B_data_in, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a32_PORT_A_address_reg = DFFE(HB1_ram_block2a32_PORT_A_address, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a32_PORT_B_address_reg = DFFE(HB1_ram_block2a32_PORT_B_address, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_PORT_A_write_enable = GND; HB1_ram_block2a32_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_A_write_enable, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1_ram_block2a32_PORT_B_write_enable = GND; HB1_ram_block2a32_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a32_PORT_B_write_enable, HB1_ram_block2a32_clock_1, , , HB1_ram_block2a32_clock_enable_1); HB1_ram_block2a32_clock_0 = S2__clk0; HB1_ram_block2a32_clock_1 = GND; HB1_ram_block2a32_clock_enable_0 = JB3_w_anode3231w[3]; HB1_ram_block2a32_clock_enable_1 = GND; HB1_ram_block2a32_PORT_A_data_out = MEMORY(HB1_ram_block2a32_PORT_A_data_in_reg, HB1_ram_block2a32_PORT_B_data_in_reg, HB1_ram_block2a32_PORT_A_address_reg, HB1_ram_block2a32_PORT_B_address_reg, HB1_ram_block2a32_PORT_A_write_enable_reg, HB1_ram_block2a32_PORT_B_write_enable_reg, , , HB1_ram_block2a32_clock_0, HB1_ram_block2a32_clock_1, HB1_ram_block2a32_clock_enable_0, HB1_ram_block2a32_clock_enable_1, , ); HB1_ram_block2a32_PORT_A_data_out_reg = DFFE(HB1_ram_block2a32_PORT_A_data_out, HB1_ram_block2a32_clock_0, , , HB1_ram_block2a32_clock_enable_0); HB1M1648Q = HB1_ram_block2a32_PORT_A_data_out_reg[7]; --KB1L230 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~281 KB1L230 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1746Q # !HB1_address_reg_a[7] & (HB1M1646Q)); --HB1_ram_block2a35 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35 = HB1_ram_block2a35_PORT_A_data_out_reg[0]; --HB1M1792Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT1 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1792Q = HB1_ram_block2a35_PORT_A_data_out_reg[1]; --HB1M1793Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT2 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1793Q = HB1_ram_block2a35_PORT_A_data_out_reg[2]; --HB1M1794Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT3 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1794Q = HB1_ram_block2a35_PORT_A_data_out_reg[3]; --HB1M1795Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT4 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1795Q = HB1_ram_block2a35_PORT_A_data_out_reg[4]; --HB1M1796Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT5 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1796Q = HB1_ram_block2a35_PORT_A_data_out_reg[5]; --HB1M1797Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT6 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1797Q = HB1_ram_block2a35_PORT_A_data_out_reg[6]; --HB1M1798Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT7 HB1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a35_PORT_A_data_in_reg = DFFE(HB1_ram_block2a35_PORT_A_data_in, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_data_in = ~GND; HB1_ram_block2a35_PORT_B_data_in_reg = DFFE(HB1_ram_block2a35_PORT_B_data_in, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a35_PORT_A_address_reg = DFFE(HB1_ram_block2a35_PORT_A_address, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a35_PORT_B_address_reg = DFFE(HB1_ram_block2a35_PORT_B_address, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_PORT_A_write_enable = GND; HB1_ram_block2a35_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_A_write_enable, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1_ram_block2a35_PORT_B_write_enable = GND; HB1_ram_block2a35_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a35_PORT_B_write_enable, HB1_ram_block2a35_clock_1, , , HB1_ram_block2a35_clock_enable_1); HB1_ram_block2a35_clock_0 = S2__clk0; HB1_ram_block2a35_clock_1 = GND; HB1_ram_block2a35_clock_enable_0 = JB3_w_anode3262w[3]; HB1_ram_block2a35_clock_enable_1 = GND; HB1_ram_block2a35_PORT_A_data_out = MEMORY(HB1_ram_block2a35_PORT_A_data_in_reg, HB1_ram_block2a35_PORT_B_data_in_reg, HB1_ram_block2a35_PORT_A_address_reg, HB1_ram_block2a35_PORT_B_address_reg, HB1_ram_block2a35_PORT_A_write_enable_reg, HB1_ram_block2a35_PORT_B_write_enable_reg, , , HB1_ram_block2a35_clock_0, HB1_ram_block2a35_clock_1, HB1_ram_block2a35_clock_enable_0, HB1_ram_block2a35_clock_enable_1, , ); HB1_ram_block2a35_PORT_A_data_out_reg = DFFE(HB1_ram_block2a35_PORT_A_data_out, HB1_ram_block2a35_clock_0, , , HB1_ram_block2a35_clock_enable_0); HB1M1798Q = HB1_ram_block2a35_PORT_A_data_out_reg[7]; --KB1L231 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~282 KB1L231 = HB1_address_reg_a[6] & (KB1L230 & (HB1M1796Q) # !KB1L230 & HB1M1696Q) # !HB1_address_reg_a[6] & (KB1L230); --HB1_ram_block2a2 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2 = HB1_ram_block2a2_PORT_A_data_out_reg[0]; --HB1M142Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT1 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M142Q = HB1_ram_block2a2_PORT_A_data_out_reg[1]; --HB1M143Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT2 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M143Q = HB1_ram_block2a2_PORT_A_data_out_reg[2]; --HB1M144Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT3 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M144Q = HB1_ram_block2a2_PORT_A_data_out_reg[3]; --HB1M145Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT4 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M145Q = HB1_ram_block2a2_PORT_A_data_out_reg[4]; --HB1M146Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT5 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M146Q = HB1_ram_block2a2_PORT_A_data_out_reg[5]; --HB1M147Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT6 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M147Q = HB1_ram_block2a2_PORT_A_data_out_reg[6]; --HB1M148Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT7 HB1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a2_PORT_A_data_in_reg = DFFE(HB1_ram_block2a2_PORT_A_data_in, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_data_in = ~GND; HB1_ram_block2a2_PORT_B_data_in_reg = DFFE(HB1_ram_block2a2_PORT_B_data_in, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a2_PORT_A_address_reg = DFFE(HB1_ram_block2a2_PORT_A_address, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a2_PORT_B_address_reg = DFFE(HB1_ram_block2a2_PORT_B_address, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_PORT_A_write_enable = GND; HB1_ram_block2a2_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_A_write_enable, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1_ram_block2a2_PORT_B_write_enable = GND; HB1_ram_block2a2_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a2_PORT_B_write_enable, HB1_ram_block2a2_clock_1, , , HB1_ram_block2a2_clock_enable_1); HB1_ram_block2a2_clock_0 = S2__clk0; HB1_ram_block2a2_clock_1 = GND; HB1_ram_block2a2_clock_enable_0 = JB3L6; HB1_ram_block2a2_clock_enable_1 = GND; HB1_ram_block2a2_PORT_A_data_out = MEMORY(HB1_ram_block2a2_PORT_A_data_in_reg, HB1_ram_block2a2_PORT_B_data_in_reg, HB1_ram_block2a2_PORT_A_address_reg, HB1_ram_block2a2_PORT_B_address_reg, HB1_ram_block2a2_PORT_A_write_enable_reg, HB1_ram_block2a2_PORT_B_write_enable_reg, , , HB1_ram_block2a2_clock_0, HB1_ram_block2a2_clock_1, HB1_ram_block2a2_clock_enable_0, HB1_ram_block2a2_clock_enable_1, , ); HB1_ram_block2a2_PORT_A_data_out_reg = DFFE(HB1_ram_block2a2_PORT_A_data_out, HB1_ram_block2a2_clock_0, , , HB1_ram_block2a2_clock_enable_0); HB1M148Q = HB1_ram_block2a2_PORT_A_data_out_reg[7]; --HB1_ram_block2a1 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1 = HB1_ram_block2a1_PORT_A_data_out_reg[0]; --HB1M92Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT1 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M92Q = HB1_ram_block2a1_PORT_A_data_out_reg[1]; --HB1M93Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT2 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M93Q = HB1_ram_block2a1_PORT_A_data_out_reg[2]; --HB1M94Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT3 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M94Q = HB1_ram_block2a1_PORT_A_data_out_reg[3]; --HB1M95Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT4 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M95Q = HB1_ram_block2a1_PORT_A_data_out_reg[4]; --HB1M96Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT5 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M96Q = HB1_ram_block2a1_PORT_A_data_out_reg[5]; --HB1M97Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT6 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M97Q = HB1_ram_block2a1_PORT_A_data_out_reg[6]; --HB1M98Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT7 HB1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a1_PORT_A_data_in_reg = DFFE(HB1_ram_block2a1_PORT_A_data_in, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_data_in = ~GND; HB1_ram_block2a1_PORT_B_data_in_reg = DFFE(HB1_ram_block2a1_PORT_B_data_in, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a1_PORT_A_address_reg = DFFE(HB1_ram_block2a1_PORT_A_address, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a1_PORT_B_address_reg = DFFE(HB1_ram_block2a1_PORT_B_address, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_PORT_A_write_enable = GND; HB1_ram_block2a1_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_A_write_enable, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1_ram_block2a1_PORT_B_write_enable = GND; HB1_ram_block2a1_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a1_PORT_B_write_enable, HB1_ram_block2a1_clock_1, , , HB1_ram_block2a1_clock_enable_1); HB1_ram_block2a1_clock_0 = S2__clk0; HB1_ram_block2a1_clock_1 = GND; HB1_ram_block2a1_clock_enable_0 = JB3_w_anode2869w[3]; HB1_ram_block2a1_clock_enable_1 = GND; HB1_ram_block2a1_PORT_A_data_out = MEMORY(HB1_ram_block2a1_PORT_A_data_in_reg, HB1_ram_block2a1_PORT_B_data_in_reg, HB1_ram_block2a1_PORT_A_address_reg, HB1_ram_block2a1_PORT_B_address_reg, HB1_ram_block2a1_PORT_A_write_enable_reg, HB1_ram_block2a1_PORT_B_write_enable_reg, , , HB1_ram_block2a1_clock_0, HB1_ram_block2a1_clock_1, HB1_ram_block2a1_clock_enable_0, HB1_ram_block2a1_clock_enable_1, , ); HB1_ram_block2a1_PORT_A_data_out_reg = DFFE(HB1_ram_block2a1_PORT_A_data_out, HB1_ram_block2a1_clock_0, , , HB1_ram_block2a1_clock_enable_0); HB1M98Q = HB1_ram_block2a1_PORT_A_data_out_reg[7]; --HB1_ram_block2a0 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0 = HB1_ram_block2a0_PORT_A_data_out_reg[0]; --HB1M42Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT1 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M42Q = HB1_ram_block2a0_PORT_A_data_out_reg[1]; --HB1M43Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT2 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M43Q = HB1_ram_block2a0_PORT_A_data_out_reg[2]; --HB1M44Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT3 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M44Q = HB1_ram_block2a0_PORT_A_data_out_reg[3]; --HB1M45Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT4 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M45Q = HB1_ram_block2a0_PORT_A_data_out_reg[4]; --HB1M46Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT5 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M46Q = HB1_ram_block2a0_PORT_A_data_out_reg[5]; --HB1M47Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT6 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M47Q = HB1_ram_block2a0_PORT_A_data_out_reg[6]; --HB1M48Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT7 HB1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a0_PORT_A_data_in_reg = DFFE(HB1_ram_block2a0_PORT_A_data_in, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_data_in = ~GND; HB1_ram_block2a0_PORT_B_data_in_reg = DFFE(HB1_ram_block2a0_PORT_B_data_in, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a0_PORT_A_address_reg = DFFE(HB1_ram_block2a0_PORT_A_address, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a0_PORT_B_address_reg = DFFE(HB1_ram_block2a0_PORT_B_address, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_PORT_A_write_enable = GND; HB1_ram_block2a0_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_A_write_enable, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1_ram_block2a0_PORT_B_write_enable = GND; HB1_ram_block2a0_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a0_PORT_B_write_enable, HB1_ram_block2a0_clock_1, , , ); HB1_ram_block2a0_clock_0 = S2__clk0; HB1_ram_block2a0_clock_1 = GND; HB1_ram_block2a0_clock_enable_0 = JB3_w_anode2852w[3]; HB1_ram_block2a0_PORT_A_data_out = MEMORY(HB1_ram_block2a0_PORT_A_data_in_reg, HB1_ram_block2a0_PORT_B_data_in_reg, HB1_ram_block2a0_PORT_A_address_reg, HB1_ram_block2a0_PORT_B_address_reg, HB1_ram_block2a0_PORT_A_write_enable_reg, HB1_ram_block2a0_PORT_B_write_enable_reg, , , HB1_ram_block2a0_clock_0, HB1_ram_block2a0_clock_1, HB1_ram_block2a0_clock_enable_0, , , ); HB1_ram_block2a0_PORT_A_data_out_reg = DFFE(HB1_ram_block2a0_PORT_A_data_out, HB1_ram_block2a0_clock_0, , , HB1_ram_block2a0_clock_enable_0); HB1M48Q = HB1_ram_block2a0_PORT_A_data_out_reg[7]; --KB1L218 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~281 KB1L218 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M96Q # !HB1_address_reg_a[6] & (HB1M46Q)); --HB1_ram_block2a3 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3 = HB1_ram_block2a3_PORT_A_data_out_reg[0]; --HB1M192Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT1 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M192Q = HB1_ram_block2a3_PORT_A_data_out_reg[1]; --HB1M193Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT2 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M193Q = HB1_ram_block2a3_PORT_A_data_out_reg[2]; --HB1M194Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT3 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M194Q = HB1_ram_block2a3_PORT_A_data_out_reg[3]; --HB1M195Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT4 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M195Q = HB1_ram_block2a3_PORT_A_data_out_reg[4]; --HB1M196Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT5 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M196Q = HB1_ram_block2a3_PORT_A_data_out_reg[5]; --HB1M197Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT6 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M197Q = HB1_ram_block2a3_PORT_A_data_out_reg[6]; --HB1M198Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT7 HB1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a3_PORT_A_data_in_reg = DFFE(HB1_ram_block2a3_PORT_A_data_in, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_data_in = ~GND; HB1_ram_block2a3_PORT_B_data_in_reg = DFFE(HB1_ram_block2a3_PORT_B_data_in, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a3_PORT_A_address_reg = DFFE(HB1_ram_block2a3_PORT_A_address, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a3_PORT_B_address_reg = DFFE(HB1_ram_block2a3_PORT_B_address, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_PORT_A_write_enable = GND; HB1_ram_block2a3_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_A_write_enable, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1_ram_block2a3_PORT_B_write_enable = GND; HB1_ram_block2a3_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a3_PORT_B_write_enable, HB1_ram_block2a3_clock_1, , , HB1_ram_block2a3_clock_enable_1); HB1_ram_block2a3_clock_0 = S2__clk0; HB1_ram_block2a3_clock_1 = GND; HB1_ram_block2a3_clock_enable_0 = JB3_w_anode2889w[3]; HB1_ram_block2a3_clock_enable_1 = GND; HB1_ram_block2a3_PORT_A_data_out = MEMORY(HB1_ram_block2a3_PORT_A_data_in_reg, HB1_ram_block2a3_PORT_B_data_in_reg, HB1_ram_block2a3_PORT_A_address_reg, HB1_ram_block2a3_PORT_B_address_reg, HB1_ram_block2a3_PORT_A_write_enable_reg, HB1_ram_block2a3_PORT_B_write_enable_reg, , , HB1_ram_block2a3_clock_0, HB1_ram_block2a3_clock_1, HB1_ram_block2a3_clock_enable_0, HB1_ram_block2a3_clock_enable_1, , ); HB1_ram_block2a3_PORT_A_data_out_reg = DFFE(HB1_ram_block2a3_PORT_A_data_out, HB1_ram_block2a3_clock_0, , , HB1_ram_block2a3_clock_enable_0); HB1M198Q = HB1_ram_block2a3_PORT_A_data_out_reg[7]; --KB1L219 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~282 KB1L219 = HB1_address_reg_a[7] & (KB1L218 & (HB1M196Q) # !KB1L218 & HB1M146Q) # !HB1_address_reg_a[7] & (KB1L218); --KB1L237 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~578 KB1L237 = KB1L236 & (HB1_address_reg_a[11] & KB1L231 # !HB1_address_reg_a[11] & (KB1L219)); --HB1_ram_block2a41 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41 = HB1_ram_block2a41_PORT_A_data_out_reg[0]; --HB1M2092Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT1 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2092Q = HB1_ram_block2a41_PORT_A_data_out_reg[1]; --HB1M2093Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT2 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2093Q = HB1_ram_block2a41_PORT_A_data_out_reg[2]; --HB1M2094Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT3 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2094Q = HB1_ram_block2a41_PORT_A_data_out_reg[3]; --HB1M2095Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT4 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2095Q = HB1_ram_block2a41_PORT_A_data_out_reg[4]; --HB1M2096Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT5 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2096Q = HB1_ram_block2a41_PORT_A_data_out_reg[5]; --HB1M2097Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT6 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2097Q = HB1_ram_block2a41_PORT_A_data_out_reg[6]; --HB1M2098Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT7 HB1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a41_PORT_A_data_in_reg = DFFE(HB1_ram_block2a41_PORT_A_data_in, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_data_in = ~GND; HB1_ram_block2a41_PORT_B_data_in_reg = DFFE(HB1_ram_block2a41_PORT_B_data_in, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a41_PORT_A_address_reg = DFFE(HB1_ram_block2a41_PORT_A_address, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a41_PORT_B_address_reg = DFFE(HB1_ram_block2a41_PORT_B_address, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_PORT_A_write_enable = GND; HB1_ram_block2a41_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_A_write_enable, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1_ram_block2a41_PORT_B_write_enable = GND; HB1_ram_block2a41_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a41_PORT_B_write_enable, HB1_ram_block2a41_clock_1, , , HB1_ram_block2a41_clock_enable_1); HB1_ram_block2a41_clock_0 = S2__clk0; HB1_ram_block2a41_clock_1 = GND; HB1_ram_block2a41_clock_enable_0 = JB3_w_anode3335w[3]; HB1_ram_block2a41_clock_enable_1 = GND; HB1_ram_block2a41_PORT_A_data_out = MEMORY(HB1_ram_block2a41_PORT_A_data_in_reg, HB1_ram_block2a41_PORT_B_data_in_reg, HB1_ram_block2a41_PORT_A_address_reg, HB1_ram_block2a41_PORT_B_address_reg, HB1_ram_block2a41_PORT_A_write_enable_reg, HB1_ram_block2a41_PORT_B_write_enable_reg, , , HB1_ram_block2a41_clock_0, HB1_ram_block2a41_clock_1, HB1_ram_block2a41_clock_enable_0, HB1_ram_block2a41_clock_enable_1, , ); HB1_ram_block2a41_PORT_A_data_out_reg = DFFE(HB1_ram_block2a41_PORT_A_data_out, HB1_ram_block2a41_clock_0, , , HB1_ram_block2a41_clock_enable_0); HB1M2098Q = HB1_ram_block2a41_PORT_A_data_out_reg[7]; --HB1_ram_block2a40 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40 = HB1_ram_block2a40_PORT_A_data_out_reg[0]; --HB1M2042Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT1 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2042Q = HB1_ram_block2a40_PORT_A_data_out_reg[1]; --HB1M2043Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT2 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2043Q = HB1_ram_block2a40_PORT_A_data_out_reg[2]; --HB1M2044Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT3 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2044Q = HB1_ram_block2a40_PORT_A_data_out_reg[3]; --HB1M2045Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT4 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2045Q = HB1_ram_block2a40_PORT_A_data_out_reg[4]; --HB1M2046Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT5 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2046Q = HB1_ram_block2a40_PORT_A_data_out_reg[5]; --HB1M2047Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT6 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2047Q = HB1_ram_block2a40_PORT_A_data_out_reg[6]; --HB1M2048Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT7 HB1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a40_PORT_A_data_in_reg = DFFE(HB1_ram_block2a40_PORT_A_data_in, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_data_in = ~GND; HB1_ram_block2a40_PORT_B_data_in_reg = DFFE(HB1_ram_block2a40_PORT_B_data_in, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a40_PORT_A_address_reg = DFFE(HB1_ram_block2a40_PORT_A_address, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a40_PORT_B_address_reg = DFFE(HB1_ram_block2a40_PORT_B_address, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_PORT_A_write_enable = GND; HB1_ram_block2a40_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_A_write_enable, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1_ram_block2a40_PORT_B_write_enable = GND; HB1_ram_block2a40_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a40_PORT_B_write_enable, HB1_ram_block2a40_clock_1, , , HB1_ram_block2a40_clock_enable_1); HB1_ram_block2a40_clock_0 = S2__clk0; HB1_ram_block2a40_clock_1 = GND; HB1_ram_block2a40_clock_enable_0 = JB3_w_anode3324w[3]; HB1_ram_block2a40_clock_enable_1 = GND; HB1_ram_block2a40_PORT_A_data_out = MEMORY(HB1_ram_block2a40_PORT_A_data_in_reg, HB1_ram_block2a40_PORT_B_data_in_reg, HB1_ram_block2a40_PORT_A_address_reg, HB1_ram_block2a40_PORT_B_address_reg, HB1_ram_block2a40_PORT_A_write_enable_reg, HB1_ram_block2a40_PORT_B_write_enable_reg, , , HB1_ram_block2a40_clock_0, HB1_ram_block2a40_clock_1, HB1_ram_block2a40_clock_enable_0, HB1_ram_block2a40_clock_enable_1, , ); HB1_ram_block2a40_PORT_A_data_out_reg = DFFE(HB1_ram_block2a40_PORT_A_data_out, HB1_ram_block2a40_clock_0, , , HB1_ram_block2a40_clock_enable_0); HB1M2048Q = HB1_ram_block2a40_PORT_A_data_out_reg[7]; --HB1_ram_block2a43 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43 = HB1_ram_block2a43_PORT_A_data_out_reg[0]; --HB1M2192Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT1 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2192Q = HB1_ram_block2a43_PORT_A_data_out_reg[1]; --HB1M2193Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT2 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2193Q = HB1_ram_block2a43_PORT_A_data_out_reg[2]; --HB1M2194Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT3 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2194Q = HB1_ram_block2a43_PORT_A_data_out_reg[3]; --HB1M2195Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT4 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2195Q = HB1_ram_block2a43_PORT_A_data_out_reg[4]; --HB1M2196Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT5 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2196Q = HB1_ram_block2a43_PORT_A_data_out_reg[5]; --HB1M2197Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT6 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2197Q = HB1_ram_block2a43_PORT_A_data_out_reg[6]; --HB1M2198Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT7 HB1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a43_PORT_A_data_in_reg = DFFE(HB1_ram_block2a43_PORT_A_data_in, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_data_in = ~GND; HB1_ram_block2a43_PORT_B_data_in_reg = DFFE(HB1_ram_block2a43_PORT_B_data_in, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a43_PORT_A_address_reg = DFFE(HB1_ram_block2a43_PORT_A_address, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a43_PORT_B_address_reg = DFFE(HB1_ram_block2a43_PORT_B_address, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_PORT_A_write_enable = GND; HB1_ram_block2a43_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_A_write_enable, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1_ram_block2a43_PORT_B_write_enable = GND; HB1_ram_block2a43_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a43_PORT_B_write_enable, HB1_ram_block2a43_clock_1, , , HB1_ram_block2a43_clock_enable_1); HB1_ram_block2a43_clock_0 = S2__clk0; HB1_ram_block2a43_clock_1 = GND; HB1_ram_block2a43_clock_enable_0 = JB3_w_anode3355w[3]; HB1_ram_block2a43_clock_enable_1 = GND; HB1_ram_block2a43_PORT_A_data_out = MEMORY(HB1_ram_block2a43_PORT_A_data_in_reg, HB1_ram_block2a43_PORT_B_data_in_reg, HB1_ram_block2a43_PORT_A_address_reg, HB1_ram_block2a43_PORT_B_address_reg, HB1_ram_block2a43_PORT_A_write_enable_reg, HB1_ram_block2a43_PORT_B_write_enable_reg, , , HB1_ram_block2a43_clock_0, HB1_ram_block2a43_clock_1, HB1_ram_block2a43_clock_enable_0, HB1_ram_block2a43_clock_enable_1, , ); HB1_ram_block2a43_PORT_A_data_out_reg = DFFE(HB1_ram_block2a43_PORT_A_data_out, HB1_ram_block2a43_clock_0, , , HB1_ram_block2a43_clock_enable_0); HB1M2198Q = HB1_ram_block2a43_PORT_A_data_out_reg[7]; --HB1_ram_block2a42 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42 = HB1_ram_block2a42_PORT_A_data_out_reg[0]; --HB1M2142Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT1 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2142Q = HB1_ram_block2a42_PORT_A_data_out_reg[1]; --HB1M2143Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT2 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2143Q = HB1_ram_block2a42_PORT_A_data_out_reg[2]; --HB1M2144Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT3 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2144Q = HB1_ram_block2a42_PORT_A_data_out_reg[3]; --HB1M2145Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT4 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2145Q = HB1_ram_block2a42_PORT_A_data_out_reg[4]; --HB1M2146Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT5 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2146Q = HB1_ram_block2a42_PORT_A_data_out_reg[5]; --HB1M2147Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT6 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2147Q = HB1_ram_block2a42_PORT_A_data_out_reg[6]; --HB1M2148Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT7 HB1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a42_PORT_A_data_in_reg = DFFE(HB1_ram_block2a42_PORT_A_data_in, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_data_in = ~GND; HB1_ram_block2a42_PORT_B_data_in_reg = DFFE(HB1_ram_block2a42_PORT_B_data_in, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a42_PORT_A_address_reg = DFFE(HB1_ram_block2a42_PORT_A_address, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a42_PORT_B_address_reg = DFFE(HB1_ram_block2a42_PORT_B_address, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_PORT_A_write_enable = GND; HB1_ram_block2a42_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_A_write_enable, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1_ram_block2a42_PORT_B_write_enable = GND; HB1_ram_block2a42_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a42_PORT_B_write_enable, HB1_ram_block2a42_clock_1, , , HB1_ram_block2a42_clock_enable_1); HB1_ram_block2a42_clock_0 = S2__clk0; HB1_ram_block2a42_clock_1 = GND; HB1_ram_block2a42_clock_enable_0 = JB3_w_anode3345w[3]; HB1_ram_block2a42_clock_enable_1 = GND; HB1_ram_block2a42_PORT_A_data_out = MEMORY(HB1_ram_block2a42_PORT_A_data_in_reg, HB1_ram_block2a42_PORT_B_data_in_reg, HB1_ram_block2a42_PORT_A_address_reg, HB1_ram_block2a42_PORT_B_address_reg, HB1_ram_block2a42_PORT_A_write_enable_reg, HB1_ram_block2a42_PORT_B_write_enable_reg, , , HB1_ram_block2a42_clock_0, HB1_ram_block2a42_clock_1, HB1_ram_block2a42_clock_enable_0, HB1_ram_block2a42_clock_enable_1, , ); HB1_ram_block2a42_PORT_A_data_out_reg = DFFE(HB1_ram_block2a42_PORT_A_data_out, HB1_ram_block2a42_clock_0, , , HB1_ram_block2a42_clock_enable_0); HB1M2148Q = HB1_ram_block2a42_PORT_A_data_out_reg[7]; --KB1L238 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~579 KB1L238 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M2196Q # !HB1_address_reg_a[6] & (HB1M2146Q)) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6]); --KB1L239 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~580 KB1L239 = HB1_address_reg_a[7] & (KB1L238) # !HB1_address_reg_a[7] & (KB1L238 & HB1M2096Q # !KB1L238 & (HB1M2046Q)); --HB1_ram_block2a10 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10 = HB1_ram_block2a10_PORT_A_data_out_reg[0]; --HB1M542Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT1 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M542Q = HB1_ram_block2a10_PORT_A_data_out_reg[1]; --HB1M543Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT2 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M543Q = HB1_ram_block2a10_PORT_A_data_out_reg[2]; --HB1M544Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT3 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M544Q = HB1_ram_block2a10_PORT_A_data_out_reg[3]; --HB1M545Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT4 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M545Q = HB1_ram_block2a10_PORT_A_data_out_reg[4]; --HB1M546Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT5 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M546Q = HB1_ram_block2a10_PORT_A_data_out_reg[5]; --HB1M547Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT6 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M547Q = HB1_ram_block2a10_PORT_A_data_out_reg[6]; --HB1M548Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT7 HB1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a10_PORT_A_data_in_reg = DFFE(HB1_ram_block2a10_PORT_A_data_in, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_data_in = ~GND; HB1_ram_block2a10_PORT_B_data_in_reg = DFFE(HB1_ram_block2a10_PORT_B_data_in, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a10_PORT_A_address_reg = DFFE(HB1_ram_block2a10_PORT_A_address, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a10_PORT_B_address_reg = DFFE(HB1_ram_block2a10_PORT_B_address, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_PORT_A_write_enable = GND; HB1_ram_block2a10_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_A_write_enable, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1_ram_block2a10_PORT_B_write_enable = GND; HB1_ram_block2a10_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a10_PORT_B_write_enable, HB1_ram_block2a10_clock_1, , , HB1_ram_block2a10_clock_enable_1); HB1_ram_block2a10_clock_0 = S2__clk0; HB1_ram_block2a10_clock_1 = GND; HB1_ram_block2a10_clock_enable_0 = JB3_w_anode2973w[3]; HB1_ram_block2a10_clock_enable_1 = GND; HB1_ram_block2a10_PORT_A_data_out = MEMORY(HB1_ram_block2a10_PORT_A_data_in_reg, HB1_ram_block2a10_PORT_B_data_in_reg, HB1_ram_block2a10_PORT_A_address_reg, HB1_ram_block2a10_PORT_B_address_reg, HB1_ram_block2a10_PORT_A_write_enable_reg, HB1_ram_block2a10_PORT_B_write_enable_reg, , , HB1_ram_block2a10_clock_0, HB1_ram_block2a10_clock_1, HB1_ram_block2a10_clock_enable_0, HB1_ram_block2a10_clock_enable_1, , ); HB1_ram_block2a10_PORT_A_data_out_reg = DFFE(HB1_ram_block2a10_PORT_A_data_out, HB1_ram_block2a10_clock_0, , , HB1_ram_block2a10_clock_enable_0); HB1M548Q = HB1_ram_block2a10_PORT_A_data_out_reg[7]; --HB1_ram_block2a8 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8 = HB1_ram_block2a8_PORT_A_data_out_reg[0]; --HB1M442Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT1 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M442Q = HB1_ram_block2a8_PORT_A_data_out_reg[1]; --HB1M443Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT2 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M443Q = HB1_ram_block2a8_PORT_A_data_out_reg[2]; --HB1M444Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT3 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M444Q = HB1_ram_block2a8_PORT_A_data_out_reg[3]; --HB1M445Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT4 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M445Q = HB1_ram_block2a8_PORT_A_data_out_reg[4]; --HB1M446Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT5 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M446Q = HB1_ram_block2a8_PORT_A_data_out_reg[5]; --HB1M447Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT6 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M447Q = HB1_ram_block2a8_PORT_A_data_out_reg[6]; --HB1M448Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT7 HB1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a8_PORT_A_data_in_reg = DFFE(HB1_ram_block2a8_PORT_A_data_in, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_data_in = ~GND; HB1_ram_block2a8_PORT_B_data_in_reg = DFFE(HB1_ram_block2a8_PORT_B_data_in, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a8_PORT_A_address_reg = DFFE(HB1_ram_block2a8_PORT_A_address, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a8_PORT_B_address_reg = DFFE(HB1_ram_block2a8_PORT_B_address, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_PORT_A_write_enable = GND; HB1_ram_block2a8_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_A_write_enable, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1_ram_block2a8_PORT_B_write_enable = GND; HB1_ram_block2a8_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a8_PORT_B_write_enable, HB1_ram_block2a8_clock_1, , , HB1_ram_block2a8_clock_enable_1); HB1_ram_block2a8_clock_0 = S2__clk0; HB1_ram_block2a8_clock_1 = GND; HB1_ram_block2a8_clock_enable_0 = JB3_w_anode2952w[3]; HB1_ram_block2a8_clock_enable_1 = GND; HB1_ram_block2a8_PORT_A_data_out = MEMORY(HB1_ram_block2a8_PORT_A_data_in_reg, HB1_ram_block2a8_PORT_B_data_in_reg, HB1_ram_block2a8_PORT_A_address_reg, HB1_ram_block2a8_PORT_B_address_reg, HB1_ram_block2a8_PORT_A_write_enable_reg, HB1_ram_block2a8_PORT_B_write_enable_reg, , , HB1_ram_block2a8_clock_0, HB1_ram_block2a8_clock_1, HB1_ram_block2a8_clock_enable_0, HB1_ram_block2a8_clock_enable_1, , ); HB1_ram_block2a8_PORT_A_data_out_reg = DFFE(HB1_ram_block2a8_PORT_A_data_out, HB1_ram_block2a8_clock_0, , , HB1_ram_block2a8_clock_enable_0); HB1M448Q = HB1_ram_block2a8_PORT_A_data_out_reg[7]; --KB1L240 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~581 KB1L240 = !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M546Q # !HB1_address_reg_a[7] & (HB1M446Q)); --HB1_ram_block2a11 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11 = HB1_ram_block2a11_PORT_A_data_out_reg[0]; --HB1M592Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT1 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M592Q = HB1_ram_block2a11_PORT_A_data_out_reg[1]; --HB1M593Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT2 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M593Q = HB1_ram_block2a11_PORT_A_data_out_reg[2]; --HB1M594Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT3 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M594Q = HB1_ram_block2a11_PORT_A_data_out_reg[3]; --HB1M595Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT4 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M595Q = HB1_ram_block2a11_PORT_A_data_out_reg[4]; --HB1M596Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT5 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M596Q = HB1_ram_block2a11_PORT_A_data_out_reg[5]; --HB1M597Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT6 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M597Q = HB1_ram_block2a11_PORT_A_data_out_reg[6]; --HB1M598Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT7 HB1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a11_PORT_A_data_in_reg = DFFE(HB1_ram_block2a11_PORT_A_data_in, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_data_in = ~GND; HB1_ram_block2a11_PORT_B_data_in_reg = DFFE(HB1_ram_block2a11_PORT_B_data_in, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a11_PORT_A_address_reg = DFFE(HB1_ram_block2a11_PORT_A_address, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a11_PORT_B_address_reg = DFFE(HB1_ram_block2a11_PORT_B_address, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_PORT_A_write_enable = GND; HB1_ram_block2a11_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_A_write_enable, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1_ram_block2a11_PORT_B_write_enable = GND; HB1_ram_block2a11_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a11_PORT_B_write_enable, HB1_ram_block2a11_clock_1, , , HB1_ram_block2a11_clock_enable_1); HB1_ram_block2a11_clock_0 = S2__clk0; HB1_ram_block2a11_clock_1 = GND; HB1_ram_block2a11_clock_enable_0 = JB3_w_anode2983w[3]; HB1_ram_block2a11_clock_enable_1 = GND; HB1_ram_block2a11_PORT_A_data_out = MEMORY(HB1_ram_block2a11_PORT_A_data_in_reg, HB1_ram_block2a11_PORT_B_data_in_reg, HB1_ram_block2a11_PORT_A_address_reg, HB1_ram_block2a11_PORT_B_address_reg, HB1_ram_block2a11_PORT_A_write_enable_reg, HB1_ram_block2a11_PORT_B_write_enable_reg, , , HB1_ram_block2a11_clock_0, HB1_ram_block2a11_clock_1, HB1_ram_block2a11_clock_enable_0, HB1_ram_block2a11_clock_enable_1, , ); HB1_ram_block2a11_PORT_A_data_out_reg = DFFE(HB1_ram_block2a11_PORT_A_data_out, HB1_ram_block2a11_clock_0, , , HB1_ram_block2a11_clock_enable_0); HB1M598Q = HB1_ram_block2a11_PORT_A_data_out_reg[7]; --HB1_ram_block2a9 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9 --RAM Block Operation Mode: True Dual-Port --Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1 --Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1 --Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9 = HB1_ram_block2a9_PORT_A_data_out_reg[0]; --HB1M492Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT1 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M492Q = HB1_ram_block2a9_PORT_A_data_out_reg[1]; --HB1M493Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT2 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M493Q = HB1_ram_block2a9_PORT_A_data_out_reg[2]; --HB1M494Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT3 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M494Q = HB1_ram_block2a9_PORT_A_data_out_reg[3]; --HB1M495Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT4 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M495Q = HB1_ram_block2a9_PORT_A_data_out_reg[4]; --HB1M496Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT5 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M496Q = HB1_ram_block2a9_PORT_A_data_out_reg[5]; --HB1M497Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT6 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M497Q = HB1_ram_block2a9_PORT_A_data_out_reg[6]; --HB1M498Q is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT7 HB1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC); HB1_ram_block2a9_PORT_A_data_in_reg = DFFE(HB1_ram_block2a9_PORT_A_data_in, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_data_in = ~GND; HB1_ram_block2a9_PORT_B_data_in_reg = DFFE(HB1_ram_block2a9_PORT_B_data_in, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_address = BUS(N1L104, N1L106, N1L108, N1L110, N1L112, N1L114, N1L116, N1L118, N1L120); HB1_ram_block2a9_PORT_A_address_reg = DFFE(HB1_ram_block2a9_PORT_A_address, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND); HB1_ram_block2a9_PORT_B_address_reg = DFFE(HB1_ram_block2a9_PORT_B_address, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_PORT_A_write_enable = GND; HB1_ram_block2a9_PORT_A_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_A_write_enable, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1_ram_block2a9_PORT_B_write_enable = GND; HB1_ram_block2a9_PORT_B_write_enable_reg = DFFE(HB1_ram_block2a9_PORT_B_write_enable, HB1_ram_block2a9_clock_1, , , HB1_ram_block2a9_clock_enable_1); HB1_ram_block2a9_clock_0 = S2__clk0; HB1_ram_block2a9_clock_1 = GND; HB1_ram_block2a9_clock_enable_0 = JB3_w_anode2963w[3]; HB1_ram_block2a9_clock_enable_1 = GND; HB1_ram_block2a9_PORT_A_data_out = MEMORY(HB1_ram_block2a9_PORT_A_data_in_reg, HB1_ram_block2a9_PORT_B_data_in_reg, HB1_ram_block2a9_PORT_A_address_reg, HB1_ram_block2a9_PORT_B_address_reg, HB1_ram_block2a9_PORT_A_write_enable_reg, HB1_ram_block2a9_PORT_B_write_enable_reg, , , HB1_ram_block2a9_clock_0, HB1_ram_block2a9_clock_1, HB1_ram_block2a9_clock_enable_0, HB1_ram_block2a9_clock_enable_1, , ); HB1_ram_block2a9_PORT_A_data_out_reg = DFFE(HB1_ram_block2a9_PORT_A_data_out, HB1_ram_block2a9_clock_0, , , HB1_ram_block2a9_clock_enable_0); HB1M498Q = HB1_ram_block2a9_PORT_A_data_out_reg[7]; --KB1L241 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~582 KB1L241 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M596Q # !HB1_address_reg_a[7] & (HB1M496Q)); --KB1L242 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~583 KB1L242 = HB1_address_reg_a[11] & KB1L239 # !HB1_address_reg_a[11] & (KB1L240 # KB1L241); --KB1L243 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~584 KB1L243 = HB1_address_reg_a[9] & !HB1_address_reg_a[10] & !HB1_address_reg_a[8]; --KB1L244 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~585 KB1L244 = KB1L235 # KB1L237 # KB1L242 & KB1L243; --KB1L54 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5039 KB1L54 = KB1L244 & (KB1L48 # !HB1_address_reg_a[10]) # !KB1L244 & (KB1L53 & HB1_address_reg_a[10]); --N1_ADDR_dd[0] is VGA_OSD_RAM:u9|ADDR_dd[0] N1_ADDR_dd[0] = DFFEAS(N1L7, S2__clk0, KEY[0], , , , , , ); --KB1L55 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5040 KB1L55 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2547Q; --KB1L56 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5041 KB1L56 = HB1_address_reg_a[6] & (HB1M2497Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2447Q & !HB1_address_reg_a[7]); --KB1L57 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5042 KB1L57 = !HB1_address_reg_a[9] & (KB1L55 & HB1_address_reg_a[7] & !KB1L56 # !KB1L55 & !HB1_address_reg_a[7] & KB1L56); --KB1L253 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~49 KB1L253 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1547Q # !HB1_address_reg_a[7] & (HB1M1447Q)); --KB1L254 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~50 KB1L254 = HB1_address_reg_a[6] & (KB1L253 & (HB1M1597Q) # !KB1L253 & HB1M1497Q) # !HB1_address_reg_a[6] & (KB1L253); --KB1L251 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~44 KB1L251 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1097Q # !HB1_address_reg_a[6] & (HB1M1047Q)); --KB1L252 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~45 KB1L252 = HB1_address_reg_a[7] & (KB1L251 & (HB1M1197Q) # !KB1L251 & HB1M1147Q) # !HB1_address_reg_a[7] & (KB1L251); --KB1L58 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5043 KB1L58 = HB1_address_reg_a[9] & KB1L254 # !HB1_address_reg_a[9] & (KB1L252); --KB1L255 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~407 KB1L255 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M897Q # !HB1_address_reg_a[6] & (HB1M847Q)); --KB1L256 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~408 KB1L256 = HB1_address_reg_a[7] & (KB1L255 & (HB1M997Q) # !KB1L255 & HB1M947Q) # !HB1_address_reg_a[7] & (KB1L255); --KB1L59 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5044 KB1L59 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1397Q # !HB1_address_reg_a[6] & (HB1M1347Q)); --KB1L60 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5045 KB1L60 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1297Q # !HB1_address_reg_a[6] & (HB1M1247Q)); --KB1L61 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5046 KB1L61 = HB1_address_reg_a[9] & (KB1L59 # KB1L60) # !HB1_address_reg_a[9] & KB1L256; --KB1L62 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5047 KB1L62 = HB1_address_reg_a[8] & KB1L58 # !HB1_address_reg_a[8] & (KB1L61); --KB1L259 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~47 KB1L259 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2347Q # !HB1_address_reg_a[7] & (HB1M2247Q)); --KB1L260 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~48 KB1L260 = HB1_address_reg_a[6] & (KB1L259 & (HB1M2397Q) # !KB1L259 & HB1M2297Q) # !HB1_address_reg_a[6] & (KB1L259); --KB1L247 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~47 KB1L247 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M697Q # !HB1_address_reg_a[6] & (HB1M647Q)); --KB1L248 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~48 KB1L248 = HB1_address_reg_a[7] & (KB1L247 & (HB1M797Q) # !KB1L247 & HB1M747Q) # !HB1_address_reg_a[7] & (KB1L247); --KB1L263 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~566 KB1L263 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L260 # !HB1_address_reg_a[11] & (KB1L248)); --KB1L257 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~44 KB1L257 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1897Q # !HB1_address_reg_a[6] & (HB1M1847Q)); --KB1L258 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~45 KB1L258 = HB1_address_reg_a[7] & (KB1L257 & (HB1M1997Q) # !KB1L257 & HB1M1947Q) # !HB1_address_reg_a[7] & (KB1L257); --KB1L245 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~44 KB1L245 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M347Q # !HB1_address_reg_a[7] & (HB1M247Q)); --KB1L246 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~45 KB1L246 = HB1_address_reg_a[6] & (KB1L245 & (HB1M397Q) # !KB1L245 & HB1M297Q) # !HB1_address_reg_a[6] & (KB1L245); --KB1L264 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~567 KB1L264 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L258 # !HB1_address_reg_a[11] & (KB1L246)); --KB1L265 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~568 KB1L265 = KB1L147 # KB1L232 & (KB1L263 # KB1L264); --KB1L261 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~281 KB1L261 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1697Q # !HB1_address_reg_a[6] & (HB1M1647Q)); --KB1L262 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~282 KB1L262 = HB1_address_reg_a[7] & (KB1L261 & (HB1M1797Q) # !KB1L261 & HB1M1747Q) # !HB1_address_reg_a[7] & (KB1L261); --KB1L249 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~281 KB1L249 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M147Q # !HB1_address_reg_a[7] & (HB1M47Q)); --KB1L250 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~282 KB1L250 = HB1_address_reg_a[6] & (KB1L249 & (HB1M197Q) # !KB1L249 & HB1M97Q) # !HB1_address_reg_a[6] & (KB1L249); --KB1L266 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~569 KB1L266 = KB1L236 & (HB1_address_reg_a[11] & KB1L262 # !HB1_address_reg_a[11] & (KB1L250)); --KB1L267 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~570 KB1L267 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2197Q # !HB1_address_reg_a[7] & (HB1M2097Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L268 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~571 KB1L268 = HB1_address_reg_a[6] & (KB1L267) # !HB1_address_reg_a[6] & (KB1L267 & HB1M2147Q # !KB1L267 & (HB1M2047Q)); --KB1L269 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~572 KB1L269 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M497Q # !HB1_address_reg_a[6] & (HB1M447Q)); --KB1L270 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~573 KB1L270 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M597Q # !HB1_address_reg_a[6] & (HB1M547Q)); --KB1L271 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~574 KB1L271 = HB1_address_reg_a[11] & KB1L268 # !HB1_address_reg_a[11] & (KB1L269 # KB1L270); --KB1L272 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~575 KB1L272 = KB1L265 # KB1L266 # KB1L243 & KB1L271; --KB1L63 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5048 KB1L63 = KB1L272 & (KB1L57 # !HB1_address_reg_a[10]) # !KB1L272 & (KB1L62 & HB1_address_reg_a[10]); --N1_ADDR_dd[1] is VGA_OSD_RAM:u9|ADDR_dd[1] N1_ADDR_dd[1] = DFFEAS(N1L9, S2__clk0, KEY[0], , , , , , ); --KB1L37 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5049 KB1L37 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2545Q; --KB1L38 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5050 KB1L38 = HB1_address_reg_a[6] & (HB1M2495Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2445Q & !HB1_address_reg_a[7]); --KB1L39 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5051 KB1L39 = !HB1_address_reg_a[9] & (KB1L37 & HB1_address_reg_a[7] & !KB1L38 # !KB1L37 & !HB1_address_reg_a[7] & KB1L38); --KB1L194 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~49 KB1L194 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1545Q # !HB1_address_reg_a[7] & (HB1M1445Q)); --KB1L195 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~50 KB1L195 = HB1_address_reg_a[6] & (KB1L194 & (HB1M1595Q) # !KB1L194 & HB1M1495Q) # !HB1_address_reg_a[6] & (KB1L194); --KB1L192 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~44 KB1L192 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1095Q # !HB1_address_reg_a[6] & (HB1M1045Q)); --KB1L193 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~45 KB1L193 = HB1_address_reg_a[7] & (KB1L192 & (HB1M1195Q) # !KB1L192 & HB1M1145Q) # !HB1_address_reg_a[7] & (KB1L192); --KB1L40 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5052 KB1L40 = HB1_address_reg_a[9] & KB1L195 # !HB1_address_reg_a[9] & (KB1L193); --KB1L196 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~407 KB1L196 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M895Q # !HB1_address_reg_a[6] & (HB1M845Q)); --KB1L197 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~408 KB1L197 = HB1_address_reg_a[7] & (KB1L196 & (HB1M995Q) # !KB1L196 & HB1M945Q) # !HB1_address_reg_a[7] & (KB1L196); --KB1L41 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5053 KB1L41 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1395Q # !HB1_address_reg_a[6] & (HB1M1345Q)); --KB1L42 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5054 KB1L42 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1295Q # !HB1_address_reg_a[6] & (HB1M1245Q)); --KB1L43 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5055 KB1L43 = HB1_address_reg_a[9] & (KB1L41 # KB1L42) # !HB1_address_reg_a[9] & KB1L197; --KB1L44 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5056 KB1L44 = HB1_address_reg_a[8] & KB1L40 # !HB1_address_reg_a[8] & (KB1L43); --KB1L200 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~47 KB1L200 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2345Q # !HB1_address_reg_a[7] & (HB1M2245Q)); --KB1L201 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~48 KB1L201 = HB1_address_reg_a[6] & (KB1L200 & (HB1M2395Q) # !KB1L200 & HB1M2295Q) # !HB1_address_reg_a[6] & (KB1L200); --KB1L188 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~47 KB1L188 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M695Q # !HB1_address_reg_a[6] & (HB1M645Q)); --KB1L189 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~48 KB1L189 = HB1_address_reg_a[7] & (KB1L188 & (HB1M795Q) # !KB1L188 & HB1M745Q) # !HB1_address_reg_a[7] & (KB1L188); --KB1L204 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~566 KB1L204 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L201 # !HB1_address_reg_a[11] & (KB1L189)); --KB1L198 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~44 KB1L198 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1895Q # !HB1_address_reg_a[6] & (HB1M1845Q)); --KB1L199 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~45 KB1L199 = HB1_address_reg_a[7] & (KB1L198 & (HB1M1995Q) # !KB1L198 & HB1M1945Q) # !HB1_address_reg_a[7] & (KB1L198); --KB1L186 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~44 KB1L186 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M345Q # !HB1_address_reg_a[7] & (HB1M245Q)); --KB1L187 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~45 KB1L187 = HB1_address_reg_a[6] & (KB1L186 & (HB1M395Q) # !KB1L186 & HB1M295Q) # !HB1_address_reg_a[6] & (KB1L186); --KB1L205 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~567 KB1L205 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L199 # !HB1_address_reg_a[11] & (KB1L187)); --KB1L206 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~568 KB1L206 = KB1L147 # KB1L232 & (KB1L204 # KB1L205); --KB1L202 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~281 KB1L202 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1695Q # !HB1_address_reg_a[6] & (HB1M1645Q)); --KB1L203 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~282 KB1L203 = HB1_address_reg_a[7] & (KB1L202 & (HB1M1795Q) # !KB1L202 & HB1M1745Q) # !HB1_address_reg_a[7] & (KB1L202); --KB1L190 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~281 KB1L190 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M145Q # !HB1_address_reg_a[7] & (HB1M45Q)); --KB1L191 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~282 KB1L191 = HB1_address_reg_a[6] & (KB1L190 & (HB1M195Q) # !KB1L190 & HB1M95Q) # !HB1_address_reg_a[6] & (KB1L190); --KB1L207 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~569 KB1L207 = KB1L236 & (HB1_address_reg_a[11] & KB1L203 # !HB1_address_reg_a[11] & (KB1L191)); --KB1L208 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~570 KB1L208 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2195Q # !HB1_address_reg_a[7] & (HB1M2095Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L209 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~571 KB1L209 = HB1_address_reg_a[6] & (KB1L208) # !HB1_address_reg_a[6] & (KB1L208 & HB1M2145Q # !KB1L208 & (HB1M2045Q)); --KB1L210 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~572 KB1L210 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M495Q # !HB1_address_reg_a[6] & (HB1M445Q)); --KB1L211 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~573 KB1L211 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M595Q # !HB1_address_reg_a[6] & (HB1M545Q)); --KB1L212 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~574 KB1L212 = HB1_address_reg_a[11] & KB1L209 # !HB1_address_reg_a[11] & (KB1L210 # KB1L211); --KB1L213 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~575 KB1L213 = KB1L206 # KB1L207 # KB1L243 & KB1L212; --KB1L45 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5057 KB1L45 = KB1L213 & (KB1L39 # !HB1_address_reg_a[10]) # !KB1L213 & (KB1L44 & HB1_address_reg_a[10]); --N1L20 is VGA_OSD_RAM:u9|Mux~32 N1L20 = N1_ADDR_dd[0] & (N1_ADDR_dd[1]) # !N1_ADDR_dd[0] & (N1_ADDR_dd[1] & KB1L63 # !N1_ADDR_dd[1] & (KB1L45)); --KB1L64 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5058 KB1L64 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2548Q; --KB1L65 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5059 KB1L65 = HB1_address_reg_a[6] & (HB1M2498Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2448Q & !HB1_address_reg_a[7]); --KB1L66 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5060 KB1L66 = !HB1_address_reg_a[9] & (KB1L64 & HB1_address_reg_a[7] & !KB1L65 # !KB1L64 & !HB1_address_reg_a[7] & KB1L65); --KB1L281 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~49 KB1L281 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1498Q # !HB1_address_reg_a[6] & (HB1M1448Q)); --KB1L282 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~50 KB1L282 = HB1_address_reg_a[7] & (KB1L281 & (HB1M1598Q) # !KB1L281 & HB1M1548Q) # !HB1_address_reg_a[7] & (KB1L281); --KB1L279 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~44 KB1L279 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1148Q # !HB1_address_reg_a[7] & (HB1M1048Q)); --KB1L280 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~45 KB1L280 = HB1_address_reg_a[6] & (KB1L279 & (HB1M1198Q) # !KB1L279 & HB1M1098Q) # !HB1_address_reg_a[6] & (KB1L279); --KB1L67 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5061 KB1L67 = HB1_address_reg_a[9] & KB1L282 # !HB1_address_reg_a[9] & (KB1L280); --KB1L283 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~407 KB1L283 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M948Q # !HB1_address_reg_a[7] & (HB1M848Q)); --KB1L284 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~408 KB1L284 = HB1_address_reg_a[6] & (KB1L283 & (HB1M998Q) # !KB1L283 & HB1M898Q) # !HB1_address_reg_a[6] & (KB1L283); --KB1L68 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5062 KB1L68 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1398Q # !HB1_address_reg_a[6] & (HB1M1348Q)); --KB1L69 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5063 KB1L69 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1298Q # !HB1_address_reg_a[6] & (HB1M1248Q)); --KB1L70 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5064 KB1L70 = HB1_address_reg_a[9] & (KB1L68 # KB1L69) # !HB1_address_reg_a[9] & KB1L284; --KB1L71 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5065 KB1L71 = HB1_address_reg_a[8] & KB1L67 # !HB1_address_reg_a[8] & (KB1L70); --KB1L287 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~47 KB1L287 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M2298Q # !HB1_address_reg_a[6] & (HB1M2248Q)); --KB1L288 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~48 KB1L288 = HB1_address_reg_a[7] & (KB1L287 & (HB1M2398Q) # !KB1L287 & HB1M2348Q) # !HB1_address_reg_a[7] & (KB1L287); --KB1L275 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~47 KB1L275 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M748Q # !HB1_address_reg_a[7] & (HB1M648Q)); --KB1L276 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~48 KB1L276 = HB1_address_reg_a[6] & (KB1L275 & (HB1M798Q) # !KB1L275 & HB1M698Q) # !HB1_address_reg_a[6] & (KB1L275); --KB1L291 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~545 KB1L291 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L288 # !HB1_address_reg_a[11] & (KB1L276)); --KB1L285 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~44 KB1L285 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1948Q # !HB1_address_reg_a[7] & (HB1M1848Q)); --KB1L286 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~45 KB1L286 = HB1_address_reg_a[6] & (KB1L285 & (HB1M1998Q) # !KB1L285 & HB1M1898Q) # !HB1_address_reg_a[6] & (KB1L285); --KB1L273 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~44 KB1L273 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M298Q # !HB1_address_reg_a[6] & (HB1M248Q)); --KB1L274 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~45 KB1L274 = HB1_address_reg_a[7] & (KB1L273 & (HB1M398Q) # !KB1L273 & HB1M348Q) # !HB1_address_reg_a[7] & (KB1L273); --KB1L292 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~546 KB1L292 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L286 # !HB1_address_reg_a[11] & (KB1L274)); --KB1L293 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~547 KB1L293 = KB1L147 # KB1L232 & (KB1L291 # KB1L292); --KB1L289 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~281 KB1L289 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1748Q # !HB1_address_reg_a[7] & (HB1M1648Q)); --KB1L290 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~282 KB1L290 = HB1_address_reg_a[6] & (KB1L289 & (HB1M1798Q) # !KB1L289 & HB1M1698Q) # !HB1_address_reg_a[6] & (KB1L289); --KB1L277 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~281 KB1L277 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M98Q # !HB1_address_reg_a[6] & (HB1M48Q)); --KB1L278 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~282 KB1L278 = HB1_address_reg_a[7] & (KB1L277 & (HB1M198Q) # !KB1L277 & HB1M148Q) # !HB1_address_reg_a[7] & (KB1L277); --KB1L294 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~548 KB1L294 = KB1L236 & (HB1_address_reg_a[11] & KB1L290 # !HB1_address_reg_a[11] & (KB1L278)); --KB1L295 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~549 KB1L295 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2198Q # !HB1_address_reg_a[7] & (HB1M2098Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L296 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~550 KB1L296 = HB1_address_reg_a[6] & (KB1L295) # !HB1_address_reg_a[6] & (KB1L295 & HB1M2148Q # !KB1L295 & (HB1M2048Q)); --KB1L297 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~551 KB1L297 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M498Q # !HB1_address_reg_a[6] & (HB1M448Q)); --KB1L298 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~552 KB1L298 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M598Q # !HB1_address_reg_a[6] & (HB1M548Q)); --KB1L299 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~553 KB1L299 = HB1_address_reg_a[11] & KB1L296 # !HB1_address_reg_a[11] & (KB1L297 # KB1L298); --KB1L300 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~554 KB1L300 = KB1L293 # KB1L294 # KB1L243 & KB1L299; --KB1L72 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5066 KB1L72 = KB1L300 & (KB1L66 # !HB1_address_reg_a[10]) # !KB1L300 & (KB1L71 & HB1_address_reg_a[10]); --N1L21 is VGA_OSD_RAM:u9|Mux~33 N1L21 = N1_ADDR_dd[0] & (N1L20 & (KB1L72) # !N1L20 & KB1L54) # !N1_ADDR_dd[0] & (N1L20); --KB1L19 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5067 KB1L19 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2543Q; --KB1L20 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5068 KB1L20 = HB1_address_reg_a[6] & (HB1M2493Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2443Q & !HB1_address_reg_a[7]); --KB1L21 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5069 KB1L21 = !HB1_address_reg_a[9] & (KB1L19 & HB1_address_reg_a[7] & !KB1L20 # !KB1L19 & !HB1_address_reg_a[7] & KB1L20); --KB1L137 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~49 KB1L137 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1543Q # !HB1_address_reg_a[7] & (HB1M1443Q)); --KB1L138 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~50 KB1L138 = HB1_address_reg_a[6] & (KB1L137 & (HB1M1593Q) # !KB1L137 & HB1M1493Q) # !HB1_address_reg_a[6] & (KB1L137); --KB1L135 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~44 KB1L135 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1093Q # !HB1_address_reg_a[6] & (HB1M1043Q)); --KB1L136 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~45 KB1L136 = HB1_address_reg_a[7] & (KB1L135 & (HB1M1193Q) # !KB1L135 & HB1M1143Q) # !HB1_address_reg_a[7] & (KB1L135); --KB1L22 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5070 KB1L22 = HB1_address_reg_a[9] & KB1L138 # !HB1_address_reg_a[9] & (KB1L136); --KB1L139 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~407 KB1L139 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M893Q # !HB1_address_reg_a[6] & (HB1M843Q)); --KB1L140 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~408 KB1L140 = HB1_address_reg_a[7] & (KB1L139 & (HB1M993Q) # !KB1L139 & HB1M943Q) # !HB1_address_reg_a[7] & (KB1L139); --KB1L23 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5071 KB1L23 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1393Q # !HB1_address_reg_a[6] & (HB1M1343Q)); --KB1L24 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5072 KB1L24 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1293Q # !HB1_address_reg_a[6] & (HB1M1243Q)); --KB1L25 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5073 KB1L25 = HB1_address_reg_a[9] & (KB1L23 # KB1L24) # !HB1_address_reg_a[9] & KB1L140; --KB1L26 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5074 KB1L26 = HB1_address_reg_a[8] & KB1L22 # !HB1_address_reg_a[8] & (KB1L25); --KB1L143 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~47 KB1L143 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2343Q # !HB1_address_reg_a[7] & (HB1M2243Q)); --KB1L144 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~48 KB1L144 = HB1_address_reg_a[6] & (KB1L143 & (HB1M2393Q) # !KB1L143 & HB1M2293Q) # !HB1_address_reg_a[6] & (KB1L143); --KB1L131 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~47 KB1L131 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M693Q # !HB1_address_reg_a[6] & (HB1M643Q)); --KB1L132 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~48 KB1L132 = HB1_address_reg_a[7] & (KB1L131 & (HB1M793Q) # !KB1L131 & HB1M743Q) # !HB1_address_reg_a[7] & (KB1L131); --KB1L148 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~609 KB1L148 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L144 # !HB1_address_reg_a[11] & (KB1L132)); --KB1L141 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~44 KB1L141 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1893Q # !HB1_address_reg_a[6] & (HB1M1843Q)); --KB1L142 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~45 KB1L142 = HB1_address_reg_a[7] & (KB1L141 & (HB1M1993Q) # !KB1L141 & HB1M1943Q) # !HB1_address_reg_a[7] & (KB1L141); --KB1L129 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~44 KB1L129 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M343Q # !HB1_address_reg_a[7] & (HB1M243Q)); --KB1L130 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~45 KB1L130 = HB1_address_reg_a[6] & (KB1L129 & (HB1M393Q) # !KB1L129 & HB1M293Q) # !HB1_address_reg_a[6] & (KB1L129); --KB1L149 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~610 KB1L149 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L142 # !HB1_address_reg_a[11] & (KB1L130)); --KB1L150 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~611 KB1L150 = KB1L147 # KB1L232 & (KB1L148 # KB1L149); --KB1L145 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~281 KB1L145 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1693Q # !HB1_address_reg_a[6] & (HB1M1643Q)); --KB1L146 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~282 KB1L146 = HB1_address_reg_a[7] & (KB1L145 & (HB1M1793Q) # !KB1L145 & HB1M1743Q) # !HB1_address_reg_a[7] & (KB1L145); --KB1L133 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~281 KB1L133 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M143Q # !HB1_address_reg_a[7] & (HB1M43Q)); --KB1L134 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~282 KB1L134 = HB1_address_reg_a[6] & (KB1L133 & (HB1M193Q) # !KB1L133 & HB1M93Q) # !HB1_address_reg_a[6] & (KB1L133); --KB1L151 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~612 KB1L151 = KB1L236 & (HB1_address_reg_a[11] & KB1L146 # !HB1_address_reg_a[11] & (KB1L134)); --KB1L152 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~613 KB1L152 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2193Q # !HB1_address_reg_a[7] & (HB1M2093Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L153 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~614 KB1L153 = HB1_address_reg_a[6] & (KB1L152) # !HB1_address_reg_a[6] & (KB1L152 & HB1M2143Q # !KB1L152 & (HB1M2043Q)); --KB1L154 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~615 KB1L154 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M493Q # !HB1_address_reg_a[6] & (HB1M443Q)); --KB1L155 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~616 KB1L155 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M593Q # !HB1_address_reg_a[6] & (HB1M543Q)); --KB1L156 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~617 KB1L156 = HB1_address_reg_a[11] & KB1L153 # !HB1_address_reg_a[11] & (KB1L154 # KB1L155); --KB1L157 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~618 KB1L157 = KB1L150 # KB1L151 # KB1L243 & KB1L156; --KB1L27 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5075 KB1L27 = KB1L157 & (KB1L21 # !HB1_address_reg_a[10]) # !KB1L157 & (KB1L26 & HB1_address_reg_a[10]); --KB1L10 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5076 KB1L10 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2542Q; --KB1L11 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5077 KB1L11 = HB1_address_reg_a[6] & (HB1M2492Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2442Q & !HB1_address_reg_a[7]); --KB1L12 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5078 KB1L12 = !HB1_address_reg_a[9] & (KB1L10 & HB1_address_reg_a[7] & !KB1L11 # !KB1L10 & !HB1_address_reg_a[7] & KB1L11); --KB1L109 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~49 KB1L109 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1492Q # !HB1_address_reg_a[6] & (HB1M1442Q)); --KB1L110 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~50 KB1L110 = HB1_address_reg_a[7] & (KB1L109 & (HB1M1592Q) # !KB1L109 & HB1M1542Q) # !HB1_address_reg_a[7] & (KB1L109); --KB1L107 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~44 KB1L107 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1142Q # !HB1_address_reg_a[7] & (HB1M1042Q)); --KB1L108 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~45 KB1L108 = HB1_address_reg_a[6] & (KB1L107 & (HB1M1192Q) # !KB1L107 & HB1M1092Q) # !HB1_address_reg_a[6] & (KB1L107); --KB1L13 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5079 KB1L13 = HB1_address_reg_a[9] & KB1L110 # !HB1_address_reg_a[9] & (KB1L108); --KB1L111 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~407 KB1L111 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M942Q # !HB1_address_reg_a[7] & (HB1M842Q)); --KB1L112 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~408 KB1L112 = HB1_address_reg_a[6] & (KB1L111 & (HB1M992Q) # !KB1L111 & HB1M892Q) # !HB1_address_reg_a[6] & (KB1L111); --KB1L14 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5080 KB1L14 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1392Q # !HB1_address_reg_a[6] & (HB1M1342Q)); --KB1L15 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5081 KB1L15 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1292Q # !HB1_address_reg_a[6] & (HB1M1242Q)); --KB1L16 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5082 KB1L16 = HB1_address_reg_a[9] & (KB1L14 # KB1L15) # !HB1_address_reg_a[9] & KB1L112; --KB1L17 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5083 KB1L17 = HB1_address_reg_a[8] & KB1L13 # !HB1_address_reg_a[8] & (KB1L16); --KB1L115 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~47 KB1L115 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M2292Q # !HB1_address_reg_a[6] & (HB1M2242Q)); --KB1L116 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~48 KB1L116 = HB1_address_reg_a[7] & (KB1L115 & (HB1M2392Q) # !KB1L115 & HB1M2342Q) # !HB1_address_reg_a[7] & (KB1L115); --KB1L103 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~47 KB1L103 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M742Q # !HB1_address_reg_a[7] & (HB1M642Q)); --KB1L104 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~48 KB1L104 = HB1_address_reg_a[6] & (KB1L103 & (HB1M792Q) # !KB1L103 & HB1M692Q) # !HB1_address_reg_a[6] & (KB1L103); --KB1L119 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~566 KB1L119 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L116 # !HB1_address_reg_a[11] & (KB1L104)); --KB1L113 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~44 KB1L113 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1942Q # !HB1_address_reg_a[7] & (HB1M1842Q)); --KB1L114 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~45 KB1L114 = HB1_address_reg_a[6] & (KB1L113 & (HB1M1992Q) # !KB1L113 & HB1M1892Q) # !HB1_address_reg_a[6] & (KB1L113); --KB1L101 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~44 KB1L101 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M292Q # !HB1_address_reg_a[6] & (HB1M242Q)); --KB1L102 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~45 KB1L102 = HB1_address_reg_a[7] & (KB1L101 & (HB1M392Q) # !KB1L101 & HB1M342Q) # !HB1_address_reg_a[7] & (KB1L101); --KB1L120 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~567 KB1L120 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L114 # !HB1_address_reg_a[11] & (KB1L102)); --KB1L121 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~568 KB1L121 = KB1L147 # KB1L232 & (KB1L119 # KB1L120); --KB1L117 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~281 KB1L117 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1742Q # !HB1_address_reg_a[7] & (HB1M1642Q)); --KB1L118 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~282 KB1L118 = HB1_address_reg_a[6] & (KB1L117 & (HB1M1792Q) # !KB1L117 & HB1M1692Q) # !HB1_address_reg_a[6] & (KB1L117); --KB1L105 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~281 KB1L105 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M92Q # !HB1_address_reg_a[6] & (HB1M42Q)); --KB1L106 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~282 KB1L106 = HB1_address_reg_a[7] & (KB1L105 & (HB1M192Q) # !KB1L105 & HB1M142Q) # !HB1_address_reg_a[7] & (KB1L105); --KB1L122 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~569 KB1L122 = KB1L236 & (HB1_address_reg_a[11] & KB1L118 # !HB1_address_reg_a[11] & (KB1L106)); --KB1L123 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~570 KB1L123 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2192Q # !HB1_address_reg_a[7] & (HB1M2092Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L124 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~571 KB1L124 = HB1_address_reg_a[6] & (KB1L123) # !HB1_address_reg_a[6] & (KB1L123 & HB1M2142Q # !KB1L123 & (HB1M2042Q)); --KB1L125 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~572 KB1L125 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M492Q # !HB1_address_reg_a[6] & (HB1M442Q)); --KB1L126 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~573 KB1L126 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M592Q # !HB1_address_reg_a[6] & (HB1M542Q)); --KB1L127 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~574 KB1L127 = HB1_address_reg_a[11] & KB1L124 # !HB1_address_reg_a[11] & (KB1L125 # KB1L126); --KB1L128 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~575 KB1L128 = KB1L121 # KB1L122 # KB1L243 & KB1L127; --KB1L18 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5084 KB1L18 = KB1L128 & (KB1L12 # !HB1_address_reg_a[10]) # !KB1L128 & (KB1L17 & HB1_address_reg_a[10]); --KB1L1 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5085 KB1L1 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1_ram_block2a50; --KB1L2 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5086 KB1L2 = HB1_address_reg_a[6] & (HB1_ram_block2a49 # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_ram_block2a48 & !HB1_address_reg_a[7]); --KB1L3 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5087 KB1L3 = !HB1_address_reg_a[9] & (KB1L1 & HB1_address_reg_a[7] & !KB1L2 # !KB1L1 & !HB1_address_reg_a[7] & KB1L2); --KB1L81 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~49 KB1L81 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1_ram_block2a30 # !HB1_address_reg_a[7] & (HB1_ram_block2a28)); --KB1L82 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~50 KB1L82 = HB1_address_reg_a[6] & (KB1L81 & (HB1_ram_block2a31) # !KB1L81 & HB1_ram_block2a29) # !HB1_address_reg_a[6] & (KB1L81); --KB1L79 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~44 KB1L79 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a21 # !HB1_address_reg_a[6] & (HB1_ram_block2a20)); --KB1L80 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~45 KB1L80 = HB1_address_reg_a[7] & (KB1L79 & (HB1_ram_block2a23) # !KB1L79 & HB1_ram_block2a22) # !HB1_address_reg_a[7] & (KB1L79); --KB1L4 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5088 KB1L4 = HB1_address_reg_a[9] & KB1L82 # !HB1_address_reg_a[9] & (KB1L80); --KB1L83 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~407 KB1L83 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a17 # !HB1_address_reg_a[6] & (HB1_ram_block2a16)); --KB1L84 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~408 KB1L84 = HB1_address_reg_a[7] & (KB1L83 & (HB1_ram_block2a19) # !KB1L83 & HB1_ram_block2a18) # !HB1_address_reg_a[7] & (KB1L83); --KB1L5 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5089 KB1L5 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a27 # !HB1_address_reg_a[6] & (HB1_ram_block2a26)); --KB1L6 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5090 KB1L6 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a25 # !HB1_address_reg_a[6] & (HB1_ram_block2a24)); --KB1L7 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5091 KB1L7 = HB1_address_reg_a[9] & (KB1L5 # KB1L6) # !HB1_address_reg_a[9] & KB1L84; --KB1L8 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5092 KB1L8 = HB1_address_reg_a[8] & KB1L4 # !HB1_address_reg_a[8] & (KB1L7); --KB1L87 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~47 KB1L87 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1_ram_block2a46 # !HB1_address_reg_a[7] & (HB1_ram_block2a44)); --KB1L88 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~48 KB1L88 = HB1_address_reg_a[6] & (KB1L87 & (HB1_ram_block2a47) # !KB1L87 & HB1_ram_block2a45) # !HB1_address_reg_a[6] & (KB1L87); --KB1L75 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~47 KB1L75 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a13 # !HB1_address_reg_a[6] & (HB1_ram_block2a12)); --KB1L76 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~48 KB1L76 = HB1_address_reg_a[7] & (KB1L75 & (HB1_ram_block2a15) # !KB1L75 & HB1_ram_block2a14) # !HB1_address_reg_a[7] & (KB1L75); --KB1L91 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~566 KB1L91 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L88 # !HB1_address_reg_a[11] & (KB1L76)); --KB1L85 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~44 KB1L85 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a37 # !HB1_address_reg_a[6] & (HB1_ram_block2a36)); --KB1L86 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~45 KB1L86 = HB1_address_reg_a[7] & (KB1L85 & (HB1_ram_block2a39) # !KB1L85 & HB1_ram_block2a38) # !HB1_address_reg_a[7] & (KB1L85); --KB1L73 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~44 KB1L73 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1_ram_block2a6 # !HB1_address_reg_a[7] & (HB1_ram_block2a4)); --KB1L74 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~45 KB1L74 = HB1_address_reg_a[6] & (KB1L73 & (HB1_ram_block2a7) # !KB1L73 & HB1_ram_block2a5) # !HB1_address_reg_a[6] & (KB1L73); --KB1L92 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~567 KB1L92 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L86 # !HB1_address_reg_a[11] & (KB1L74)); --KB1L93 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~568 KB1L93 = KB1L147 # KB1L232 & (KB1L91 # KB1L92); --KB1L89 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~281 KB1L89 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a33 # !HB1_address_reg_a[6] & (HB1_ram_block2a32)); --KB1L90 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~282 KB1L90 = HB1_address_reg_a[7] & (KB1L89 & (HB1_ram_block2a35) # !KB1L89 & HB1_ram_block2a34) # !HB1_address_reg_a[7] & (KB1L89); --KB1L77 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~281 KB1L77 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1_ram_block2a2 # !HB1_address_reg_a[7] & (HB1_ram_block2a0)); --KB1L78 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~282 KB1L78 = HB1_address_reg_a[6] & (KB1L77 & (HB1_ram_block2a3) # !KB1L77 & HB1_ram_block2a1) # !HB1_address_reg_a[6] & (KB1L77); --KB1L94 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~569 KB1L94 = KB1L236 & (HB1_address_reg_a[11] & KB1L90 # !HB1_address_reg_a[11] & (KB1L78)); --KB1L95 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~570 KB1L95 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1_ram_block2a43 # !HB1_address_reg_a[7] & (HB1_ram_block2a41)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L96 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~571 KB1L96 = HB1_address_reg_a[6] & (KB1L95) # !HB1_address_reg_a[6] & (KB1L95 & HB1_ram_block2a42 # !KB1L95 & (HB1_ram_block2a40)); --KB1L97 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~572 KB1L97 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a9 # !HB1_address_reg_a[6] & (HB1_ram_block2a8)); --KB1L98 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~573 KB1L98 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1_ram_block2a11 # !HB1_address_reg_a[6] & (HB1_ram_block2a10)); --KB1L99 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~574 KB1L99 = HB1_address_reg_a[11] & KB1L96 # !HB1_address_reg_a[11] & (KB1L97 # KB1L98); --KB1L100 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~575 KB1L100 = KB1L93 # KB1L94 # KB1L243 & KB1L99; --KB1L9 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5093 KB1L9 = KB1L100 & (KB1L3 # !HB1_address_reg_a[10]) # !KB1L100 & (KB1L8 & HB1_address_reg_a[10]); --N1L22 is VGA_OSD_RAM:u9|Mux~34 N1L22 = N1_ADDR_dd[1] & (N1_ADDR_dd[0]) # !N1_ADDR_dd[1] & (N1_ADDR_dd[0] & KB1L18 # !N1_ADDR_dd[0] & (KB1L9)); --KB1L28 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5094 KB1L28 = HB1_address_reg_a[8] & !HB1_address_reg_a[7] # !HB1_address_reg_a[8] & HB1_address_reg_a[7] & HB1M2544Q; --KB1L29 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5095 KB1L29 = HB1_address_reg_a[6] & (HB1M2494Q # HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1M2444Q & !HB1_address_reg_a[7]); --KB1L30 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5096 KB1L30 = !HB1_address_reg_a[9] & (KB1L28 & HB1_address_reg_a[7] & !KB1L29 # !KB1L28 & !HB1_address_reg_a[7] & KB1L29); --KB1L166 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~49 KB1L166 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1494Q # !HB1_address_reg_a[6] & (HB1M1444Q)); --KB1L167 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~50 KB1L167 = HB1_address_reg_a[7] & (KB1L166 & (HB1M1594Q) # !KB1L166 & HB1M1544Q) # !HB1_address_reg_a[7] & (KB1L166); --KB1L164 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~44 KB1L164 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1144Q # !HB1_address_reg_a[7] & (HB1M1044Q)); --KB1L165 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~45 KB1L165 = HB1_address_reg_a[6] & (KB1L164 & (HB1M1194Q) # !KB1L164 & HB1M1094Q) # !HB1_address_reg_a[6] & (KB1L164); --KB1L31 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5097 KB1L31 = HB1_address_reg_a[9] & KB1L167 # !HB1_address_reg_a[9] & (KB1L165); --KB1L168 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~407 KB1L168 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M944Q # !HB1_address_reg_a[7] & (HB1M844Q)); --KB1L169 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~408 KB1L169 = HB1_address_reg_a[6] & (KB1L168 & (HB1M994Q) # !KB1L168 & HB1M894Q) # !HB1_address_reg_a[6] & (KB1L168); --KB1L32 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5098 KB1L32 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1394Q # !HB1_address_reg_a[6] & (HB1M1344Q)); --KB1L33 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5099 KB1L33 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M1294Q # !HB1_address_reg_a[6] & (HB1M1244Q)); --KB1L34 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5100 KB1L34 = HB1_address_reg_a[9] & (KB1L32 # KB1L33) # !HB1_address_reg_a[9] & KB1L169; --KB1L35 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5101 KB1L35 = HB1_address_reg_a[8] & KB1L31 # !HB1_address_reg_a[8] & (KB1L34); --KB1L172 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~47 KB1L172 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M2294Q # !HB1_address_reg_a[6] & (HB1M2244Q)); --KB1L173 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~48 KB1L173 = HB1_address_reg_a[7] & (KB1L172 & (HB1M2394Q) # !KB1L172 & HB1M2344Q) # !HB1_address_reg_a[7] & (KB1L172); --KB1L160 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~47 KB1L160 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M744Q # !HB1_address_reg_a[7] & (HB1M644Q)); --KB1L161 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~48 KB1L161 = HB1_address_reg_a[6] & (KB1L160 & (HB1M794Q) # !KB1L160 & HB1M694Q) # !HB1_address_reg_a[6] & (KB1L160); --KB1L176 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~545 KB1L176 = HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L173 # !HB1_address_reg_a[11] & (KB1L161)); --KB1L170 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~44 KB1L170 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1944Q # !HB1_address_reg_a[7] & (HB1M1844Q)); --KB1L171 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~45 KB1L171 = HB1_address_reg_a[6] & (KB1L170 & (HB1M1994Q) # !KB1L170 & HB1M1894Q) # !HB1_address_reg_a[6] & (KB1L170); --KB1L158 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~44 KB1L158 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M294Q # !HB1_address_reg_a[6] & (HB1M244Q)); --KB1L159 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~45 KB1L159 = HB1_address_reg_a[7] & (KB1L158 & (HB1M394Q) # !KB1L158 & HB1M344Q) # !HB1_address_reg_a[7] & (KB1L158); --KB1L177 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~546 KB1L177 = !HB1_address_reg_a[9] & (HB1_address_reg_a[11] & KB1L171 # !HB1_address_reg_a[11] & (KB1L159)); --KB1L178 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~547 KB1L178 = KB1L147 # KB1L232 & (KB1L176 # KB1L177); --KB1L174 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~281 KB1L174 = HB1_address_reg_a[6] & (HB1_address_reg_a[7]) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M1744Q # !HB1_address_reg_a[7] & (HB1M1644Q)); --KB1L175 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~282 KB1L175 = HB1_address_reg_a[6] & (KB1L174 & (HB1M1794Q) # !KB1L174 & HB1M1694Q) # !HB1_address_reg_a[6] & (KB1L174); --KB1L162 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~281 KB1L162 = HB1_address_reg_a[7] & (HB1_address_reg_a[6]) # !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M94Q # !HB1_address_reg_a[6] & (HB1M44Q)); --KB1L163 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~282 KB1L163 = HB1_address_reg_a[7] & (KB1L162 & (HB1M194Q) # !KB1L162 & HB1M144Q) # !HB1_address_reg_a[7] & (KB1L162); --KB1L179 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~548 KB1L179 = KB1L236 & (HB1_address_reg_a[11] & KB1L175 # !HB1_address_reg_a[11] & (KB1L163)); --KB1L180 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~549 KB1L180 = HB1_address_reg_a[6] & (HB1_address_reg_a[7] & HB1M2194Q # !HB1_address_reg_a[7] & (HB1M2094Q)) # !HB1_address_reg_a[6] & (HB1_address_reg_a[7]); --KB1L181 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~550 KB1L181 = HB1_address_reg_a[6] & (KB1L180) # !HB1_address_reg_a[6] & (KB1L180 & HB1M2144Q # !KB1L180 & (HB1M2044Q)); --KB1L182 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~551 KB1L182 = !HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M494Q # !HB1_address_reg_a[6] & (HB1M444Q)); --KB1L183 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~552 KB1L183 = HB1_address_reg_a[7] & (HB1_address_reg_a[6] & HB1M594Q # !HB1_address_reg_a[6] & (HB1M544Q)); --KB1L184 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~553 KB1L184 = HB1_address_reg_a[11] & KB1L181 # !HB1_address_reg_a[11] & (KB1L182 # KB1L183); --KB1L185 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~554 KB1L185 = KB1L178 # KB1L179 # KB1L243 & KB1L184; --KB1L36 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5102 KB1L36 = KB1L185 & (KB1L30 # !HB1_address_reg_a[10]) # !KB1L185 & (KB1L35 & HB1_address_reg_a[10]); --N1L23 is VGA_OSD_RAM:u9|Mux~35 N1L23 = N1_ADDR_dd[1] & (N1L22 & (KB1L36) # !N1L22 & KB1L27) # !N1_ADDR_dd[1] & (N1L22); --N1_ADDR_dd[2] is VGA_OSD_RAM:u9|ADDR_dd[2] N1_ADDR_dd[2] = DFFEAS(N1L11, S2__clk0, KEY[0], , , , , , ); --N1L140 is VGA_OSD_RAM:u9|oRed~83 N1L140 = N1L139 & (N1_ADDR_dd[2] & N1L21 # !N1_ADDR_dd[2] & (N1L23)); --K1_f_VGA is CMD_Decode:u5|f_VGA K1_f_VGA = DFFEAS(K1L196, CLOCK_50, KEY[0], , , , , , ); --K1L66 is CMD_Decode:u5|Decoder~516 K1L66 = K1L75 & K1L76 & K1L149 & K1_f_VGA; --K1L67 is CMD_Decode:u5|Decoder~517 K1L67 = K1L66 & !K1_CMD_Tmp[24] & !K1_CMD_Tmp[25] & !K1_CMD_Tmp[26]; --K1L68 is CMD_Decode:u5|Decoder~518 K1L68 = K1_CMD_Tmp[24] & K1_CMD_Tmp[25] & K1L66 & !K1_CMD_Tmp[26]; --K1L69 is CMD_Decode:u5|Decoder~519 K1L69 = K1_CMD_Tmp[25] & K1L66 & !K1_CMD_Tmp[24] & !K1_CMD_Tmp[26]; --K1L70 is CMD_Decode:u5|Decoder~520 K1L70 = K1_CMD_Tmp[24] & K1L66 & !K1_CMD_Tmp[25] & !K1_CMD_Tmp[26]; --K1L71 is CMD_Decode:u5|Decoder~521 K1L71 = K1_CMD_Tmp[26] & K1L66 & !K1_CMD_Tmp[24] & !K1_CMD_Tmp[25]; --K1L72 is CMD_Decode:u5|Decoder~522 K1L72 = K1_CMD_Tmp[24] & K1_CMD_Tmp[26] & K1L66 & !K1_CMD_Tmp[25]; --Q1L112 is AUDIO_DAC:u11|LRCK_1X_DIV[0]~145 Q1L112 = Q1_LRCK_1X_DIV[0] $ VCC; --Q1L113 is AUDIO_DAC:u11|LRCK_1X_DIV[0]~146 Q1L113 = CARRY(Q1_LRCK_1X_DIV[0]); --Q1L115 is AUDIO_DAC:u11|LRCK_1X_DIV[1]~147 Q1L115 = Q1_LRCK_1X_DIV[1] & !Q1L113 # !Q1_LRCK_1X_DIV[1] & (Q1L113 # GND); --Q1L116 is AUDIO_DAC:u11|LRCK_1X_DIV[1]~148 Q1L116 = CARRY(!Q1L113 # !Q1_LRCK_1X_DIV[1]); --Q1L118 is AUDIO_DAC:u11|LRCK_1X_DIV[2]~149 Q1L118 = Q1_LRCK_1X_DIV[2] & (Q1L116 $ GND) # !Q1_LRCK_1X_DIV[2] & !Q1L116 & VCC; --Q1L119 is AUDIO_DAC:u11|LRCK_1X_DIV[2]~150 Q1L119 = CARRY(Q1_LRCK_1X_DIV[2] & !Q1L116); --Q1L121 is AUDIO_DAC:u11|LRCK_1X_DIV[3]~151 Q1L121 = Q1_LRCK_1X_DIV[3] & !Q1L119 # !Q1_LRCK_1X_DIV[3] & (Q1L119 # GND); --Q1L122 is AUDIO_DAC:u11|LRCK_1X_DIV[3]~152 Q1L122 = CARRY(!Q1L119 # !Q1_LRCK_1X_DIV[3]); --Q1L124 is AUDIO_DAC:u11|LRCK_1X_DIV[4]~153 Q1L124 = Q1_LRCK_1X_DIV[4] & (Q1L122 $ GND) # !Q1_LRCK_1X_DIV[4] & !Q1L122 & VCC; --Q1L125 is AUDIO_DAC:u11|LRCK_1X_DIV[4]~154 Q1L125 = CARRY(Q1_LRCK_1X_DIV[4] & !Q1L122); --Q1L127 is AUDIO_DAC:u11|LRCK_1X_DIV[5]~155 Q1L127 = Q1_LRCK_1X_DIV[5] & !Q1L125 # !Q1_LRCK_1X_DIV[5] & (Q1L125 # GND); --Q1L128 is AUDIO_DAC:u11|LRCK_1X_DIV[5]~156 Q1L128 = CARRY(!Q1L125 # !Q1_LRCK_1X_DIV[5]); --Q1L130 is AUDIO_DAC:u11|LRCK_1X_DIV[6]~157 Q1L130 = Q1_LRCK_1X_DIV[6] & (Q1L128 $ GND) # !Q1_LRCK_1X_DIV[6] & !Q1L128 & VCC; --Q1L131 is AUDIO_DAC:u11|LRCK_1X_DIV[6]~158 Q1L131 = CARRY(Q1_LRCK_1X_DIV[6] & !Q1L128); --Q1L133 is AUDIO_DAC:u11|LRCK_1X_DIV[7]~159 Q1L133 = Q1_LRCK_1X_DIV[7] & !Q1L131 # !Q1_LRCK_1X_DIV[7] & (Q1L131 # GND); --Q1L134 is AUDIO_DAC:u11|LRCK_1X_DIV[7]~160 Q1L134 = CARRY(!Q1L131 # !Q1_LRCK_1X_DIV[7]); --Q1L136 is AUDIO_DAC:u11|LRCK_1X_DIV[8]~161 Q1L136 = Q1_LRCK_1X_DIV[8] $ !Q1L134; --W1_mFL_DATA[5] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[5] W1_mFL_DATA[5] = DFFEAS(X1_oDATA[5], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L28 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[5]~104 W1L28 = K1_oFL_Select[0] & W1_mFL_DATA[5] & !K1_oFL_Select[1]; --Q1_LRCK_2X_DIV[0] is AUDIO_DAC:u11|LRCK_2X_DIV[0] Q1_LRCK_2X_DIV[0] = DFFEAS(Q1L142, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1_LRCK_2X_DIV[1] is AUDIO_DAC:u11|LRCK_2X_DIV[1] Q1_LRCK_2X_DIV[1] = DFFEAS(Q1L145, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1L202 is AUDIO_DAC:u11|LessThan~876 Q1L202 = !Q1_LRCK_2X_DIV[1] # !Q1_LRCK_2X_DIV[0]; --Q1_LRCK_2X_DIV[4] is AUDIO_DAC:u11|LRCK_2X_DIV[4] Q1_LRCK_2X_DIV[4] = DFFEAS(Q1L154, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1_LRCK_2X_DIV[2] is AUDIO_DAC:u11|LRCK_2X_DIV[2] Q1_LRCK_2X_DIV[2] = DFFEAS(Q1L148, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1_LRCK_2X_DIV[3] is AUDIO_DAC:u11|LRCK_2X_DIV[3] Q1_LRCK_2X_DIV[3] = DFFEAS(Q1L151, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1L203 is AUDIO_DAC:u11|LessThan~877 Q1L203 = Q1L202 # !Q1_LRCK_2X_DIV[3] # !Q1_LRCK_2X_DIV[2] # !Q1_LRCK_2X_DIV[4]; --Q1_LRCK_2X_DIV[5] is AUDIO_DAC:u11|LRCK_2X_DIV[5] Q1_LRCK_2X_DIV[5] = DFFEAS(Q1L157, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1_LRCK_2X_DIV[6] is AUDIO_DAC:u11|LRCK_2X_DIV[6] Q1_LRCK_2X_DIV[6] = DFFEAS(Q1L160, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1_LRCK_2X_DIV[7] is AUDIO_DAC:u11|LRCK_2X_DIV[7] Q1_LRCK_2X_DIV[7] = DFFEAS(Q1L163, S2__clk1, B1_oRESET, , , , , Q1L204, ); --Q1L204 is AUDIO_DAC:u11|LessThan~878 Q1L204 = Q1_LRCK_2X_DIV[7] # Q1_LRCK_2X_DIV[6] & (Q1_LRCK_2X_DIV[5] # !Q1L203); --Q1L165 is AUDIO_DAC:u11|LRCK_2X~49 Q1L165 = Q1_LRCK_2X $ Q1L204; --Q1_BCK_DIV[2] is AUDIO_DAC:u11|BCK_DIV[2] Q1_BCK_DIV[2] = DFFEAS(Q1L5, S2__clk1, B1_oRESET, , , , , , ); --Q1_BCK_DIV[1] is AUDIO_DAC:u11|BCK_DIV[1] Q1_BCK_DIV[1] = DFFEAS(Q1L6, S2__clk1, B1_oRESET, , , , , , ); --Q1_BCK_DIV[0] is AUDIO_DAC:u11|BCK_DIV[0] Q1_BCK_DIV[0] = DFFEAS(Q1L7, S2__clk1, B1_oRESET, , , , , , ); --Q1L237 is AUDIO_DAC:u11|oAUD_BCK~37 Q1L237 = Q1_oAUD_BCK $ (Q1_BCK_DIV[2] & (Q1_BCK_DIV[1] # Q1_BCK_DIV[0])); --W1_mFL_DATA[6] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[6] W1_mFL_DATA[6] = DFFEAS(X1_oDATA[6], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L29 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[6]~105 W1L29 = K1_oFL_Select[0] & W1_mFL_DATA[6] & !K1_oFL_Select[1]; --W1_mFL_DATA[7] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[7] W1_mFL_DATA[7] = DFFEAS(X1_oDATA[7], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L30 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[7]~106 W1L30 = K1_oFL_Select[0] & W1_mFL_DATA[7] & !K1_oFL_Select[1]; --W1_mFL_DATA[4] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[4] W1_mFL_DATA[4] = DFFEAS(X1_oDATA[4], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L27 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[4]~107 W1L27 = K1_oFL_Select[0] & W1_mFL_DATA[4] & !K1_oFL_Select[1]; --W1_mFL_DATA[2] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[2] W1_mFL_DATA[2] = DFFEAS(X1_oDATA[2], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L25 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[2]~108 W1L25 = K1_oFL_Select[0] & W1_mFL_DATA[2] & !K1_oFL_Select[1]; --W1_mFL_DATA[1] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[1] W1_mFL_DATA[1] = DFFEAS(X1_oDATA[1], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L24 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[1]~109 W1L24 = K1_oFL_Select[0] & W1_mFL_DATA[1] & !K1_oFL_Select[1]; --W1_mFL_DATA[3] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[3] W1_mFL_DATA[3] = DFFEAS(X1_oDATA[3], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L26 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[3]~110 W1L26 = K1_oFL_Select[0] & W1_mFL_DATA[3] & !K1_oFL_Select[1]; --W1_mFL_DATA[0] is Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[0] W1_mFL_DATA[0] = DFFEAS(X1_oDATA[0], CLOCK_50, KEY[0], , W1L10, , , , ); --W1L23 is Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[0]~111 W1L23 = K1_oFL_Select[0] & W1_mFL_DATA[0] & !K1_oFL_Select[1]; --CB1_DIN2[0] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[0] CB1_DIN2[0] = DFFEAS(CB1_DIN1[0], S1__clk0, KEY[0], , , , , , ); --AB1_OE is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|OE AB1_OE = DFFEAS(AB1_oe4, S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[1] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[1] CB1_DIN2[1] = DFFEAS(CB1_DIN1[1], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[2] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[2] CB1_DIN2[2] = DFFEAS(CB1_DIN1[2], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[3] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[3] CB1_DIN2[3] = DFFEAS(CB1_DIN1[3], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[4] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[4] CB1_DIN2[4] = DFFEAS(CB1_DIN1[4], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[5] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[5] CB1_DIN2[5] = DFFEAS(CB1_DIN1[5], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[6] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[6] CB1_DIN2[6] = DFFEAS(CB1_DIN1[6], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[7] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[7] CB1_DIN2[7] = DFFEAS(CB1_DIN1[7], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[8] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[8] CB1_DIN2[8] = DFFEAS(CB1_DIN1[8], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[9] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[9] CB1_DIN2[9] = DFFEAS(CB1_DIN1[9], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[10] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[10] CB1_DIN2[10] = DFFEAS(CB1_DIN1[10], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[11] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[11] CB1_DIN2[11] = DFFEAS(CB1_DIN1[11], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[12] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[12] CB1_DIN2[12] = DFFEAS(CB1_DIN1[12], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[13] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[13] CB1_DIN2[13] = DFFEAS(CB1_DIN1[13], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[14] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[14] CB1_DIN2[14] = DFFEAS(CB1_DIN1[14], S1__clk0, KEY[0], , , , , , ); --CB1_DIN2[15] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[15] CB1_DIN2[15] = DFFEAS(CB1_DIN1[15], S1__clk0, KEY[0], , , , , , ); --X1_r_DATA[0] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[0] X1_r_DATA[0] = DFFEAS(W1L55, CLOCK_50, , , X1L243, , , , ); --X1L193 is Multi_Flash:u2|Flash_Controller:u1|mDATA[0]~156 X1L193 = X1_ST.P2 # X1_ST.P5 # X1_ST.P4_PRG & X1_r_DATA[0]; --X1_r_DATA[1] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[1] X1_r_DATA[1] = DFFEAS(W1L56, CLOCK_50, , , X1L243, , , , ); --X1L194 is Multi_Flash:u2|Flash_Controller:u1|mDATA[1]~157 X1L194 = X1_ST.P4 # X1_ST.P1 # X1_ST.P4_PRG & X1_r_DATA[1]; --X1_r_DATA[2] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[2] X1_r_DATA[2] = DFFEAS(W1L57, CLOCK_50, , , X1L243, , , , ); --X1L195 is Multi_Flash:u2|Flash_Controller:u1|mDATA[2]~158 X1L195 = X1_ST.P2 # X1_ST.P5 # X1_ST.P4_PRG & X1_r_DATA[2]; --X1_r_DATA[3] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[3] X1_r_DATA[3] = DFFEAS(W1L58, CLOCK_50, , , X1L243, , , , ); --X1L196 is Multi_Flash:u2|Flash_Controller:u1|mDATA[3]~159 X1L196 = X1_ST.P4 # X1_ST.P1 # X1_ST.P4_PRG & X1_r_DATA[3]; --X1_r_DATA[4] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[4] X1_r_DATA[4] = DFFEAS(W1L59, CLOCK_50, , , X1L243, , , , ); --X1L197 is Multi_Flash:u2|Flash_Controller:u1|mDATA[4]~160 X1L197 = X1_ST.P4_PRG & X1_r_DATA[4] # !X1L253 # !X1L137; --X1_r_DATA[5] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[5] X1_r_DATA[5] = DFFEAS(W1L60, CLOCK_50, , , X1L243, , , , ); --X1L198 is Multi_Flash:u2|Flash_Controller:u1|mDATA[5]~161 X1L198 = !X1_ST.P4 & !X1_ST.P1; --X1L199 is Multi_Flash:u2|Flash_Controller:u1|mDATA[5]~162 X1L199 = X1_ST.P3_PRG # X1_ST.P4_PRG & X1_r_DATA[5] # !X1L198; --X1_r_DATA[6] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[6] X1_r_DATA[6] = DFFEAS(W1L61, CLOCK_50, , , X1L243, , , , ); --X1L200 is Multi_Flash:u2|Flash_Controller:u1|mDATA[6]~163 X1L200 = X1_ST.P2 # X1_ST.P5 # X1_ST.P4_PRG & X1_r_DATA[6]; --X1_r_DATA[7] is Multi_Flash:u2|Flash_Controller:u1|r_DATA[7] X1_r_DATA[7] = DFFEAS(W1L62, CLOCK_50, , , X1L243, , , , ); --X1L201 is Multi_Flash:u2|Flash_Controller:u1|mDATA[7]~164 X1L201 = X1_ST.P3_DEV # X1_ST.P4_PRG & X1_r_DATA[7] # !X1L138; --K1_oSR_DATA[0] is CMD_Decode:u5|oSR_DATA[0] K1_oSR_DATA[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, , , K1L425, , , , ); --L1L21 is Multi_Sram:u6|SRAM_DQ~288 L1L21 = K1_oSR_DATA[0] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[1] is CMD_Decode:u5|oSR_DATA[1] K1_oSR_DATA[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, , , K1L425, , , , ); --L1L22 is Multi_Sram:u6|SRAM_DQ~289 L1L22 = K1_oSR_DATA[1] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[2] is CMD_Decode:u5|oSR_DATA[2] K1_oSR_DATA[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, , , K1L425, , , , ); --L1L23 is Multi_Sram:u6|SRAM_DQ~290 L1L23 = K1_oSR_DATA[2] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[3] is CMD_Decode:u5|oSR_DATA[3] K1_oSR_DATA[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, , , K1L425, , , , ); --L1L24 is Multi_Sram:u6|SRAM_DQ~291 L1L24 = K1_oSR_DATA[3] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[4] is CMD_Decode:u5|oSR_DATA[4] K1_oSR_DATA[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, , , K1L425, , , , ); --L1L25 is Multi_Sram:u6|SRAM_DQ~292 L1L25 = K1_oSR_DATA[4] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[5] is CMD_Decode:u5|oSR_DATA[5] K1_oSR_DATA[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, , , K1L425, , , , ); --L1L26 is Multi_Sram:u6|SRAM_DQ~293 L1L26 = K1_oSR_DATA[5] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[6] is CMD_Decode:u5|oSR_DATA[6] K1_oSR_DATA[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, , , K1L425, , , , ); --L1L27 is Multi_Sram:u6|SRAM_DQ~294 L1L27 = K1_oSR_DATA[6] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[7] is CMD_Decode:u5|oSR_DATA[7] K1_oSR_DATA[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, , , K1L425, , , , ); --L1L28 is Multi_Sram:u6|SRAM_DQ~295 L1L28 = K1_oSR_DATA[7] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[8] is CMD_Decode:u5|oSR_DATA[8] K1_oSR_DATA[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, , , K1L425, , , , ); --L1L29 is Multi_Sram:u6|SRAM_DQ~296 L1L29 = K1_oSR_DATA[8] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[9] is CMD_Decode:u5|oSR_DATA[9] K1_oSR_DATA[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, , , K1L425, , , , ); --L1L30 is Multi_Sram:u6|SRAM_DQ~297 L1L30 = K1_oSR_DATA[9] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[10] is CMD_Decode:u5|oSR_DATA[10] K1_oSR_DATA[10] = DFFEAS(K1_CMD_Tmp[18], CLOCK_50, , , K1L425, , , , ); --L1L31 is Multi_Sram:u6|SRAM_DQ~298 L1L31 = K1_oSR_DATA[10] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[11] is CMD_Decode:u5|oSR_DATA[11] K1_oSR_DATA[11] = DFFEAS(K1_CMD_Tmp[19], CLOCK_50, , , K1L425, , , , ); --L1L32 is Multi_Sram:u6|SRAM_DQ~299 L1L32 = K1_oSR_DATA[11] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[12] is CMD_Decode:u5|oSR_DATA[12] K1_oSR_DATA[12] = DFFEAS(K1_CMD_Tmp[20], CLOCK_50, , , K1L425, , , , ); --L1L33 is Multi_Sram:u6|SRAM_DQ~300 L1L33 = K1_oSR_DATA[12] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[13] is CMD_Decode:u5|oSR_DATA[13] K1_oSR_DATA[13] = DFFEAS(K1_CMD_Tmp[21], CLOCK_50, , , K1L425, , , , ); --L1L34 is Multi_Sram:u6|SRAM_DQ~301 L1L34 = K1_oSR_DATA[13] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[14] is CMD_Decode:u5|oSR_DATA[14] K1_oSR_DATA[14] = DFFEAS(K1_CMD_Tmp[22], CLOCK_50, , , K1L425, , , , ); --L1L35 is Multi_Sram:u6|SRAM_DQ~302 L1L35 = K1_oSR_DATA[14] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --K1_oSR_DATA[15] is CMD_Decode:u5|oSR_DATA[15] K1_oSR_DATA[15] = DFFEAS(K1_CMD_Tmp[23], CLOCK_50, , , K1L425, , , , ); --L1L36 is Multi_Sram:u6|SRAM_DQ~303 L1L36 = K1_oSR_DATA[15] & !K1_oSR_Select[1] & !K1_oSR_Select[0]; --MB1L25Q is I2C_AV_Config:u10|I2C_Controller:u0|SDO~reg0 MB1L25Q = DFFEAS(MB1L70, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --U1_oRxD_Ready is USB_JTAG:u1|JTAG_REC:u0|oRxD_Ready U1_oRxD_Ready = DFFEAS(U1L1, F1_mTCK, !TCS, , , , , , ); --F1_Pre_RxD_Ready is USB_JTAG:u1|Pre_RxD_Ready F1_Pre_RxD_Ready = DFFEAS(U1_oRxD_Ready, CLOCK_50, KEY[0], , , , , , ); --F1L4 is USB_JTAG:u1|always1~0 F1L4 = U1_oRxD_Ready & !K1L501 & !F1_Pre_RxD_Ready; --U1_oRxD_DATA[7] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[7] U1_oRxD_DATA[7] = DFFEAS(TDI, F1_mTCK, , , U1L11, , , , ); --F1L15 is USB_JTAG:u1|oRxD_DATA[7]~8 F1L15 = KEY[0] & U1_oRxD_Ready & !K1L501 & !F1_Pre_RxD_Ready; --U1_oRxD_DATA[3] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[3] U1_oRxD_DATA[3] = DFFEAS(U1_rDATA[4], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[4] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[4] U1_oRxD_DATA[4] = DFFEAS(U1_rDATA[5], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[0] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[0] U1_oRxD_DATA[0] = DFFEAS(U1_rDATA[1], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[6] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[6] U1_oRxD_DATA[6] = DFFEAS(U1_rDATA[7], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[2] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[2] U1_oRxD_DATA[2] = DFFEAS(U1_rDATA[3], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[5] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[5] U1_oRxD_DATA[5] = DFFEAS(U1_rDATA[6], F1_mTCK, , , U1L11, , , , ); --U1_oRxD_DATA[1] is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[1] U1_oRxD_DATA[1] = DFFEAS(U1_rDATA[2], F1_mTCK, , , U1L11, , , , ); --K1_oSDR_ADDR[0] is CMD_Decode:u5|oSDR_ADDR[0] K1_oSDR_ADDR[0] = DFFEAS(K1_CMD_Tmp[24], CLOCK_50, , , K1L351, , , , ); --Y1L13 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[0]~330 Y1L13 = K1_oSDR_ADDR[0] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[8] is CMD_Decode:u5|oSDR_ADDR[8] K1_oSDR_ADDR[8] = DFFEAS(K1_CMD_Tmp[32], CLOCK_50, , , K1L351, , , , ); --Y1L21 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[8]~331 Y1L21 = K1_oSDR_ADDR[8] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --BB1_WRITEA is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|WRITEA BB1_WRITEA = DFFEAS(BB1L2, S1__clk0, KEY[0], , , , , , ); --AB1_rp_done is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done AB1_rp_done = DFFEAS(AB1L102, S1__clk0, KEY[0], , AB1L107, , , , ); --AB1_command_done is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_done AB1_command_done = DFFEAS(AB1L81, S1__clk0, KEY[0], , , , , , ); --AB1L55 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~151 AB1L55 = !AB1_do_writea & !AB1_rp_done & !AB1_command_done; --BB1_INIT_REQ is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|INIT_REQ BB1_INIT_REQ = DFFEAS(BB1L19, S1__clk0, KEY[0], , , , , , ); --BB1_REF_REQ is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REF_REQ BB1_REF_REQ = DFFEAS(BB1L32, S1__clk0, KEY[0], , , , , , ); --AB1L91 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_writea~38 AB1L91 = BB1_WRITEA & AB1L55 & !BB1_INIT_REQ & !BB1_REF_REQ; --BB1_READA is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|READA BB1_READA = DFFEAS(BB1L8, S1__clk0, KEY[0], , , , , , ); --AB1L56 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~152 AB1L56 = !AB1_do_reada & !BB1_REF_REQ & !AB1_rp_done & !AB1_command_done; --AB1L86 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_reada~36 AB1L86 = BB1_READA & AB1L56 & !BB1_INIT_REQ; --BB1_LOAD_MODE is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE BB1_LOAD_MODE = DFFEAS(BB1L16, S1__clk0, KEY[0], , , , , , ); --AB1L57 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~153 AB1L57 = BB1_LOAD_MODE & !AB1_do_load_mode & !AB1_command_done; --K1L115 is CMD_Decode:u5|Select~2940 K1L115 = K1_mSDR_ST.100 # !F1_oTxD_Done & K1_mSDR_ST.101; --K1L116 is CMD_Decode:u5|Select~2941 K1L116 = K1_mSDR_ST.010 # K1_mSDR_ST.011 # K1L115 # !K1_mSDR_ST.000; --Z1_DONE is Multi_Sdram:u3|Sdram_Controller:u1|DONE Z1_DONE = DFFEAS(Z1L30, CLOCK_50, KEY[0], , , , , , ); --K1L117 is CMD_Decode:u5|Select~2942 K1L117 = K1_mSDR_WRn & (K1_oSDR_Select[1] # K1_oSDR_Select[0] # Z1_DONE); --K1L118 is CMD_Decode:u5|Select~2943 K1L118 = K1L116 # K1_mSDR_ST.001 & !K1L117; --K1L156 is CMD_Decode:u5|always9~1 K1L156 = K1L151 & K1L157 & K1_CMD_Tmp[52] & !K1_CMD_Tmp[48]; --K1L119 is CMD_Decode:u5|Select~2944 K1L119 = K1_mSDR_Start & (K1L118 # K1L156 & !K1_mSDR_ST.000) # !K1_mSDR_Start & (K1L156 & !K1_mSDR_ST.000); --Y1L52 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_WR~35 Y1L52 = K1_mSDR_WRn & K1_mSDR_Start & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_f_SDR_SEL is CMD_Decode:u5|f_SDR_SEL K1_f_SDR_SEL = DFFEAS(K1L178, CLOCK_50, KEY[0], , , , , , ); --K1L393 is CMD_Decode:u5|oSDR_Select[1]~3 K1L393 = K1L148 & K1_f_SDR_SEL; --Y1_ST.10 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.10 Y1_ST.10 = DFFEAS(Y1L6, CLOCK_50, KEY[0], , , , , , ); --Y1_ST.11 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.11 Y1_ST.11 = DFFEAS(Y1L7, CLOCK_50, KEY[0], , , , , , ); --Y1L11 is Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD~127 Y1L11 = Y1L1 & (Y1_mSDR_RD # !Y1_ST.10 & !Y1_ST.11); --Y1_ST.01 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.01 Y1_ST.01 = DFFEAS(Y1L8, CLOCK_50, KEY[0], , , , , , ); --Y1L12 is Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD~128 Y1L12 = Y1L11 & (Y1_mSDR_RD & !Z1_DONE # !Y1_ST.01); --AB1_CM_ACK is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CM_ACK AB1_CM_ACK = DFFEAS(AB1L9, S1__clk0, KEY[0], , , , , , ); --BB1L58 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|always1~0 BB1L58 = AB1_CM_ACK & !BB1_CMD_ACK; --K1_oSDR_ADDR[1] is CMD_Decode:u5|oSDR_ADDR[1] K1_oSDR_ADDR[1] = DFFEAS(K1_CMD_Tmp[25], CLOCK_50, , , K1L351, , , , ); --Y1L14 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[1]~332 Y1L14 = K1_oSDR_ADDR[1] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[9] is CMD_Decode:u5|oSDR_ADDR[9] K1_oSDR_ADDR[9] = DFFEAS(K1_CMD_Tmp[33], CLOCK_50, , , K1L351, , , , ); --Y1L22 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[9]~333 Y1L22 = K1_oSDR_ADDR[9] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[2] is CMD_Decode:u5|oSDR_ADDR[2] K1_oSDR_ADDR[2] = DFFEAS(K1_CMD_Tmp[26], CLOCK_50, , , K1L351, , , , ); --Y1L15 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[2]~334 Y1L15 = K1_oSDR_ADDR[2] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[10] is CMD_Decode:u5|oSDR_ADDR[10] K1_oSDR_ADDR[10] = DFFEAS(K1_CMD_Tmp[34], CLOCK_50, , , K1L351, , , , ); --Y1L23 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[10]~335 Y1L23 = K1_oSDR_ADDR[10] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[11] is CMD_Decode:u5|oSDR_ADDR[11] K1_oSDR_ADDR[11] = DFFEAS(K1_CMD_Tmp[35], CLOCK_50, , , K1L351, , , , ); --Y1L24 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[11]~336 Y1L24 = K1_oSDR_ADDR[11] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[3] is CMD_Decode:u5|oSDR_ADDR[3] K1_oSDR_ADDR[3] = DFFEAS(K1_CMD_Tmp[27], CLOCK_50, , , K1L351, , , , ); --Y1L16 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[3]~337 Y1L16 = K1_oSDR_ADDR[3] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[4] is CMD_Decode:u5|oSDR_ADDR[4] K1_oSDR_ADDR[4] = DFFEAS(K1_CMD_Tmp[28], CLOCK_50, , , K1L351, , , , ); --Y1L17 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[4]~338 Y1L17 = K1_oSDR_ADDR[4] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[12] is CMD_Decode:u5|oSDR_ADDR[12] K1_oSDR_ADDR[12] = DFFEAS(K1_CMD_Tmp[36], CLOCK_50, , , K1L351, , , , ); --Y1L25 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[12]~339 Y1L25 = K1_oSDR_ADDR[12] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[5] is CMD_Decode:u5|oSDR_ADDR[5] K1_oSDR_ADDR[5] = DFFEAS(K1_CMD_Tmp[29], CLOCK_50, , , K1L351, , , , ); --Y1L18 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[5]~340 Y1L18 = K1_oSDR_ADDR[5] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[13] is CMD_Decode:u5|oSDR_ADDR[13] K1_oSDR_ADDR[13] = DFFEAS(K1_CMD_Tmp[37], CLOCK_50, , , K1L351, , , , ); --Y1L26 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[13]~341 Y1L26 = K1_oSDR_ADDR[13] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[14] is CMD_Decode:u5|oSDR_ADDR[14] K1_oSDR_ADDR[14] = DFFEAS(K1_CMD_Tmp[38], CLOCK_50, , , K1L351, , , , ); --Y1L27 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[14]~342 Y1L27 = K1_oSDR_ADDR[14] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[6] is CMD_Decode:u5|oSDR_ADDR[6] K1_oSDR_ADDR[6] = DFFEAS(K1_CMD_Tmp[30], CLOCK_50, , , K1L351, , , , ); --Y1L19 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[6]~343 Y1L19 = K1_oSDR_ADDR[6] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[15] is CMD_Decode:u5|oSDR_ADDR[15] K1_oSDR_ADDR[15] = DFFEAS(K1_CMD_Tmp[39], CLOCK_50, , , K1L351, , , , ); --Y1L28 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[15]~344 Y1L28 = K1_oSDR_ADDR[15] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[7] is CMD_Decode:u5|oSDR_ADDR[7] K1_oSDR_ADDR[7] = DFFEAS(K1_CMD_Tmp[31], CLOCK_50, , , K1L351, , , , ); --Y1L20 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[7]~345 Y1L20 = K1_oSDR_ADDR[7] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[16] is CMD_Decode:u5|oSDR_ADDR[16] K1_oSDR_ADDR[16] = DFFEAS(K1_CMD_Tmp[40], CLOCK_50, , , K1L351, , , , ); --Y1L29 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[16]~346 Y1L29 = K1_oSDR_ADDR[16] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[17] is CMD_Decode:u5|oSDR_ADDR[17] K1_oSDR_ADDR[17] = DFFEAS(K1_CMD_Tmp[41], CLOCK_50, , , K1L351, , , , ); --Y1L30 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[17]~347 Y1L30 = K1_oSDR_ADDR[17] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --BB1_PRECHARGE is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|PRECHARGE BB1_PRECHARGE = DFFEAS(BB1L27, S1__clk0, KEY[0], , , , , , ); --AB1L58 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~154 AB1L58 = BB1_PRECHARGE & !AB1_do_precharge & !AB1_command_done; --K1_oSDR_ADDR[18] is CMD_Decode:u5|oSDR_ADDR[18] K1_oSDR_ADDR[18] = DFFEAS(K1_CMD_Tmp[42], CLOCK_50, , , K1L351, , , , ); --Y1L31 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[18]~348 Y1L31 = K1_oSDR_ADDR[18] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --AB1_rw_shift[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_shift[0] AB1_rw_shift[0] = DFFEAS(AB1L121, S1__clk0, KEY[0], , , , , , ); --AB1L89 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_rw~49 AB1L89 = AB1_do_writea & AB1_do_rw # !AB1_do_writea & (AB1_do_reada & AB1_do_rw # !AB1_do_reada & (AB1_rw_shift[0])); --K1_oSDR_ADDR[19] is CMD_Decode:u5|oSDR_ADDR[19] K1_oSDR_ADDR[19] = DFFEAS(K1_CMD_Tmp[43], CLOCK_50, , , K1L351, , , , ); --Y1L32 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[19]~349 Y1L32 = K1_oSDR_ADDR[19] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --AB1L98 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|oe4~678 AB1L98 = !AB1_do_reada & !AB1_do_refresh; --BB1_REFRESH is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REFRESH BB1_REFRESH = DFFEAS(BB1L30, S1__clk0, KEY[0], , , , , , ); --AB1L59 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~155 AB1L59 = AB1L55 & AB1L98 & (BB1_REF_REQ # BB1_REFRESH); --AB1L116 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag~36 AB1L116 = !AB1_do_writea & !AB1_do_load_mode & !AB1_do_precharge & !AB1_do_refresh; --AB1L117 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag~37 AB1L117 = AB1_do_reada # AB1_rw_flag & AB1L116; --AB1L99 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|oe4~679 AB1L99 = AB1_oe4 & !AB1_do_reada & !AB1_do_precharge & !AB1_do_refresh; --Z1_PM_STOP is Multi_Sdram:u3|Sdram_Controller:u1|PM_STOP Z1_PM_STOP = DFFEAS(Z1L39, S1__clk0, , , , , , , ); --AB1_do_initial is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_initial AB1_do_initial = DFFEAS(BB1_INIT_REQ, S1__clk0, KEY[0], , , , , , ); --AB1L100 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|oe4~680 AB1L100 = AB1_do_writea # AB1L99 & !Z1_PM_STOP & !AB1_do_initial; --K1_oSDR_ADDR[20] is CMD_Decode:u5|oSDR_ADDR[20] K1_oSDR_ADDR[20] = DFFEAS(K1_CMD_Tmp[44], CLOCK_50, , , K1L351, , , , ); --Y1L33 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[20]~350 Y1L33 = K1_oSDR_ADDR[20] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_ADDR[21] is CMD_Decode:u5|oSDR_ADDR[21] K1_oSDR_ADDR[21] = DFFEAS(K1_CMD_Tmp[45], CLOCK_50, , , K1L351, , , , ); --Y1L34 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_ADDR[21]~351 Y1L34 = K1_oSDR_ADDR[21] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --Q1_LRCK_4X_DIV[0] is AUDIO_DAC:u11|LRCK_4X_DIV[0] Q1_LRCK_4X_DIV[0] = DFFEAS(Q1L169, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1_LRCK_4X_DIV[1] is AUDIO_DAC:u11|LRCK_4X_DIV[1] Q1_LRCK_4X_DIV[1] = DFFEAS(Q1L172, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1_LRCK_4X_DIV[2] is AUDIO_DAC:u11|LRCK_4X_DIV[2] Q1_LRCK_4X_DIV[2] = DFFEAS(Q1L175, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1_LRCK_4X_DIV[3] is AUDIO_DAC:u11|LRCK_4X_DIV[3] Q1_LRCK_4X_DIV[3] = DFFEAS(Q1L178, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1L205 is AUDIO_DAC:u11|LessThan~879 Q1L205 = !Q1_LRCK_4X_DIV[3] # !Q1_LRCK_4X_DIV[2] # !Q1_LRCK_4X_DIV[1] # !Q1_LRCK_4X_DIV[0]; --Q1_LRCK_4X_DIV[4] is AUDIO_DAC:u11|LRCK_4X_DIV[4] Q1_LRCK_4X_DIV[4] = DFFEAS(Q1L181, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1_LRCK_4X_DIV[5] is AUDIO_DAC:u11|LRCK_4X_DIV[5] Q1_LRCK_4X_DIV[5] = DFFEAS(Q1L184, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1_LRCK_4X_DIV[6] is AUDIO_DAC:u11|LRCK_4X_DIV[6] Q1_LRCK_4X_DIV[6] = DFFEAS(Q1L187, S2__clk1, B1_oRESET, , , , , Q1L206, ); --Q1L206 is AUDIO_DAC:u11|LessThan~880 Q1L206 = Q1_LRCK_4X_DIV[6] # Q1_LRCK_4X_DIV[5] & (Q1_LRCK_4X_DIV[4] # !Q1L205); --Q1L189 is AUDIO_DAC:u11|LRCK_4X~47 Q1L189 = Q1_LRCK_4X $ Q1L206; --K1L120 is CMD_Decode:u5|Select~2945 K1L120 = !K1_oFL_CMD[0] & !K1_oFL_CMD[2] # !K1_mFL_ST.101 # !W1L72; --K1L121 is CMD_Decode:u5|Select~2946 K1L121 = !K1_mFL_ST.111 # !F1_oTxD_Done; --K1L122 is CMD_Decode:u5|Select~2947 K1L122 = K1L120 & K1L121 & (K1_mFL_ST.000 # K1L150); --K1L195 is CMD_Decode:u5|f_VGA~56 K1L195 = K1_CMD_Tmp[40] & K1L194 & K1L193 & !K1_CMD_Tmp[44]; --K1L160 is CMD_Decode:u5|f_FLASH~141 K1L160 = K1_f_FLASH & K1L122 # !K1_f_FLASH & (K1L189 & K1L195); --K1L183 is CMD_Decode:u5|f_SETUP~49 K1L183 = K1_CMD_Tmp[42] & K1L176 & !K1_CMD_Tmp[40] & !K1_CMD_Tmp[44]; --K1L162 is CMD_Decode:u5|f_FL_SEL~31 K1L162 = K1_CMD_Tmp[41] & !K1_CMD_Tmp[46]; --K1L163 is CMD_Decode:u5|f_FL_SEL~32 K1L163 = K1_CMD_Tmp[45] & K1L183 & K1L162 & !K1_f_FL_SEL; --W1L7 is Multi_Flash:u2|Flash_Multiplexer:u0|ST~165 W1L7 = W1_ST.10 & (K1_oFL_Select[0] # K1_oFL_Select[1]); --X1L215 is Multi_Flash:u2|Flash_Controller:u1|oReady~18 X1L215 = X1_mFinish & !X1_mStart; --W1_ST.00 is Multi_Flash:u2|Flash_Multiplexer:u0|ST.00 W1_ST.00 = DFFEAS(W1L9, CLOCK_50, KEY[0], , , , , , ); --W1L8 is Multi_Flash:u2|Flash_Multiplexer:u0|ST~166 W1L8 = W1L1 & (W1_ST.01 & !X1L215 # !W1_ST.00); --X1_CMD_Period[19] is Multi_Flash:u2|Flash_Controller:u1|CMD_Period[19] X1_CMD_Period[19] = DFFEAS(X1L82, CLOCK_50, , , , , , , ); --X1_Cont_Finish[19] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[19] X1_Cont_Finish[19] = DFFEAS(X1L74, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L112 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1958 X1L112 = X1_CMD_Period[19] & !X1_Cont_Finish[19]; --X1_Cont_Finish[10] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[10] X1_Cont_Finish[10] = DFFEAS(X1L47, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[11] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[11] X1_Cont_Finish[11] = DFFEAS(X1L50, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[12] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[12] X1_Cont_Finish[12] = DFFEAS(X1L53, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[13] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[13] X1_Cont_Finish[13] = DFFEAS(X1L56, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L113 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1959 X1L113 = !X1_Cont_Finish[10] & !X1_Cont_Finish[11] & !X1_Cont_Finish[12] & !X1_Cont_Finish[13]; --X1_CMD_Period[2] is Multi_Flash:u2|Flash_Controller:u1|CMD_Period[2] X1_CMD_Period[2] = DFFEAS(X1L254, CLOCK_50, , , , , , , ); --X1_CMD_Period[1] is Multi_Flash:u2|Flash_Controller:u1|CMD_Period[1] X1_CMD_Period[1] = DFFEAS(X1_r_CMD[2], CLOCK_50, , , , , , , ); --X1_Cont_Finish[1] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[1] X1_Cont_Finish[1] = DFFEAS(X1L20, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[0] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[0] X1_Cont_Finish[0] = DFFEAS(X1L17, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L114 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1960 X1L114 = !X1_Cont_Finish[0] # !X1_Cont_Finish[1]; --X1_Cont_Finish[2] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[2] X1_Cont_Finish[2] = DFFEAS(X1L23, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L115 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1961 X1L115 = X1_CMD_Period[2] & (X1_CMD_Period[1] & X1L114 # !X1_Cont_Finish[2]) # !X1_CMD_Period[2] & X1_CMD_Period[1] & X1L114 & !X1_Cont_Finish[2]; --X1_Cont_Finish[16] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[16] X1_Cont_Finish[16] = DFFEAS(X1L65, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[15] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[15] X1_Cont_Finish[15] = DFFEAS(X1L62, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[14] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[14] X1_Cont_Finish[14] = DFFEAS(X1L59, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L116 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1962 X1L116 = !X1_Cont_Finish[19] & !X1_Cont_Finish[16] & !X1_Cont_Finish[15] & !X1_Cont_Finish[14]; --X1_Cont_Finish[9] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[9] X1_Cont_Finish[9] = DFFEAS(X1L44, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[8] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[8] X1_Cont_Finish[8] = DFFEAS(X1L41, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[7] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[7] X1_Cont_Finish[7] = DFFEAS(X1L38, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[6] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[6] X1_Cont_Finish[6] = DFFEAS(X1L35, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L117 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1963 X1L117 = !X1_Cont_Finish[9] & !X1_Cont_Finish[8] & !X1_Cont_Finish[7] & !X1_Cont_Finish[6]; --X1_Cont_Finish[5] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[5] X1_Cont_Finish[5] = DFFEAS(X1L32, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[4] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[4] X1_Cont_Finish[4] = DFFEAS(X1L29, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[3] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[3] X1_Cont_Finish[3] = DFFEAS(X1L26, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L118 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1964 X1L118 = X1L117 & !X1_Cont_Finish[5] & !X1_Cont_Finish[4] & !X1_Cont_Finish[3]; --X1L119 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1965 X1L119 = X1L115 & (X1_CMD_Period[19] # X1L116 & X1L118); --X1L120 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1966 X1L120 = !X1_Cont_Finish[6] # !X1_Cont_Finish[7] # !X1_Cont_Finish[8] # !X1_Cont_Finish[9]; --X1L121 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1967 X1L121 = X1L120 # !X1_Cont_Finish[3] # !X1_Cont_Finish[4] # !X1_Cont_Finish[5]; --X1L122 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1968 X1L122 = X1L113 & (X1L119 # X1_CMD_Period[19] & X1L121); --X1L123 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1969 X1L123 = X1_CMD_Period[19] & (!X1_Cont_Finish[14] # !X1_Cont_Finish[15] # !X1_Cont_Finish[16]); --X1_Cont_Finish[17] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[17] X1_Cont_Finish[17] = DFFEAS(X1L68, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[18] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[18] X1_Cont_Finish[18] = DFFEAS(X1L71, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L124 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1970 X1L124 = !X1_Cont_Finish[17] & !X1_Cont_Finish[18] & (X1L122 # X1L123); --X1_Cont_Finish[20] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[20] X1_Cont_Finish[20] = DFFEAS(X1L77, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1_Cont_Finish[21] is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[21] X1_Cont_Finish[21] = DFFEAS(X1L80, CLOCK_50, KEY[0], , X1_mACT, , , X1_mStart, ); --X1L125 is Multi_Flash:u2|Flash_Controller:u1|LessThan~1971 X1L125 = !X1_Cont_Finish[20] & !X1_Cont_Finish[21] & (X1L112 # X1L124); --X1L203 is Multi_Flash:u2|Flash_Controller:u1|mFinish~20 X1L203 = X1_mFinish # !X1L125; --K1_mFL_ST.100 is CMD_Decode:u5|mFL_ST.100 K1_mFL_ST.100 = DFFEAS(K1L135, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1L123 is CMD_Decode:u5|Select~2948 K1L123 = K1_mFL_ST.100 # K1_mFL_ST.101 & !W1L72; --K1_mFL_ST.010 is CMD_Decode:u5|mFL_ST.010 K1_mFL_ST.010 = DFFEAS(K1L136, CLOCK_50, KEY[0], , K1_f_FLASH, , , , ); --K1L124 is CMD_Decode:u5|Select~2949 K1L124 = K1_mFL_ST.010 # K1_mFL_ST.011 & !W1L72; --K1L125 is CMD_Decode:u5|Select~2950 K1L125 = K1L150 & (K1_mFL_ST.001 & !W1L72 # !K1_mFL_ST.000) # !K1L150 & K1_mFL_ST.001 & (!W1L72); --K1L126 is CMD_Decode:u5|Select~2951 K1L126 = W1L72 & K1_mFL_ST.101 & !K1_oFL_CMD[0] & !K1_oFL_CMD[2]; --K1L127 is CMD_Decode:u5|Select~2952 K1L127 = K1_mFL_ST.110 # K1_mFL_ST.111 & !F1_oTxD_Done; --X1_Start_Delay[2] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[2] X1_Start_Delay[2] = DFFEAS(X1L159, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[1] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[1] X1_Start_Delay[1] = DFFEAS(X1L156, CLOCK_50, KEY[0], , , , , X1L83, ); --X1_Start_Delay[0] is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[0] X1_Start_Delay[0] = DFFEAS(X1L153, CLOCK_50, KEY[0], , , , , X1L83, ); --X1L153 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[0]~201 X1L153 = X1L111 & X1_Start_Delay[0] & VCC # !X1L111 & (X1_Start_Delay[0] $ VCC); --X1L154 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[0]~202 X1L154 = CARRY(!X1L111 & X1_Start_Delay[0]); --X1L156 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[1]~203 X1L156 = X1_Start_Delay[1] & !X1L154 # !X1_Start_Delay[1] & (X1L154 # GND); --X1L157 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[1]~204 X1L157 = CARRY(!X1L154 # !X1_Start_Delay[1]); --X1L159 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[2]~205 X1L159 = X1_Start_Delay[2] & (X1L157 $ GND) # !X1_Start_Delay[2] & !X1L157 & VCC; --X1L160 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[2]~206 X1L160 = CARRY(X1_Start_Delay[2] & !X1L157); --X1L162 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[3]~207 X1L162 = X1_Start_Delay[3] & !X1L160 # !X1_Start_Delay[3] & (X1L160 # GND); --X1L163 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[3]~208 X1L163 = CARRY(!X1L160 # !X1_Start_Delay[3]); --X1L165 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[4]~209 X1L165 = X1_Start_Delay[4] & (X1L163 $ GND) # !X1_Start_Delay[4] & !X1L163 & VCC; --X1L166 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[4]~210 X1L166 = CARRY(X1_Start_Delay[4] & !X1L163); --X1L168 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[5]~211 X1L168 = X1_Start_Delay[5] & !X1L166 # !X1_Start_Delay[5] & (X1L166 # GND); --X1L169 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[5]~212 X1L169 = CARRY(!X1L166 # !X1_Start_Delay[5]); --X1L171 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[6]~213 X1L171 = X1_Start_Delay[6] & (X1L169 $ GND) # !X1_Start_Delay[6] & !X1L169 & VCC; --X1L172 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[6]~214 X1L172 = CARRY(X1_Start_Delay[6] & !X1L169); --X1L174 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[7]~215 X1L174 = X1_Start_Delay[7] & !X1L172 # !X1_Start_Delay[7] & (X1L172 # GND); --X1L175 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[7]~216 X1L175 = CARRY(!X1L172 # !X1_Start_Delay[7]); --X1L177 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[8]~217 X1L177 = X1_Start_Delay[8] & (X1L175 $ GND) # !X1_Start_Delay[8] & !X1L175 & VCC; --X1L178 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[8]~218 X1L178 = CARRY(X1_Start_Delay[8] & !X1L175); --X1L180 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[9]~219 X1L180 = X1_Start_Delay[9] & !X1L178 # !X1_Start_Delay[9] & (X1L178 # GND); --X1L181 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[9]~220 X1L181 = CARRY(!X1L178 # !X1_Start_Delay[9]); --X1L183 is Multi_Flash:u2|Flash_Controller:u1|Start_Delay[10]~221 X1L183 = X1_Start_Delay[10] $ !X1L181; --X1_Cont_DIV[2] is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[2] X1_Cont_DIV[2] = DFFEAS(X1L13, CLOCK_50, KEY[0], , , , , , ); --K1L80 is CMD_Decode:u5|Equal~635 K1L80 = K1_CMD_Tmp[60] & K1_CMD_Tmp[57] & K1L78 & !K1_CMD_Tmp[56]; --B1L3 is Reset_Delay:d0|Cont[0]~1092 B1L3 = B1_Cont[0] $ VCC; --B1L4 is Reset_Delay:d0|Cont[0]~1093 B1L4 = CARRY(B1_Cont[0]); --B1L6 is Reset_Delay:d0|Cont[1]~1094 B1L6 = B1_Cont[1] & !B1L4 # !B1_Cont[1] & (B1L4 # GND); --B1L7 is Reset_Delay:d0|Cont[1]~1095 B1L7 = CARRY(!B1L4 # !B1_Cont[1]); --B1L9 is Reset_Delay:d0|Cont[2]~1096 B1L9 = B1_Cont[2] & (B1L7 $ GND) # !B1_Cont[2] & !B1L7 & VCC; --B1L10 is Reset_Delay:d0|Cont[2]~1097 B1L10 = CARRY(B1_Cont[2] & !B1L7); --B1L12 is Reset_Delay:d0|Cont[3]~1098 B1L12 = B1_Cont[3] & !B1L10 # !B1_Cont[3] & (B1L10 # GND); --B1L13 is Reset_Delay:d0|Cont[3]~1099 B1L13 = CARRY(!B1L10 # !B1_Cont[3]); --B1L15 is Reset_Delay:d0|Cont[4]~1100 B1L15 = B1_Cont[4] & (B1L13 $ GND) # !B1_Cont[4] & !B1L13 & VCC; --B1L16 is Reset_Delay:d0|Cont[4]~1101 B1L16 = CARRY(B1_Cont[4] & !B1L13); --B1L18 is Reset_Delay:d0|Cont[5]~1102 B1L18 = B1_Cont[5] & !B1L16 # !B1_Cont[5] & (B1L16 # GND); --B1L19 is Reset_Delay:d0|Cont[5]~1103 B1L19 = CARRY(!B1L16 # !B1_Cont[5]); --B1L21 is Reset_Delay:d0|Cont[6]~1104 B1L21 = B1_Cont[6] & (B1L19 $ GND) # !B1_Cont[6] & !B1L19 & VCC; --B1L22 is Reset_Delay:d0|Cont[6]~1105 B1L22 = CARRY(B1_Cont[6] & !B1L19); --B1L24 is Reset_Delay:d0|Cont[7]~1106 B1L24 = B1_Cont[7] & !B1L22 # !B1_Cont[7] & (B1L22 # GND); --B1L25 is Reset_Delay:d0|Cont[7]~1107 B1L25 = CARRY(!B1L22 # !B1_Cont[7]); --B1L27 is Reset_Delay:d0|Cont[8]~1108 B1L27 = B1_Cont[8] & (B1L25 $ GND) # !B1_Cont[8] & !B1L25 & VCC; --B1L28 is Reset_Delay:d0|Cont[8]~1109 B1L28 = CARRY(B1_Cont[8] & !B1L25); --B1L30 is Reset_Delay:d0|Cont[9]~1110 B1L30 = B1_Cont[9] & !B1L28 # !B1_Cont[9] & (B1L28 # GND); --B1L31 is Reset_Delay:d0|Cont[9]~1111 B1L31 = CARRY(!B1L28 # !B1_Cont[9]); --B1L33 is Reset_Delay:d0|Cont[10]~1112 B1L33 = B1_Cont[10] & (B1L31 $ GND) # !B1_Cont[10] & !B1L31 & VCC; --B1L34 is Reset_Delay:d0|Cont[10]~1113 B1L34 = CARRY(B1_Cont[10] & !B1L31); --B1L36 is Reset_Delay:d0|Cont[11]~1114 B1L36 = B1_Cont[11] & !B1L34 # !B1_Cont[11] & (B1L34 # GND); --B1L37 is Reset_Delay:d0|Cont[11]~1115 B1L37 = CARRY(!B1L34 # !B1_Cont[11]); --B1L39 is Reset_Delay:d0|Cont[12]~1116 B1L39 = B1_Cont[12] & (B1L37 $ GND) # !B1_Cont[12] & !B1L37 & VCC; --B1L40 is Reset_Delay:d0|Cont[12]~1117 B1L40 = CARRY(B1_Cont[12] & !B1L37); --B1L42 is Reset_Delay:d0|Cont[13]~1118 B1L42 = B1_Cont[13] & !B1L40 # !B1_Cont[13] & (B1L40 # GND); --B1L43 is Reset_Delay:d0|Cont[13]~1119 B1L43 = CARRY(!B1L40 # !B1_Cont[13]); --B1L45 is Reset_Delay:d0|Cont[14]~1120 B1L45 = B1_Cont[14] & (B1L43 $ GND) # !B1_Cont[14] & !B1L43 & VCC; --B1L46 is Reset_Delay:d0|Cont[14]~1121 B1L46 = CARRY(B1_Cont[14] & !B1L43); --B1L48 is Reset_Delay:d0|Cont[15]~1122 B1L48 = B1_Cont[15] & !B1L46 # !B1_Cont[15] & (B1L46 # GND); --B1L49 is Reset_Delay:d0|Cont[15]~1123 B1L49 = CARRY(!B1L46 # !B1_Cont[15]); --B1L51 is Reset_Delay:d0|Cont[16]~1124 B1L51 = B1_Cont[16] & (B1L49 $ GND) # !B1_Cont[16] & !B1L49 & VCC; --B1L52 is Reset_Delay:d0|Cont[16]~1125 B1L52 = CARRY(B1_Cont[16] & !B1L49); --B1L54 is Reset_Delay:d0|Cont[17]~1126 B1L54 = B1_Cont[17] & !B1L52 # !B1_Cont[17] & (B1L52 # GND); --B1L55 is Reset_Delay:d0|Cont[17]~1127 B1L55 = CARRY(!B1L52 # !B1_Cont[17]); --B1L57 is Reset_Delay:d0|Cont[18]~1128 B1L57 = B1_Cont[18] & (B1L55 $ GND) # !B1_Cont[18] & !B1L55 & VCC; --B1L58 is Reset_Delay:d0|Cont[18]~1129 B1L58 = CARRY(B1_Cont[18] & !B1L55); --B1L60 is Reset_Delay:d0|Cont[19]~1130 B1L60 = B1_Cont[19] $ B1L58; --V1L1 is USB_JTAG:u1|JTAG_TRANS:u1|Equal~74 V1L1 = V1_rCont[2] & V1_rCont[0] & V1_rCont[1]; --K1L128 is CMD_Decode:u5|Select~2953 K1L128 = F1_oTxD_Done & !K1_mSDR_ST.101 & (!K1L117 # !K1_mSDR_ST.001) # !F1_oTxD_Done & (!K1L117 # !K1_mSDR_ST.001); --K1L129 is CMD_Decode:u5|Select~2954 K1L129 = K1L128 & (K1_mSDR_ST.000 # K1L156); --K1L130 is CMD_Decode:u5|Select~2955 K1L130 = !K1_oSDR_Select[1] & !K1_oSDR_Select[0] & !Z1_DONE; --K1L131 is CMD_Decode:u5|Select~2956 K1L131 = K1_mSDR_ST.001 & (K1L130 # K1L156 & !K1_mSDR_ST.000) # !K1_mSDR_ST.001 & (K1L156 & !K1_mSDR_ST.000); --K1L132 is CMD_Decode:u5|Select~2957 K1L132 = K1_mSDR_ST.010 # K1_mSDR_ST.011 & !F1_oTxD_Done; --K1L173 is CMD_Decode:u5|f_SDRAM~171 K1L173 = K1_f_SDRAM & K1L129 # !K1_f_SDRAM & (K1L165 & K1L175); --K1L171 is CMD_Decode:u5|f_PS2~218 K1L171 = K1_f_PS2 & (!K1_mPS2_ST.001 # !F1_oTxD_Done) # !K1_f_PS2 & K1L170; --K1L206 is CMD_Decode:u5|mPS2_ST~61 K1L206 = K1_mPS2_ST.001 & (!K1_f_PS2 # !F1_oTxD_Done) # !K1_mPS2_ST.001 & (K1_f_PS2); --K1L184 is CMD_Decode:u5|f_SETUP~50 K1L184 = K1_CMD_Tmp[46] & !K1_CMD_Tmp[41]; --K1L185 is CMD_Decode:u5|f_SETUP~51 K1L185 = K1L183 & K1L184 & !K1_CMD_Tmp[45] & !K1_f_SETUP; --X1L190 is Multi_Flash:u2|Flash_Controller:u1|always3~0 X1L190 = X1_ST.READ & X1_mACT; --Z1_mDATAOUT[13] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[13] Z1_mDATAOUT[13] = DFFEAS(A1L61, S1__clk0, , , , , , , ); --Z1_mDATAOUT[5] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[5] Z1_mDATAOUT[5] = DFFEAS(A1L45, S1__clk0, , , , , , , ); --K1L133 is CMD_Decode:u5|Select~2958 K1L133 = F1_oTxD_Done & K1_mSDR_ST.011; --K1L134 is CMD_Decode:u5|Select~2959 K1L134 = K1_mSDR_ST.001 & !K1_mSDR_WRn & !K1L130; --J1_q[7] is ps2_keyboard:u4|q[7] J1_q[7] = DFFEAS(J1L131, CLOCK_50, , , J1L124, , , , ); --J1_q[6] is ps2_keyboard:u4|q[6] J1_q[6] = DFFEAS(J1L132, CLOCK_50, , , J1L124, , , , ); --J1_q[5] is ps2_keyboard:u4|q[5] J1_q[5] = DFFEAS(J1L133, CLOCK_50, , , J1L124, , , , ); --J1_q[8] is ps2_keyboard:u4|q[8] J1_q[8] = DFFEAS(J1L134, CLOCK_50, , , J1L124, , , , ); --J1L2 is ps2_keyboard:u4|Equal~8653 J1L2 = J1_q[7] & !J1_q[6] & !J1_q[5] & !J1_q[8]; --J1_q[3] is ps2_keyboard:u4|q[3] J1_q[3] = DFFEAS(J1L135, CLOCK_50, , , J1L124, , , , ); --J1_q[1] is ps2_keyboard:u4|q[1] J1_q[1] = DFFEAS(J1L136, CLOCK_50, , , J1L124, , , , ); --J1L3 is ps2_keyboard:u4|Equal~8654 J1L3 = J1_q[3] & !J1_q[1]; --J1_left_shift_key is ps2_keyboard:u4|left_shift_key J1_left_shift_key = DFFEAS(J1L91, CLOCK_50, , , , , , !KEY[0], ); --J1_right_shift_key is ps2_keyboard:u4|right_shift_key J1_right_shift_key = DFFEAS(J1L246, CLOCK_50, , , , , , !KEY[0], ); --J1_q[2] is ps2_keyboard:u4|q[2] J1_q[2] = DFFEAS(J1L137, CLOCK_50, , , J1L124, , , , ); --J1L4 is ps2_keyboard:u4|Equal~8655 J1L4 = !J1_q[2] & (J1_left_shift_key # J1_right_shift_key); --J1_q[4] is ps2_keyboard:u4|q[4] J1_q[4] = DFFEAS(J1L138, CLOCK_50, , , J1L124, , , , ); --J1L256 is ps2_keyboard:u4|rx_shift_key_on~0 J1L256 = J1_left_shift_key # J1_right_shift_key; --J1L5 is ps2_keyboard:u4|Equal~8656 J1L5 = J1_q[1] & J1_q[3] & !J1_q[2]; --J1L143 is ps2_keyboard:u4|reduce_nor~841 J1L143 = !J1_q[8] & !J1_q[7]; --J1L6 is ps2_keyboard:u4|Equal~8657 J1L6 = J1_q[2] & !J1_q[1]; --J1L7 is ps2_keyboard:u4|Equal~8658 J1L7 = J1_q[6] & !J1_q[5]; --J1L8 is ps2_keyboard:u4|Equal~8659 J1L8 = J1_q[6] & J1_q[5] & !J1_q[8] & !J1_q[7]; --J1L9 is ps2_keyboard:u4|Equal~8660 J1L9 = J1L8 & !J1_q[4]; --J1L188 is ps2_keyboard:u4|reduce_or~1237 J1L188 = J1L52 # J1L256 & J1L5 & J1L9; --J1L10 is ps2_keyboard:u4|Equal~8661 J1L10 = J1_q[5] & J1_q[7] & !J1_q[6] & !J1_q[8]; --J1L11 is ps2_keyboard:u4|Equal~8662 J1L11 = J1L3 & !J1L256 & !J1_q[2] & !J1_q[4]; --J1L144 is ps2_keyboard:u4|reduce_nor~842 J1L144 = J1_q[4] & !J1_q[6] & !J1_q[5]; --J1L12 is ps2_keyboard:u4|Equal~8663 J1L12 = J1_q[7] & !J1_q[8]; --J1L13 is ps2_keyboard:u4|Equal~8664 J1L13 = J1_q[2] & J1_q[3] & !J1_q[1] & !J1_q[4]; --J1L14 is ps2_keyboard:u4|Equal~8665 J1L14 = J1_q[2] & J1_q[4] & !J1_q[1] & !J1_q[3]; --J1L189 is ps2_keyboard:u4|reduce_or~1238 J1L189 = J1L179 & J1L242 & (!J1L10 # !J1L14); --J1L190 is ps2_keyboard:u4|reduce_or~1239 J1L190 = J1L189 & (!J1L11 & !J1L53 # !J1L10); --J1L191 is ps2_keyboard:u4|reduce_or~1240 J1L191 = J1L188 # J1L2 & J1L51 # !J1L190; --J1L15 is ps2_keyboard:u4|Equal~8666 J1L15 = J1_q[2] & J1_q[1] & J1_q[4] & !J1_q[3]; --J1L16 is ps2_keyboard:u4|Equal~8667 J1L16 = J1_q[1] & !J1_q[2] & !J1_q[3] & !J1_q[4]; --J1L17 is ps2_keyboard:u4|Equal~8668 J1L17 = J1_q[2] & J1_q[1] & !J1_q[3] & !J1_q[4]; --J1L192 is ps2_keyboard:u4|reduce_or~1241 J1L192 = J1L13 # J1L14 # J1L17; --J1L193 is ps2_keyboard:u4|reduce_or~1242 J1L193 = J1L8 & (J1L15 # J1L16 # J1L192); --J1L18 is ps2_keyboard:u4|Equal~8669 J1L18 = J1_q[2] & J1_q[3] & J1_q[4] & !J1_q[1]; --J1L194 is ps2_keyboard:u4|reduce_or~1243 J1L194 = J1L256 & (J1L18 # J1L15) # !J1L256 & (J1L10 & J1L15); --J1L195 is ps2_keyboard:u4|reduce_or~1244 J1L195 = J1L256 & (J1L193 # J1L2 & J1L194) # !J1L256 & (J1L194); --J1L19 is ps2_keyboard:u4|Equal~8670 J1L19 = J1_q[5] & !J1_q[6] & !J1_q[8] & !J1_q[7]; --J1L20 is ps2_keyboard:u4|Equal~8671 J1L20 = J1L256 & J1L12 & !J1_q[6] & !J1_q[5]; --J1L21 is ps2_keyboard:u4|Equal~8672 J1L21 = J1_q[2] & !J1_q[1] & !J1_q[3] & !J1_q[4]; --J1L196 is ps2_keyboard:u4|reduce_or~1245 J1L196 = J1L54 # J1L20 & (J1L21 # J1L17); --J1L22 is ps2_keyboard:u4|Equal~8673 J1L22 = J1_q[2] & J1L3 & J1_q[4] & J1L19; --J1L23 is ps2_keyboard:u4|Equal~8674 J1L23 = J1L256 & J1_q[4] & J1L2 & J1L5; --J1L145 is ps2_keyboard:u4|reduce_nor~843 J1L145 = !J1L23 & !J1L55 & (!J1L22 # !J1L256); --J1L24 is ps2_keyboard:u4|Equal~8675 J1L24 = J1_q[6] & !J1_q[5] & !J1_q[8] & !J1_q[7]; --J1L25 is ps2_keyboard:u4|Equal~8676 J1L25 = J1L3 & J1L4 & J1L24 & !J1_q[4]; --J1L26 is ps2_keyboard:u4|Equal~8677 J1L26 = J1L3 & J1_q[4] & J1L4 & J1L24; --J1L27 is ps2_keyboard:u4|Equal~8678 J1L27 = J1L256 & J1_q[4] & J1L19 & J1L5; --J1L28 is ps2_keyboard:u4|Equal~8679 J1L28 = J1L256 & J1L19 & J1L5 & !J1_q[4]; --J1L197 is ps2_keyboard:u4|reduce_or~1246 J1L197 = !J1L25 & !J1L26 & !J1L27 & !J1L28; --J1L29 is ps2_keyboard:u4|Equal~8680 J1L29 = J1L3 & J1_q[4] & J1L8 & J1L4; --J1L30 is ps2_keyboard:u4|Equal~8681 J1L30 = J1L3 & J1L8 & J1L4 & !J1_q[4]; --J1L31 is ps2_keyboard:u4|Equal~8682 J1L31 = J1_q[4] & J1L143 & J1L6 & J1L7; --J1L198 is ps2_keyboard:u4|reduce_or~1247 J1L198 = !J1L29 & !J1L30 & !J1L56; --J1L199 is ps2_keyboard:u4|reduce_or~1248 J1L199 = J1L24 & (J1L15 # J1L17); --J1L200 is ps2_keyboard:u4|reduce_or~1249 J1L200 = !J1L199 & (!J1L15 # !J1L19) # !J1L256; --J1L32 is ps2_keyboard:u4|Equal~8683 J1L32 = J1L3 & J1_q[4] & J1L19 & J1L4; --J1L33 is ps2_keyboard:u4|Equal~8684 J1L33 = J1L256 & J1_q[4] & J1L5 & J1L24; --J1L201 is ps2_keyboard:u4|reduce_or~1250 J1L201 = J1L200 & !J1L32 & !J1L33 & !J1L57; --J1L202 is ps2_keyboard:u4|reduce_or~1251 J1L202 = J1L145 & J1L197 & J1L198 & J1L201; --J1L185 is ps2_keyboard:u4|reduce_or~15 J1L185 = !J1L191 & !J1L195 & !J1L196 & J1L202; --J1_bit_count[2] is ps2_keyboard:u4|bit_count[2] J1_bit_count[2] = DFFEAS(J1L83, CLOCK_50, , , , , , J1L87, ); --J1_bit_count[0] is ps2_keyboard:u4|bit_count[0] J1_bit_count[0] = DFFEAS(J1L77, CLOCK_50, , , , , , J1L87, ); --J1_bit_count[1] is ps2_keyboard:u4|bit_count[1] J1_bit_count[1] = DFFEAS(J1L80, CLOCK_50, , , , , , J1L87, ); --J1_bit_count[3] is ps2_keyboard:u4|bit_count[3] J1_bit_count[3] = DFFEAS(J1L88, CLOCK_50, , , , , , J1L87, ); --J1L257 is ps2_keyboard:u4|rx_shifting_done~74 J1L257 = J1_bit_count[2] # !J1_bit_count[3] # !J1_bit_count[1] # !J1_bit_count[0]; --J1L249 is ps2_keyboard:u4|rx_ascii[0]~830 J1L249 = !J1L257 # !KEY[0]; --J1L115 is ps2_keyboard:u4|m2_next_state~9 J1L115 = !J1_m2_state & !J1L257; --J1L203 is ps2_keyboard:u4|reduce_or~1252 J1L203 = J1L10 & (J1L58 # J1L59) # !J1L189; --J1L34 is ps2_keyboard:u4|Equal~8685 J1L34 = J1_q[3] & !J1L256 & !J1_q[2] & !J1_q[1]; --J1L35 is ps2_keyboard:u4|Equal~8686 J1L35 = J1_q[4] & J1L2 & J1L34; --J1L36 is ps2_keyboard:u4|Equal~8687 J1L36 = J1L256 & J1L2 & J1L5 & !J1_q[4]; --J1L204 is ps2_keyboard:u4|reduce_or~1253 J1L204 = J1L8 & J1L18; --J1L37 is ps2_keyboard:u4|Equal~8688 J1L37 = J1L3 & J1_q[4] & J1L2 & J1L4; --J1L38 is ps2_keyboard:u4|Equal~8689 J1L38 = J1_q[1] & J1_q[4] & !J1_q[2] & !J1_q[3]; --J1L205 is ps2_keyboard:u4|reduce_or~1254 J1L205 = J1L2 & (J1L14 # J1L38); --J1L206 is ps2_keyboard:u4|reduce_or~1255 J1L206 = J1L16 # J1L13 # J1L18 & !J1L256; --J1L207 is ps2_keyboard:u4|reduce_or~1256 J1L207 = J1L37 # J1L205 # J1L2 & J1L206; --J1L208 is ps2_keyboard:u4|reduce_or~1257 J1L208 = J1L35 # J1L36 # J1L204 # J1L207; --J1L146 is ps2_keyboard:u4|reduce_nor~844 J1L146 = !J1L15 # !J1L19; --J1L39 is ps2_keyboard:u4|Equal~8690 J1L39 = J1_q[3] & !J1_left_shift_key & !J1_right_shift_key; --J1L147 is ps2_keyboard:u4|reduce_nor~845 J1L147 = J1L51 & !J1L10 & (!J1L39 # !J1L73) # !J1L51 & (!J1L39 # !J1L73); --J1L148 is ps2_keyboard:u4|reduce_nor~846 J1L148 = J1L147 & !J1L35 & (!J1L11 # !J1L10); --J1L40 is ps2_keyboard:u4|Equal~8691 J1L40 = J1_q[3] & (J1_left_shift_key # J1_right_shift_key); --J1L149 is ps2_keyboard:u4|reduce_nor~847 J1L149 = J1L58 & !J1L10 & (!J1L40 # !J1L73) # !J1L58 & (!J1L40 # !J1L73); --J1L150 is ps2_keyboard:u4|reduce_nor~848 J1L150 = !J1L21 # !J1L2; --J1L151 is ps2_keyboard:u4|reduce_nor~849 J1L151 = J1L149 & J1L150 & !J1L57 & !J1L60; --J1L41 is ps2_keyboard:u4|Equal~8692 J1L41 = J1_q[1] & J1_q[3] & !J1_q[2] & !J1_q[4]; --J1L152 is ps2_keyboard:u4|reduce_nor~850 J1L152 = J1L13 & !J1L61 & (!J1L62) # !J1L13 & (!J1L62 # !J1L41); --J1L153 is ps2_keyboard:u4|reduce_nor~851 J1L153 = J1L181 & J1L152 & (!J1L180 # !J1_q[5]); --J1L154 is ps2_keyboard:u4|reduce_nor~852 J1L154 = !J1L153 # !J1L151 # !J1L148 # !J1L146; --J1L42 is ps2_keyboard:u4|Equal~8693 J1L42 = J1_q[4] & J1L19 & J1L34; --J1L155 is ps2_keyboard:u4|reduce_nor~853 J1L155 = J1L2 & (J1L58 # J1L17); --J1L156 is ps2_keyboard:u4|reduce_nor~854 J1L156 = J1L256 & J1L19 & J1L13 # !J1L179; --J1L157 is ps2_keyboard:u4|reduce_nor~855 J1L157 = J1L32 # J1L42 # J1L155 # J1L156; --J1L43 is ps2_keyboard:u4|Equal~8694 J1L43 = J1_q[3] & J1L143 & J1L6 & J1L144; --J1L158 is ps2_keyboard:u4|reduce_nor~856 J1L158 = J1L256 & !J1L43 & (!J1L13 # !J1L8) # !J1L256 & (!J1L13 # !J1L8); --J1L159 is ps2_keyboard:u4|reduce_nor~857 J1L159 = J1L158 & !J1L56 & !J1L63 & !J1L64; --J1L209 is ps2_keyboard:u4|reduce_or~1258 J1L209 = !J1L26 & (!J1L65 & !J1L53 # !J1L10); --J1L210 is ps2_keyboard:u4|reduce_or~1259 J1L210 = !J1L59 & (!J1L34 # !J1_q[4]) # !J1L24; --J1L211 is ps2_keyboard:u4|reduce_or~1260 J1L211 = J1L209 & J1L210 & (!J1L20 # !J1L16); --J1L212 is ps2_keyboard:u4|reduce_or~1261 J1L212 = !J1L65 & !J1L16 # !J1L8; --J1L213 is ps2_keyboard:u4|reduce_or~1262 J1L213 = !J1L15 # !J1L24; --J1L214 is ps2_keyboard:u4|reduce_or~1263 J1L214 = J1L212 & J1L213 & (!J1L61 # !J1L38); --J1L160 is ps2_keyboard:u4|reduce_nor~858 J1L160 = J1L2 & (J1L15 # !J1L256 & J1L16); --J1L161 is ps2_keyboard:u4|reduce_nor~859 J1L161 = J1L160 # J1L24 & (J1L17 # J1L58); --J1L162 is ps2_keyboard:u4|reduce_nor~860 J1L162 = J1L159 & J1L211 & J1L214 & !J1L161; --J1L215 is ps2_keyboard:u4|reduce_or~1264 J1L215 = !J1L29 & (!J1L34 # !J1L8 # !J1_q[4]); --J1L216 is ps2_keyboard:u4|reduce_or~1265 J1L216 = J1_q[4] # !J1L2 & !J1L8 # !J1L34; --J1L217 is ps2_keyboard:u4|reduce_or~1266 J1L217 = !J1L67 & (J1L256 # !J1L14 # !J1L2); --J1L44 is ps2_keyboard:u4|Equal~8695 J1L44 = J1L3 & J1L2 & J1L4 & !J1_q[4]; --J1L218 is ps2_keyboard:u4|reduce_or~1267 J1L218 = J1L216 & J1L217 & !J1L30 & !J1L44; --J1L141 is ps2_keyboard:u4|reduce_nor~5 J1L141 = !J1L16 # !J1L12 # !J1_q[5] # !J1_q[6]; --J1L163 is ps2_keyboard:u4|reduce_nor~861 J1L163 = J1L141 & (!J1L14 & !J1L18 # !J1L20); --J1L45 is ps2_keyboard:u4|Equal~8696 J1L45 = J1_q[4] & J1L19 & J1L5 & !J1L256; --J1L46 is ps2_keyboard:u4|Equal~8697 J1L46 = J1_q[4] & J1L5 & J1L8 & !J1L256; --J1L164 is ps2_keyboard:u4|reduce_nor~862 J1L164 = J1L163 & !J1L27 & !J1L45 & !J1L46; --J1L165 is ps2_keyboard:u4|reduce_nor~863 J1L165 = !J1L8 & !J1L10 # !J1L14; --J1L47 is ps2_keyboard:u4|Equal~8698 J1L47 = J1L143 & J1L7 & J1L34 & !J1_q[4]; --J1L166 is ps2_keyboard:u4|reduce_nor~864 J1L166 = J1L165 & !J1L25 & !J1L68 & !J1L47; --J1L167 is ps2_keyboard:u4|reduce_nor~865 J1L167 = J1L164 & J1L166 & (!J1L61 # !J1L18); --J1L168 is ps2_keyboard:u4|reduce_nor~866 J1L168 = J1L162 & J1L244 & J1L218 & J1L167; --J1L169 is ps2_keyboard:u4|reduce_nor~867 J1L169 = !J1L24 # !J1L5 # !J1_q[4]; --J1L170 is ps2_keyboard:u4|reduce_nor~868 J1L170 = !J1L14 # !J1L19; --J1L171 is ps2_keyboard:u4|reduce_nor~869 J1L171 = J1L169 & J1L170 & !J1L69 & !J1L37; --J1L48 is ps2_keyboard:u4|Equal~8699 J1L48 = !J1_left_shift_key & !J1_right_shift_key & !J1_q[3]; --J1L219 is ps2_keyboard:u4|reduce_or~1268 J1L219 = J1L73 & !J1L48 & (!J1L70 # !J1L18) # !J1L73 & (!J1L70 # !J1L18); --J1L49 is ps2_keyboard:u4|Equal~8700 J1L49 = J1_q[4] & J1L2 & J1L5 & !J1L256; --J1L50 is ps2_keyboard:u4|Equal~8701 J1L50 = J1L2 & J1L5 & !J1L256 & !J1_q[4]; --J1L220 is ps2_keyboard:u4|reduce_or~1269 J1L220 = J1L219 & !J1L52 & !J1L49 & !J1L50; --J1L172 is ps2_keyboard:u4|reduce_nor~870 J1L172 = !J1L71 & (!J1L15 & !J1L182 # !J1L8); --J1L173 is ps2_keyboard:u4|reduce_nor~871 J1L173 = !J1L17 # !J1L8; --J1L174 is ps2_keyboard:u4|reduce_nor~872 J1L174 = J1L256 & (J1_q[5] # !J1L180) # !J1L256 & !J1L43 & (J1_q[5] # !J1L180); --J1L175 is ps2_keyboard:u4|reduce_nor~873 J1L175 = J1L24 & !J1L38 & (!J1L20 # !J1L13) # !J1L24 & (!J1L20 # !J1L13); --J1L176 is ps2_keyboard:u4|reduce_nor~874 J1L176 = J1L172 & J1L173 & J1L174 & J1L175; --J1L177 is ps2_keyboard:u4|reduce_nor~875 J1L177 = J1L145 & J1L171 & J1L220 & J1L176; --J1L142 is ps2_keyboard:u4|reduce_nor~6 J1L142 = J1L154 # J1L157 # !J1L177 # !J1L168; --J1L221 is ps2_keyboard:u4|reduce_or~1270 J1L221 = !J1L8 # !J1L5 # !J1_q[4]; --J1L222 is ps2_keyboard:u4|reduce_or~1271 J1L222 = !J1L31 & !J1L73 # !J1L40; --J1L223 is ps2_keyboard:u4|reduce_or~1272 J1L223 = J1L222 & (!J1L58 & !J1L59 # !J1L24); --J1L224 is ps2_keyboard:u4|reduce_or~1273 J1L224 = !J1L19 & (J1L256 # !J1L8) # !J1L13; --J1L225 is ps2_keyboard:u4|reduce_or~1274 J1L225 = !J1L67 & !J1L71 & (!J1L38 # !J1L24); --J1L226 is ps2_keyboard:u4|reduce_or~1275 J1L226 = J1L50 # J1_q[3] & J1L73 & !J1L256; --J1L227 is ps2_keyboard:u4|reduce_or~1276 J1L227 = !J1L66 & J1L224 & J1L225 & !J1L226; --J1L228 is ps2_keyboard:u4|reduce_or~1277 J1L228 = J1L221 & !J1L69 & J1L223 & J1L227; --J1L184 is ps2_keyboard:u4|reduce_or~14 J1L184 = !J1L203 & !J1L208 & J1L142 & J1L228; --J1L229 is ps2_keyboard:u4|reduce_or~1278 J1L229 = J1L23 # !J1L152 # !J1L181 # !J1L220; --J1L178 is ps2_keyboard:u4|reduce_nor~876 J1L178 = J1L148 & J1L146 & (!J1L180 # !J1_q[5]); --J1L230 is ps2_keyboard:u4|reduce_or~1279 J1L230 = J1L159 & J1L164 & J1L171 & J1L178; --J1L231 is ps2_keyboard:u4|reduce_or~1280 J1L231 = J1L229 # !J1L230 # !J1L244 # !J1L211; --J1L186 is ps2_keyboard:u4|reduce_or~18 J1L186 = J1L177 & !J1L154 & !J1L157 # !J1L168; --J1L187 is ps2_keyboard:u4|reduce_or~20 J1L187 = J1L162 & J1L177 & J1L142; --J1L232 is ps2_keyboard:u4|reduce_or~1281 J1L232 = J1L214 & J1L218 & !J1L55 & J1L172; --J1L233 is ps2_keyboard:u4|reduce_or~1282 J1L233 = !J1L232 # !J1L230 # !J1L142 # !J1L151; --J1L234 is ps2_keyboard:u4|reduce_or~1283 J1L234 = J1L34 & (J1L8 # J1_q[4] & J1L24); --J1L235 is ps2_keyboard:u4|reduce_or~1284 J1L235 = J1L45 # J1L63 # J1L47 # J1L234; --J1L236 is ps2_keyboard:u4|reduce_or~1285 J1L236 = J1L72 # J1L62 & (J1L15 # J1L41); --J1L237 is ps2_keyboard:u4|reduce_or~1286 J1L237 = J1L60 # J1L236 # J1L21 & J1L70; --J1L238 is ps2_keyboard:u4|reduce_or~1287 J1L238 = J1L17 # J1_q[4] & J1L5; --J1L239 is ps2_keyboard:u4|reduce_or~1288 J1L239 = J1L24 & !J1L256 & (J1L15 # J1L238); --J1L240 is ps2_keyboard:u4|reduce_or~1289 J1L240 = J1L49 # J1L42 # J1L237 # J1L239; --J1L241 is ps2_keyboard:u4|reduce_or~1290 J1L241 = !J1L235 & !J1L240 & J1L202 & J1L228; --Z1_mDATAOUT[14] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[14] Z1_mDATAOUT[14] = DFFEAS(A1L63, S1__clk0, , , , , , , ); --Z1_mDATAOUT[6] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[6] Z1_mDATAOUT[6] = DFFEAS(A1L47, S1__clk0, , , , , , , ); --Z1_mDATAOUT[12] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[12] Z1_mDATAOUT[12] = DFFEAS(A1L59, S1__clk0, , , , , , , ); --Z1_mDATAOUT[4] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[4] Z1_mDATAOUT[4] = DFFEAS(A1L43, S1__clk0, , , , , , , ); --Z1_mDATAOUT[15] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[15] Z1_mDATAOUT[15] = DFFEAS(A1L65, S1__clk0, , , , , , , ); --Z1_mDATAOUT[7] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[7] Z1_mDATAOUT[7] = DFFEAS(A1L49, S1__clk0, , , , , , , ); --Z1_mDATAOUT[10] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[10] Z1_mDATAOUT[10] = DFFEAS(A1L55, S1__clk0, , , , , , , ); --Z1_mDATAOUT[2] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[2] Z1_mDATAOUT[2] = DFFEAS(A1L39, S1__clk0, , , , , , , ); --Z1_mDATAOUT[9] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[9] Z1_mDATAOUT[9] = DFFEAS(A1L53, S1__clk0, , , , , , , ); --Z1_mDATAOUT[1] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[1] Z1_mDATAOUT[1] = DFFEAS(A1L37, S1__clk0, , , , , , , ); --Z1_mDATAOUT[8] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[8] Z1_mDATAOUT[8] = DFFEAS(A1L51, S1__clk0, , , , , , , ); --Z1_mDATAOUT[0] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[0] Z1_mDATAOUT[0] = DFFEAS(A1L35, S1__clk0, , , , , , , ); --Z1_mDATAOUT[11] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[11] Z1_mDATAOUT[11] = DFFEAS(A1L57, S1__clk0, , , , , , , ); --Z1_mDATAOUT[3] is Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[3] Z1_mDATAOUT[3] = DFFEAS(A1L41, S1__clk0, , , , , , , ); --MB1L13 is I2C_AV_Config:u10|I2C_Controller:u0|END~124 MB1L13 = MB1L52Q & MB1L40Q & MB1L46Q & MB1L49Q; --MB1L14 is I2C_AV_Config:u10|I2C_Controller:u0|END~125 MB1L14 = MB1L43Q & (MB1L13 & (MB1L55Q) # !MB1L13 & MB1_END) # !MB1L43Q & (MB1_END); --MB1_ACK3 is I2C_AV_Config:u10|I2C_Controller:u0|ACK3 MB1_ACK3 = DFFEAS(MB1L11, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --MB1_ACK1 is I2C_AV_Config:u10|I2C_Controller:u0|ACK1 MB1_ACK1 = DFFEAS(MB1L3, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --MB1_ACK2 is I2C_AV_Config:u10|I2C_Controller:u0|ACK2 MB1_ACK2 = DFFEAS(MB1L8, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1L89 is I2C_AV_Config:u10|mSetup_ST~58 P1L89 = !MB1_ACK3 & !MB1_ACK1 & !MB1_ACK2; --P1L90 is I2C_AV_Config:u10|mSetup_ST~59 P1L90 = P1_mSetup_ST.01 & P1L89 & !MB1_END; --P1_mSetup_ST.00 is I2C_AV_Config:u10|mSetup_ST.00 P1_mSetup_ST.00 = DFFEAS(P1L21, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1L20 is I2C_AV_Config:u10|Select~136 P1L20 = P1_mSetup_ST.01 & MB1_END # !P1_mSetup_ST.00; --HB1_address_reg_a[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[3] HB1_address_reg_a[3] = DFFEAS(N1L128, S2__clk0, , , , , , , ); --HB1_address_reg_a[2] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[2] HB1_address_reg_a[2] = DFFEAS(N1L126, S2__clk0, , , , , , , ); --HB1_address_reg_a[1] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[1] HB1_address_reg_a[1] = DFFEAS(N1L124, S2__clk0, , , , , , , ); --N1L25 is VGA_OSD_RAM:u9|add~1377 N1L25 = CARRY(!M1_oCoord_Y[0]); --N1L26 is VGA_OSD_RAM:u9|add~1378 N1L26 = M1_oCoord_Y[1] & (N1L25 # GND) # !M1_oCoord_Y[1] & !N1L25; --N1L27 is VGA_OSD_RAM:u9|add~1379 N1L27 = CARRY(M1_oCoord_Y[1] # !N1L25); --N1L28 is VGA_OSD_RAM:u9|add~1380 N1L28 = M1_oCoord_Y[2] & !N1L27 & VCC # !M1_oCoord_Y[2] & (N1L27 $ GND); --N1L29 is VGA_OSD_RAM:u9|add~1381 N1L29 = CARRY(!M1_oCoord_Y[2] & !N1L27); --N1L30 is VGA_OSD_RAM:u9|add~1382 N1L30 = M1_oCoord_Y[3] & (N1L29 # GND) # !M1_oCoord_Y[3] & !N1L29; --N1L31 is VGA_OSD_RAM:u9|add~1383 N1L31 = CARRY(M1_oCoord_Y[3] # !N1L29); --N1L32 is VGA_OSD_RAM:u9|add~1384 N1L32 = M1_oCoord_Y[4] & !N1L31 & VCC # !M1_oCoord_Y[4] & (N1L31 $ GND); --N1L33 is VGA_OSD_RAM:u9|add~1385 N1L33 = CARRY(!M1_oCoord_Y[4] & !N1L31); --N1L34 is VGA_OSD_RAM:u9|add~1386 N1L34 = M1_oCoord_Y[5] & (N1L33 # GND) # !M1_oCoord_Y[5] & !N1L33; --N1L35 is VGA_OSD_RAM:u9|add~1387 N1L35 = CARRY(M1_oCoord_Y[5] # !N1L33); --N1L36 is VGA_OSD_RAM:u9|add~1388 N1L36 = M1_oCoord_Y[6] & !N1L35 & VCC # !M1_oCoord_Y[6] & (N1L35 $ GND); --N1L37 is VGA_OSD_RAM:u9|add~1389 N1L37 = CARRY(!M1_oCoord_Y[6] & !N1L35); --N1L38 is VGA_OSD_RAM:u9|add~1390 N1L38 = M1_oCoord_Y[7] & (N1L37 # GND) # !M1_oCoord_Y[7] & !N1L37; --N1L39 is VGA_OSD_RAM:u9|add~1391 N1L39 = CARRY(M1_oCoord_Y[7] # !N1L37); --N1L40 is VGA_OSD_RAM:u9|add~1392 N1L40 = M1_oCoord_Y[8] & !N1L39 & VCC # !M1_oCoord_Y[8] & (N1L39 $ GND); --N1L41 is VGA_OSD_RAM:u9|add~1393 N1L41 = CARRY(!M1_oCoord_Y[8] & !N1L39); --N1L42 is VGA_OSD_RAM:u9|add~1394 N1L42 = M1_oCoord_Y[9] & (N1L41 # GND) # !M1_oCoord_Y[9] & !N1L41; --N1L43 is VGA_OSD_RAM:u9|add~1395 N1L43 = CARRY(M1_oCoord_Y[9] # !N1L41); --N1L44 is VGA_OSD_RAM:u9|add~1396 N1L44 = N1L43 $ GND; --N1L45 is VGA_OSD_RAM:u9|add~1397 N1L45 = CARRY(!N1L43); --N1L46 is VGA_OSD_RAM:u9|add~1398 N1L46 = !N1L45; --N1L48 is VGA_OSD_RAM:u9|add~1400 N1L48 = N1L32 & (M1_oCoord_Y[0] $ VCC) # !N1L32 & M1_oCoord_Y[0] & VCC; --N1L49 is VGA_OSD_RAM:u9|add~1401 N1L49 = CARRY(N1L32 & M1_oCoord_Y[0]); --N1L50 is VGA_OSD_RAM:u9|add~1402 N1L50 = N1L34 & (M1_oCoord_Y[1] & N1L49 & VCC # !M1_oCoord_Y[1] & !N1L49) # !N1L34 & (M1_oCoord_Y[1] & !N1L49 # !M1_oCoord_Y[1] & (N1L49 # GND)); --N1L51 is VGA_OSD_RAM:u9|add~1403 N1L51 = CARRY(N1L34 & !M1_oCoord_Y[1] & !N1L49 # !N1L34 & (!N1L49 # !M1_oCoord_Y[1])); --N1L52 is VGA_OSD_RAM:u9|add~1404 N1L52 = (N1L36 $ M1_oCoord_Y[2] $ !N1L51) # GND; --N1L53 is VGA_OSD_RAM:u9|add~1405 N1L53 = CARRY(N1L36 & (M1_oCoord_Y[2] # !N1L51) # !N1L36 & M1_oCoord_Y[2] & !N1L51); --N1L54 is VGA_OSD_RAM:u9|add~1406 N1L54 = N1L38 & (M1_oCoord_Y[3] & N1L53 & VCC # !M1_oCoord_Y[3] & !N1L53) # !N1L38 & (M1_oCoord_Y[3] & !N1L53 # !M1_oCoord_Y[3] & (N1L53 # GND)); --N1L55 is VGA_OSD_RAM:u9|add~1407 N1L55 = CARRY(N1L38 & !M1_oCoord_Y[3] & !N1L53 # !N1L38 & (!N1L53 # !M1_oCoord_Y[3])); --N1L56 is VGA_OSD_RAM:u9|add~1408 N1L56 = (N1L40 $ M1_oCoord_Y[4] $ !N1L55) # GND; --N1L57 is VGA_OSD_RAM:u9|add~1409 N1L57 = CARRY(N1L40 & (M1_oCoord_Y[4] # !N1L55) # !N1L40 & M1_oCoord_Y[4] & !N1L55); --N1L58 is VGA_OSD_RAM:u9|add~1410 N1L58 = N1L42 & (M1_oCoord_Y[5] & N1L57 & VCC # !M1_oCoord_Y[5] & !N1L57) # !N1L42 & (M1_oCoord_Y[5] & !N1L57 # !M1_oCoord_Y[5] & (N1L57 # GND)); --N1L59 is VGA_OSD_RAM:u9|add~1411 N1L59 = CARRY(N1L42 & !M1_oCoord_Y[5] & !N1L57 # !N1L42 & (!N1L57 # !M1_oCoord_Y[5])); --N1L60 is VGA_OSD_RAM:u9|add~1412 N1L60 = (N1L44 $ M1_oCoord_Y[6] $ !N1L59) # GND; --N1L61 is VGA_OSD_RAM:u9|add~1413 N1L61 = CARRY(N1L44 & (M1_oCoord_Y[6] # !N1L59) # !N1L44 & M1_oCoord_Y[6] & !N1L59); --N1L62 is VGA_OSD_RAM:u9|add~1414 N1L62 = N1L46 & (M1_oCoord_Y[7] & N1L61 & VCC # !M1_oCoord_Y[7] & !N1L61) # !N1L46 & (M1_oCoord_Y[7] & !N1L61 # !M1_oCoord_Y[7] & (N1L61 # GND)); --N1L63 is VGA_OSD_RAM:u9|add~1415 N1L63 = CARRY(N1L46 & !M1_oCoord_Y[7] & !N1L61 # !N1L46 & (!N1L61 # !M1_oCoord_Y[7])); --N1L64 is VGA_OSD_RAM:u9|add~1416 N1L64 = (N1L46 $ M1_oCoord_Y[8] $ !N1L63) # GND; --N1L65 is VGA_OSD_RAM:u9|add~1417 N1L65 = CARRY(N1L46 & (M1_oCoord_Y[8] # !N1L63) # !N1L46 & M1_oCoord_Y[8] & !N1L63); --N1L66 is VGA_OSD_RAM:u9|add~1418 N1L66 = N1L46 & (M1_oCoord_Y[9] & N1L65 & VCC # !M1_oCoord_Y[9] & !N1L65) # !N1L46 & (M1_oCoord_Y[9] & !N1L65 # !M1_oCoord_Y[9] & (N1L65 # GND)); --N1L67 is VGA_OSD_RAM:u9|add~1419 N1L67 = CARRY(N1L46 & !M1_oCoord_Y[9] & !N1L65 # !N1L46 & (!N1L65 # !M1_oCoord_Y[9])); --N1L68 is VGA_OSD_RAM:u9|add~1420 N1L68 = N1L46 $ !N1L67; --N1L70 is VGA_OSD_RAM:u9|add~1422 N1L70 = M1_oCoord_Y[0] & (M1_oAddress[3] $ VCC) # !M1_oCoord_Y[0] & (M1_oAddress[3] # GND); --N1L71 is VGA_OSD_RAM:u9|add~1423 N1L71 = CARRY(M1_oAddress[3] # !M1_oCoord_Y[0]); --N1L72 is VGA_OSD_RAM:u9|add~1424 N1L72 = N1L26 & (M1_oAddress[4] & !N1L71 # !M1_oAddress[4] & (N1L71 # GND)) # !N1L26 & (M1_oAddress[4] & N1L71 & VCC # !M1_oAddress[4] & !N1L71); --N1L73 is VGA_OSD_RAM:u9|add~1425 N1L73 = CARRY(N1L26 & (!N1L71 # !M1_oAddress[4]) # !N1L26 & !M1_oAddress[4] & !N1L71); --N1L74 is VGA_OSD_RAM:u9|add~1426 N1L74 = (N1L28 $ M1_oAddress[5] $ N1L73) # GND; --N1L75 is VGA_OSD_RAM:u9|add~1427 N1L75 = CARRY(N1L28 & M1_oAddress[5] & !N1L73 # !N1L28 & (M1_oAddress[5] # !N1L73)); --N1L76 is VGA_OSD_RAM:u9|add~1428 N1L76 = N1L30 & (M1_oAddress[6] & !N1L75 # !M1_oAddress[6] & (N1L75 # GND)) # !N1L30 & (M1_oAddress[6] & N1L75 & VCC # !M1_oAddress[6] & !N1L75); --N1L77 is VGA_OSD_RAM:u9|add~1429 N1L77 = CARRY(N1L30 & (!N1L75 # !M1_oAddress[6]) # !N1L30 & !M1_oAddress[6] & !N1L75); --N1L78 is VGA_OSD_RAM:u9|add~1430 N1L78 = (N1L48 $ M1_oAddress[7] $ N1L77) # GND; --N1L79 is VGA_OSD_RAM:u9|add~1431 N1L79 = CARRY(N1L48 & M1_oAddress[7] & !N1L77 # !N1L48 & (M1_oAddress[7] # !N1L77)); --N1L80 is VGA_OSD_RAM:u9|add~1432 N1L80 = N1L50 & (M1_oAddress[8] & !N1L79 # !M1_oAddress[8] & (N1L79 # GND)) # !N1L50 & (M1_oAddress[8] & N1L79 & VCC # !M1_oAddress[8] & !N1L79); --N1L81 is VGA_OSD_RAM:u9|add~1433 N1L81 = CARRY(N1L50 & (!N1L79 # !M1_oAddress[8]) # !N1L50 & !M1_oAddress[8] & !N1L79); --N1L82 is VGA_OSD_RAM:u9|add~1434 N1L82 = (N1L52 $ M1_oAddress[9] $ N1L81) # GND; --N1L83 is VGA_OSD_RAM:u9|add~1435 N1L83 = CARRY(N1L52 & M1_oAddress[9] & !N1L81 # !N1L52 & (M1_oAddress[9] # !N1L81)); --N1L84 is VGA_OSD_RAM:u9|add~1436 N1L84 = N1L54 & (M1_oAddress[10] & !N1L83 # !M1_oAddress[10] & (N1L83 # GND)) # !N1L54 & (M1_oAddress[10] & N1L83 & VCC # !M1_oAddress[10] & !N1L83); --N1L85 is VGA_OSD_RAM:u9|add~1437 N1L85 = CARRY(N1L54 & (!N1L83 # !M1_oAddress[10]) # !N1L54 & !M1_oAddress[10] & !N1L83); --N1L86 is VGA_OSD_RAM:u9|add~1438 N1L86 = (N1L56 $ M1_oAddress[11] $ N1L85) # GND; --N1L87 is VGA_OSD_RAM:u9|add~1439 N1L87 = CARRY(N1L56 & M1_oAddress[11] & !N1L85 # !N1L56 & (M1_oAddress[11] # !N1L85)); --N1L88 is VGA_OSD_RAM:u9|add~1440 N1L88 = N1L58 & (M1_oAddress[12] & !N1L87 # !M1_oAddress[12] & (N1L87 # GND)) # !N1L58 & (M1_oAddress[12] & N1L87 & VCC # !M1_oAddress[12] & !N1L87); --N1L89 is VGA_OSD_RAM:u9|add~1441 N1L89 = CARRY(N1L58 & (!N1L87 # !M1_oAddress[12]) # !N1L58 & !M1_oAddress[12] & !N1L87); --N1L90 is VGA_OSD_RAM:u9|add~1442 N1L90 = (N1L60 $ M1_oAddress[13] $ N1L89) # GND; --N1L91 is VGA_OSD_RAM:u9|add~1443 N1L91 = CARRY(N1L60 & M1_oAddress[13] & !N1L89 # !N1L60 & (M1_oAddress[13] # !N1L89)); --N1L92 is VGA_OSD_RAM:u9|add~1444 N1L92 = N1L62 & (M1_oAddress[14] & !N1L91 # !M1_oAddress[14] & (N1L91 # GND)) # !N1L62 & (M1_oAddress[14] & N1L91 & VCC # !M1_oAddress[14] & !N1L91); --N1L93 is VGA_OSD_RAM:u9|add~1445 N1L93 = CARRY(N1L62 & (!N1L91 # !M1_oAddress[14]) # !N1L62 & !M1_oAddress[14] & !N1L91); --N1L94 is VGA_OSD_RAM:u9|add~1446 N1L94 = (N1L64 $ M1_oAddress[15] $ N1L93) # GND; --N1L95 is VGA_OSD_RAM:u9|add~1447 N1L95 = CARRY(N1L64 & M1_oAddress[15] & !N1L93 # !N1L64 & (M1_oAddress[15] # !N1L93)); --N1L96 is VGA_OSD_RAM:u9|add~1448 N1L96 = N1L66 & (M1_oAddress[16] & !N1L95 # !M1_oAddress[16] & (N1L95 # GND)) # !N1L66 & (M1_oAddress[16] & N1L95 & VCC # !M1_oAddress[16] & !N1L95); --N1L97 is VGA_OSD_RAM:u9|add~1449 N1L97 = CARRY(N1L66 & (!N1L95 # !M1_oAddress[16]) # !N1L66 & !M1_oAddress[16] & !N1L95); --N1L98 is VGA_OSD_RAM:u9|add~1450 N1L98 = N1L68 $ M1_oAddress[17] $ N1L97; --N1L100 is VGA_OSD_RAM:u9|add~1452 N1L100 = M1_oAddress[1] $ VCC; --N1L101 is VGA_OSD_RAM:u9|add~1453 N1L101 = CARRY(M1_oAddress[1]); --N1L102 is VGA_OSD_RAM:u9|add~1454 N1L102 = M1_oAddress[2] & N1L101 & VCC # !M1_oAddress[2] & !N1L101; --N1L103 is VGA_OSD_RAM:u9|add~1455 N1L103 = CARRY(!M1_oAddress[2] & !N1L101); --N1L104 is VGA_OSD_RAM:u9|add~1456 N1L104 = N1L70 & (GND # !N1L103) # !N1L70 & (N1L103 $ GND); --N1L105 is VGA_OSD_RAM:u9|add~1457 N1L105 = CARRY(N1L70 # !N1L103); --N1L106 is VGA_OSD_RAM:u9|add~1458 N1L106 = N1L72 & N1L105 & VCC # !N1L72 & !N1L105; --N1L107 is VGA_OSD_RAM:u9|add~1459 N1L107 = CARRY(!N1L72 & !N1L105); --N1L108 is VGA_OSD_RAM:u9|add~1460 N1L108 = N1L74 & (GND # !N1L107) # !N1L74 & (N1L107 $ GND); --N1L109 is VGA_OSD_RAM:u9|add~1461 N1L109 = CARRY(N1L74 # !N1L107); --N1L110 is VGA_OSD_RAM:u9|add~1462 N1L110 = N1L76 & !N1L109 # !N1L76 & (N1L109 # GND); --N1L111 is VGA_OSD_RAM:u9|add~1463 N1L111 = CARRY(!N1L109 # !N1L76); --N1L112 is VGA_OSD_RAM:u9|add~1464 N1L112 = N1L78 & (N1L111 $ GND) # !N1L78 & !N1L111 & VCC; --N1L113 is VGA_OSD_RAM:u9|add~1465 N1L113 = CARRY(N1L78 & !N1L111); --N1L114 is VGA_OSD_RAM:u9|add~1466 N1L114 = N1L80 & !N1L113 # !N1L80 & (N1L113 # GND); --N1L115 is VGA_OSD_RAM:u9|add~1467 N1L115 = CARRY(!N1L113 # !N1L80); --N1L116 is VGA_OSD_RAM:u9|add~1468 N1L116 = N1L82 & (GND # !N1L115) # !N1L82 & (N1L115 $ GND); --N1L117 is VGA_OSD_RAM:u9|add~1469 N1L117 = CARRY(N1L82 # !N1L115); --N1L118 is VGA_OSD_RAM:u9|add~1470 N1L118 = N1L84 & !N1L117 # !N1L84 & (N1L117 # GND); --N1L119 is VGA_OSD_RAM:u9|add~1471 N1L119 = CARRY(!N1L117 # !N1L84); --N1L120 is VGA_OSD_RAM:u9|add~1472 N1L120 = N1L86 & (GND # !N1L119) # !N1L86 & (N1L119 $ GND); --N1L121 is VGA_OSD_RAM:u9|add~1473 N1L121 = CARRY(N1L86 # !N1L119); --N1L122 is VGA_OSD_RAM:u9|add~1474 N1L122 = N1L88 & N1L121 & VCC # !N1L88 & !N1L121; --N1L123 is VGA_OSD_RAM:u9|add~1475 N1L123 = CARRY(!N1L88 & !N1L121); --N1L124 is VGA_OSD_RAM:u9|add~1476 N1L124 = N1L90 & (N1L123 $ GND) # !N1L90 & !N1L123 & VCC; --N1L125 is VGA_OSD_RAM:u9|add~1477 N1L125 = CARRY(N1L90 & !N1L123); --N1L126 is VGA_OSD_RAM:u9|add~1478 N1L126 = N1L92 & !N1L125 # !N1L92 & (N1L125 # GND); --N1L127 is VGA_OSD_RAM:u9|add~1479 N1L127 = CARRY(!N1L125 # !N1L92); --N1L128 is VGA_OSD_RAM:u9|add~1480 N1L128 = N1L94 & (GND # !N1L127) # !N1L94 & (N1L127 $ GND); --N1L129 is VGA_OSD_RAM:u9|add~1481 N1L129 = CARRY(N1L94 # !N1L127); --N1L130 is VGA_OSD_RAM:u9|add~1482 N1L130 = N1L96 & N1L129 & VCC # !N1L96 & !N1L129; --N1L131 is VGA_OSD_RAM:u9|add~1483 N1L131 = CARRY(!N1L96 & !N1L129); --N1L132 is VGA_OSD_RAM:u9|add~1484 N1L132 = N1L98 $ N1L131; --JB3L93 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3]~15 JB3L93 = N1L124 & !N1L122 & !N1L126; --JB3L106 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3438w[3]~24 JB3L106 = N1L132 & N1L130 & JB3L93 & !N1L128; --JB3L23 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3]~14 JB3L23 = N1L122 & !N1L124 & !N1L126; --JB3L105 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3428w[3]~10 JB3L105 = N1L132 & N1L130 & JB3L23 & !N1L128; --JB3L88 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3]~15 JB3L88 = !N1L122 & !N1L124 & !N1L126; --JB3L104 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3417w[3]~11 JB3L104 = N1L132 & N1L130 & JB3L88 & !N1L128; --HB1_address_reg_a[0] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[0] HB1_address_reg_a[0] = DFFEAS(N1L122, S2__clk0, , , , , , , ); --JB3L17 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3]~21 JB3L17 = N1L124 & N1L126; --JB3L52 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3127w[3]~18 JB3L52 = N1L130 & !N1L132; --JB3_w_anode3199w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3199w[3] JB3_w_anode3199w[3] = N1L128 & JB3L17 & JB3L52 & !N1L122; --JB3L13 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3]~22 JB3L13 = N1L126 & !N1L124; --JB3_w_anode3189w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3189w[3] JB3_w_anode3189w[3] = N1L122 & N1L128 & JB3L13 & JB3L52; --JB3_w_anode3179w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3179w[3] JB3_w_anode3179w[3] = N1L128 & JB3L13 & JB3L52 & !N1L122; --JB3_w_anode3209w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3209w[3] JB3_w_anode3209w[3] = N1L122 & N1L128 & JB3L17 & JB3L52; --JB3_w_anode3096w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3096w[3] JB3_w_anode3096w[3] = N1L122 & JB3L13 & JB3L52 & !N1L128; --JB3_w_anode3106w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3106w[3] JB3_w_anode3106w[3] = JB3L17 & JB3L52 & !N1L122 & !N1L128; --JB3_w_anode3086w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3086w[3] JB3_w_anode3086w[3] = JB3L13 & JB3L52 & !N1L122 & !N1L128; --JB3_w_anode3116w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3116w[3] JB3_w_anode3116w[3] = N1L122 & JB3L17 & JB3L52 & !N1L128; --JB3L9 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3]~16 JB3L9 = N1L124 & !N1L126; --JB3_w_anode3076w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3076w[3] JB3_w_anode3076w[3] = N1L122 & JB3L9 & JB3L52 & !N1L128; --JB3_w_anode3169w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3169w[3] JB3_w_anode3169w[3] = N1L122 & N1L128 & JB3L9 & JB3L52; --HB1_address_reg_a[5] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[5] HB1_address_reg_a[5] = DFFEAS(N1L132, S2__clk0, , , , , , , ); --HB1_address_reg_a[4] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[4] HB1_address_reg_a[4] = DFFEAS(N1L130, S2__clk0, , , , , , , ); --JB3L18 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2941w[3]~20 JB3L18 = N1L128 & !N1L130; --JB3_w_anode3385w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3385w[3] JB3_w_anode3385w[3] = N1L132 & JB3L18 & JB3L17 & !N1L122; --JB3_w_anode3375w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3375w[3] JB3_w_anode3375w[3] = N1L132 & N1L122 & JB3L18 & JB3L13; --JB3_w_anode3365w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3365w[3] JB3_w_anode3365w[3] = N1L132 & JB3L18 & JB3L13 & !N1L122; --JB3_w_anode3395w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3395w[3] JB3_w_anode3395w[3] = N1L132 & N1L122 & JB3L18 & JB3L17; --JB3_w_anode3003w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3003w[3] JB3_w_anode3003w[3] = N1L122 & JB3L18 & JB3L13 & !N1L132; --JB3_w_anode3013w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3013w[3] JB3_w_anode3013w[3] = JB3L18 & JB3L17 & !N1L132 & !N1L122; --JB3_w_anode2993w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2993w[3] JB3_w_anode2993w[3] = JB3L18 & JB3L13 & !N1L132 & !N1L122; --JB3_w_anode3023w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3023w[3] JB3_w_anode3023w[3] = N1L122 & JB3L18 & JB3L17 & !N1L132; --JB3L69 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3220w[3]~28 JB3L69 = !N1L128 & !N1L130; --JB3_w_anode3282w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3282w[3] JB3_w_anode3282w[3] = N1L132 & N1L122 & JB3L13 & JB3L69; --JB3_w_anode3292w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3292w[3] JB3_w_anode3292w[3] = N1L132 & JB3L17 & JB3L69 & !N1L122; --JB3_w_anode3272w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3272w[3] JB3_w_anode3272w[3] = N1L132 & JB3L13 & JB3L69 & !N1L122; --JB3_w_anode3302w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3302w[3] JB3_w_anode3302w[3] = N1L132 & N1L122 & JB3L17 & JB3L69; --JB3L14 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2919w[3]~23 JB3L14 = JB3L17 & JB3L69 & !N1L132 & !N1L122; --JB3_w_anode2909w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3] JB3_w_anode2909w[3] = N1L122 & JB3L13 & JB3L69 & !N1L132; --JB3L10 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2899w[3]~18 JB3L10 = JB3L13 & JB3L69 & !N1L132 & !N1L122; --JB3_w_anode2929w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3] JB3_w_anode2929w[3] = N1L122 & JB3L17 & JB3L69 & !N1L132; --JB3_w_anode3262w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3262w[3] JB3_w_anode3262w[3] = N1L132 & N1L122 & JB3L9 & JB3L69; --JB3L5 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3]~21 JB3L5 = !N1L124 & !N1L126; --JB3_w_anode2869w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3] JB3_w_anode2869w[3] = N1L122 & JB3L5 & JB3L69 & !N1L132; --JB3_w_anode2889w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3] JB3_w_anode2889w[3] = N1L122 & JB3L9 & JB3L69 & !N1L132; --JB3_w_anode3355w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3355w[3] JB3_w_anode3355w[3] = N1L132 & N1L122 & JB3L18 & JB3L9; --JB3_w_anode2983w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2983w[3] JB3_w_anode2983w[3] = N1L122 & JB3L18 & JB3L9 & !N1L132; --N1_ADDR_d[0] is VGA_OSD_RAM:u9|ADDR_d[0] N1_ADDR_d[0] = DFFEAS(M1_oAddress[0], S2__clk0, KEY[0], , , , , , ); --N1_ADDR_d[1] is VGA_OSD_RAM:u9|ADDR_d[1] N1_ADDR_d[1] = DFFEAS(N1L100, S2__clk0, KEY[0], , , , , , ); --N1_ADDR_d[2] is VGA_OSD_RAM:u9|ADDR_d[2] N1_ADDR_d[2] = DFFEAS(N1L102, S2__clk0, KEY[0], , , , , , ); --Q1L142 is AUDIO_DAC:u11|LRCK_2X_DIV[0]~128 Q1L142 = Q1_LRCK_2X_DIV[0] $ VCC; --Q1L143 is AUDIO_DAC:u11|LRCK_2X_DIV[0]~129 Q1L143 = CARRY(Q1_LRCK_2X_DIV[0]); --Q1L145 is AUDIO_DAC:u11|LRCK_2X_DIV[1]~130 Q1L145 = Q1_LRCK_2X_DIV[1] & !Q1L143 # !Q1_LRCK_2X_DIV[1] & (Q1L143 # GND); --Q1L146 is AUDIO_DAC:u11|LRCK_2X_DIV[1]~131 Q1L146 = CARRY(!Q1L143 # !Q1_LRCK_2X_DIV[1]); --Q1L148 is AUDIO_DAC:u11|LRCK_2X_DIV[2]~132 Q1L148 = Q1_LRCK_2X_DIV[2] & (Q1L146 $ GND) # !Q1_LRCK_2X_DIV[2] & !Q1L146 & VCC; --Q1L149 is AUDIO_DAC:u11|LRCK_2X_DIV[2]~133 Q1L149 = CARRY(Q1_LRCK_2X_DIV[2] & !Q1L146); --Q1L151 is AUDIO_DAC:u11|LRCK_2X_DIV[3]~134 Q1L151 = Q1_LRCK_2X_DIV[3] & !Q1L149 # !Q1_LRCK_2X_DIV[3] & (Q1L149 # GND); --Q1L152 is AUDIO_DAC:u11|LRCK_2X_DIV[3]~135 Q1L152 = CARRY(!Q1L149 # !Q1_LRCK_2X_DIV[3]); --Q1L154 is AUDIO_DAC:u11|LRCK_2X_DIV[4]~136 Q1L154 = Q1_LRCK_2X_DIV[4] & (Q1L152 $ GND) # !Q1_LRCK_2X_DIV[4] & !Q1L152 & VCC; --Q1L155 is AUDIO_DAC:u11|LRCK_2X_DIV[4]~137 Q1L155 = CARRY(Q1_LRCK_2X_DIV[4] & !Q1L152); --Q1L157 is AUDIO_DAC:u11|LRCK_2X_DIV[5]~138 Q1L157 = Q1_LRCK_2X_DIV[5] & !Q1L155 # !Q1_LRCK_2X_DIV[5] & (Q1L155 # GND); --Q1L158 is AUDIO_DAC:u11|LRCK_2X_DIV[5]~139 Q1L158 = CARRY(!Q1L155 # !Q1_LRCK_2X_DIV[5]); --Q1L160 is AUDIO_DAC:u11|LRCK_2X_DIV[6]~140 Q1L160 = Q1_LRCK_2X_DIV[6] & (Q1L158 $ GND) # !Q1_LRCK_2X_DIV[6] & !Q1L158 & VCC; --Q1L161 is AUDIO_DAC:u11|LRCK_2X_DIV[6]~141 Q1L161 = CARRY(Q1_LRCK_2X_DIV[6] & !Q1L158); --Q1L163 is AUDIO_DAC:u11|LRCK_2X_DIV[7]~142 Q1L163 = Q1_LRCK_2X_DIV[7] $ Q1L161; --Q1L5 is AUDIO_DAC:u11|BCK_DIV~127 Q1L5 = Q1_BCK_DIV[1] & Q1_BCK_DIV[0] & !Q1_BCK_DIV[2] # !Q1_BCK_DIV[1] & !Q1_BCK_DIV[0] & Q1_BCK_DIV[2]; --Q1L6 is AUDIO_DAC:u11|BCK_DIV~128 Q1L6 = !Q1_BCK_DIV[2] & (Q1_BCK_DIV[1] $ Q1_BCK_DIV[0]); --Q1L7 is AUDIO_DAC:u11|BCK_DIV~129 Q1L7 = !Q1_BCK_DIV[0] & (!Q1_BCK_DIV[1] # !Q1_BCK_DIV[2]); --CB1_DIN1[0] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[0] CB1_DIN1[0] = DFFEAS(Y1L35, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[1] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[1] CB1_DIN1[1] = DFFEAS(Y1L36, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[2] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[2] CB1_DIN1[2] = DFFEAS(Y1L37, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[3] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[3] CB1_DIN1[3] = DFFEAS(Y1L38, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[4] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[4] CB1_DIN1[4] = DFFEAS(Y1L39, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[5] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[5] CB1_DIN1[5] = DFFEAS(Y1L40, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[6] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[6] CB1_DIN1[6] = DFFEAS(Y1L41, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[7] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[7] CB1_DIN1[7] = DFFEAS(Y1L42, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[8] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[8] CB1_DIN1[8] = DFFEAS(Y1L43, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[9] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[9] CB1_DIN1[9] = DFFEAS(Y1L44, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[10] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[10] CB1_DIN1[10] = DFFEAS(Y1L45, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[11] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[11] CB1_DIN1[11] = DFFEAS(Y1L46, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[12] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[12] CB1_DIN1[12] = DFFEAS(Y1L47, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[13] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[13] CB1_DIN1[13] = DFFEAS(Y1L48, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[14] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[14] CB1_DIN1[14] = DFFEAS(Y1L49, S1__clk0, KEY[0], , , , , , ); --CB1_DIN1[15] is Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[15] CB1_DIN1[15] = DFFEAS(Y1L50, S1__clk0, KEY[0], , , , , , ); --K1_oFL_DATA[0] is CMD_Decode:u5|oFL_DATA[0] K1_oFL_DATA[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, , , K1L264, , , , ); --W1L55 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[0]~64 W1L55 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[0]; --K1_oFL_DATA[1] is CMD_Decode:u5|oFL_DATA[1] K1_oFL_DATA[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, , , K1L264, , , , ); --W1L56 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[1]~65 W1L56 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[1]; --K1_oFL_DATA[2] is CMD_Decode:u5|oFL_DATA[2] K1_oFL_DATA[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, , , K1L264, , , , ); --W1L57 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[2]~66 W1L57 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[2]; --K1_oFL_DATA[3] is CMD_Decode:u5|oFL_DATA[3] K1_oFL_DATA[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, , , K1L264, , , , ); --W1L58 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[3]~67 W1L58 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[3]; --K1_oFL_DATA[4] is CMD_Decode:u5|oFL_DATA[4] K1_oFL_DATA[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, , , K1L264, , , , ); --W1L59 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[4]~68 W1L59 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[4]; --K1_oFL_DATA[5] is CMD_Decode:u5|oFL_DATA[5] K1_oFL_DATA[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, , , K1L264, , , , ); --W1L60 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[5]~69 W1L60 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[5]; --K1_oFL_DATA[6] is CMD_Decode:u5|oFL_DATA[6] K1_oFL_DATA[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, , , K1L264, , , , ); --W1L61 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[6]~70 W1L61 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[6]; --K1_oFL_DATA[7] is CMD_Decode:u5|oFL_DATA[7] K1_oFL_DATA[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, , , K1L264, , , , ); --W1L62 is Multi_Flash:u2|Flash_Multiplexer:u0|oFL_DATA[7]~71 W1L62 = K1_oFL_Select[0] # K1_oFL_Select[1] # K1_oFL_DATA[7]; --MB1L57 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1104 MB1L57 = MB1L40Q & MB1L46Q & MB1L49Q & MB1L43Q; --MB1_SD[9] is I2C_AV_Config:u10|I2C_Controller:u0|SD[9] MB1_SD[9] = DFFEAS(P1_mI2C_DATA[9], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1_SD[2] is I2C_AV_Config:u10|I2C_Controller:u0|SD[2] MB1_SD[2] = DFFEAS(P1_mI2C_DATA[2], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L58 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1105 MB1L58 = MB1L49Q & MB1_SD[9] # !MB1L49Q & (MB1_SD[2]); --MB1_SD[1] is I2C_AV_Config:u10|I2C_Controller:u0|SD[1] MB1_SD[1] = DFFEAS(P1_mI2C_DATA[1], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L59 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1106 MB1L59 = MB1L40Q & MB1L58 # !MB1L40Q & (MB1_SD[1] & !MB1L49Q); --MB1_SD[7] is I2C_AV_Config:u10|I2C_Controller:u0|SD[7] MB1_SD[7] = DFFEAS(P1_mI2C_DATA[7], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1_SD[0] is I2C_AV_Config:u10|I2C_Controller:u0|SD[0] MB1_SD[0] = DFFEAS(P1_mI2C_DATA[0], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L60 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1107 MB1L60 = MB1L40Q & (MB1_SD[0] # MB1L49Q) # !MB1L40Q & (MB1_SD[7] # !MB1L49Q); --MB1_SD[11] is I2C_AV_Config:u10|I2C_Controller:u0|SD[11] MB1_SD[11] = DFFEAS(P1_mI2C_DATA[11], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1_SD[10] is I2C_AV_Config:u10|I2C_Controller:u0|SD[10] MB1_SD[10] = DFFEAS(P1_mI2C_DATA[10], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L61 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1108 MB1L61 = MB1L40Q & MB1_SD[11] # !MB1L40Q & (MB1_SD[10]); --MB1_SD[4] is I2C_AV_Config:u10|I2C_Controller:u0|SD[4] MB1_SD[4] = DFFEAS(P1_mI2C_DATA[4], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L62 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1109 MB1L62 = MB1L49Q & MB1L61 # !MB1L49Q & (MB1_SD[4]); --MB1L63 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1110 MB1L63 = MB1L43Q & (MB1L46Q & (MB1L62) # !MB1L46Q & MB1L60) # !MB1L43Q & (!MB1L46Q); --MB1_SD[6] is I2C_AV_Config:u10|I2C_Controller:u0|SD[6] MB1_SD[6] = DFFEAS(P1_mI2C_DATA[6], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L64 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1111 MB1L64 = MB1L49Q & MB1_SD[6] # !MB1L49Q & (!MB1L40Q & !MB1L25Q); --MB1L65 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1112 MB1L65 = MB1L43Q & (MB1L63) # !MB1L43Q & (MB1L63 & (MB1L64) # !MB1L63 & MB1L59); --MB1_SD[12] is I2C_AV_Config:u10|I2C_Controller:u0|SD[12] MB1_SD[12] = DFFEAS(P1_mI2C_DATA[12], P1_mI2C_CTRL_CLK, , , MB1L36, , , , ); --MB1L66 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1113 MB1L66 = MB1L40Q & (MB1L46Q & (!MB1L43Q) # !MB1L46Q & (MB1L43Q # !MB1L49Q)) # !MB1L40Q & (MB1L49Q & (MB1L46Q # !MB1L43Q) # !MB1L49Q & (MB1L43Q)); --MB1L67 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1114 MB1L67 = MB1L49Q & (MB1L40Q $ (!MB1L46Q & MB1L43Q)) # !MB1L49Q & MB1L46Q & (MB1L40Q $ !MB1L43Q); --MB1L68 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1115 MB1L68 = MB1L66 & !MB1L25Q & (MB1L67) # !MB1L66 & (MB1_SD[12] # MB1L67); --MB1L69 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1116 MB1L69 = MB1L55Q & (MB1L52Q & (MB1L68) # !MB1L52Q & MB1L65) # !MB1L55Q & (!MB1L52Q); --MB1L70 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1117 MB1L70 = MB1L55Q & (!MB1L69) # !MB1L55Q & MB1L25Q & (MB1L69 # !MB1L57); --U1_rCont[2] is USB_JTAG:u1|JTAG_REC:u0|rCont[2] U1_rCont[2] = DFFEAS(U1L19, F1_mTCK, !TCS, , , , , , ); --U1_rCont[1] is USB_JTAG:u1|JTAG_REC:u0|rCont[1] U1_rCont[1] = DFFEAS(U1L17, F1_mTCK, !TCS, , , , , , ); --U1_rCont[0] is USB_JTAG:u1|JTAG_REC:u0|rCont[0] U1_rCont[0] = DFFEAS(U1L15, F1_mTCK, !TCS, , , , , , ); --U1L1 is USB_JTAG:u1|JTAG_REC:u0|Equal~87 U1L1 = !U1_rCont[2] & !U1_rCont[1] & !U1_rCont[0]; --F1_mTCK is USB_JTAG:u1|mTCK F1_mTCK = DFFEAS(R1_wire_clkctrl1_outclk, CLOCK_50, , , , , , , ); --U1L11 is USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[7]~8 U1L11 = !TCS & !U1_rCont[2] & !U1_rCont[1] & !U1_rCont[0]; --U1_rDATA[4] is USB_JTAG:u1|JTAG_REC:u0|rDATA[4] U1_rDATA[4] = DFFEAS(U1_rDATA[5], F1_mTCK, , , !TCS, , , , ); --U1_rDATA[5] is USB_JTAG:u1|JTAG_REC:u0|rDATA[5] U1_rDATA[5] = DFFEAS(U1_rDATA[6], F1_mTCK, , , !TCS, , , , ); --U1_rDATA[1] is USB_JTAG:u1|JTAG_REC:u0|rDATA[1] U1_rDATA[1] = DFFEAS(U1_rDATA[2], F1_mTCK, , , !TCS, , , , ); --U1_rDATA[7] is USB_JTAG:u1|JTAG_REC:u0|rDATA[7] U1_rDATA[7] = DFFEAS(TDI, F1_mTCK, , , !TCS, , , , ); --U1_rDATA[3] is USB_JTAG:u1|JTAG_REC:u0|rDATA[3] U1_rDATA[3] = DFFEAS(U1_rDATA[4], F1_mTCK, , , !TCS, , , , ); --U1_rDATA[6] is USB_JTAG:u1|JTAG_REC:u0|rDATA[6] U1_rDATA[6] = DFFEAS(U1_rDATA[7], F1_mTCK, , , !TCS, , , , ); --U1_rDATA[2] is USB_JTAG:u1|JTAG_REC:u0|rDATA[2] U1_rDATA[2] = DFFEAS(U1_rDATA[3], F1_mTCK, , , !TCS, , , , ); --K1L351 is CMD_Decode:u5|oSDR_ADDR[0]~43 K1L351 = KEY[0] & K1_f_SDRAM & K1L156 & !K1_mSDR_ST.000; --Z1_CMD[1] is Multi_Sdram:u3|Sdram_Controller:u1|CMD[1] Z1_CMD[1] = DFFEAS(Z1L102, S1__clk0, KEY[0], , Z1L9, , , , ); --Z1_CMD[0] is Multi_Sdram:u3|Sdram_Controller:u1|CMD[0] Z1_CMD[0] = DFFEAS(Z1L103, S1__clk0, KEY[0], , Z1L9, , , , ); --BB1L2 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~875 BB1L2 = Z1_CMD[1] & !Z1_CMD[0]; --AB1_rp_shift[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[0] AB1_rp_shift[0] = DFFEAS(AB1L110, S1__clk0, KEY[0], , AB1L107, , , , ); --AB1_command_delay[0] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[0] AB1_command_delay[0] = DFFEAS(AB1L72, S1__clk0, KEY[0], , , , , , ); --AB1L102 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done~76 AB1L102 = !BB1_INIT_REQ & (AB1_rp_shift[0] # AB1_command_done & !AB1_command_delay[0]); --AB1L64 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[0]~331 AB1L64 = AB1_command_done & !AB1_command_delay[0]; --AB1_ex_read is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_read AB1_ex_read = DFFEAS(AB1L94, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1_ex_write is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_write AB1_ex_write = DFFEAS(AB1L96, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1L106 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[1]~912 AB1L106 = AB1_ex_read # AB1_ex_write; --AB1L107 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[1]~913 AB1L107 = BB1_INIT_REQ # Z1_PM_STOP # AB1L64 # !AB1L106; --AB1L81 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_done~132 AB1L81 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[0] # !AB1L116); --BB1_init_timer[9] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[9] BB1_init_timer[9] = DFFEAS(BB1L92, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[6] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[6] BB1_init_timer[6] = DFFEAS(BB1L83, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[7] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[7] BB1_init_timer[7] = DFFEAS(BB1L86, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[8] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[8] BB1_init_timer[8] = DFFEAS(BB1L89, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L25 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|PRECHARGE~36 BB1L25 = BB1_init_timer[6] & BB1_init_timer[7] & BB1_init_timer[8]; --BB1_init_timer[10] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[10] BB1_init_timer[10] = DFFEAS(BB1L95, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[11] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[11] BB1_init_timer[11] = DFFEAS(BB1L98, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[12] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[12] BB1_init_timer[12] = DFFEAS(BB1L101, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L17 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~421 BB1L17 = BB1_init_timer[10] & BB1_init_timer[11] & BB1_init_timer[12]; --BB1L18 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~422 BB1L18 = !BB1_init_timer[9] & !BB1L25 # !BB1L17; --BB1_init_timer[13] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[13] BB1_init_timer[13] = DFFEAS(BB1L104, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[14] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[14] BB1_init_timer[14] = DFFEAS(BB1L107, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[15] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[15] BB1_init_timer[15] = DFFEAS(BB1L110, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L19 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~423 BB1L19 = !BB1_init_timer[15] & (BB1L18 & !BB1_init_timer[13] # !BB1_init_timer[14]); --BB1_timer[0] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[0] BB1_timer[0] = DFFEAS(BB1L114, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[1] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[1] BB1_timer[1] = DFFEAS(BB1L117, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[2] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[2] BB1_timer[2] = DFFEAS(BB1L120, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[3] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[3] BB1_timer[3] = DFFEAS(BB1L123, S1__clk0, KEY[0], , , AB1L19, , , BB1L33); --BB1L3 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~876 BB1L3 = !BB1_timer[0] & !BB1_timer[1] & !BB1_timer[2] & !BB1_timer[3]; --BB1_timer[4] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[4] BB1_timer[4] = DFFEAS(BB1L126, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[5] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[5] BB1_timer[5] = DFFEAS(BB1L129, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[6] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[6] BB1_timer[6] = DFFEAS(BB1L132, S1__clk0, KEY[0], , , AB1L19, , , BB1L33); --BB1_timer[7] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[7] BB1_timer[7] = DFFEAS(BB1L135, S1__clk0, KEY[0], , , AB1L19, , , BB1L33); --BB1L4 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~877 BB1L4 = !BB1_timer[4] & !BB1_timer[5] & !BB1_timer[6] & !BB1_timer[7]; --BB1_timer[8] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[8] BB1_timer[8] = DFFEAS(BB1L138, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[9] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[9] BB1_timer[9] = DFFEAS(BB1L141, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[10] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[10] BB1_timer[10] = DFFEAS(BB1L144, S1__clk0, KEY[0], , , VCC, , , BB1L33); --BB1_timer[11] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[11] BB1_timer[11] = DFFEAS(BB1L147, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1L5 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~878 BB1L5 = !BB1_timer[8] & !BB1_timer[9] & !BB1_timer[10] & !BB1_timer[11]; --BB1_timer[12] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[12] BB1_timer[12] = DFFEAS(BB1L150, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[13] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[13] BB1_timer[13] = DFFEAS(BB1L153, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[14] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[14] BB1_timer[14] = DFFEAS(BB1L156, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1_timer[15] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[15] BB1_timer[15] = DFFEAS(BB1L159, S1__clk0, KEY[0], , , ~GND, , , BB1L33); --BB1L6 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~879 BB1L6 = !BB1_timer[12] & !BB1_timer[13] & !BB1_timer[14] & !BB1_timer[15]; --BB1L7 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~880 BB1L7 = BB1L3 & BB1L4 & BB1L5 & BB1L6; --AB1_REF_ACK is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|REF_ACK AB1_REF_ACK = DFFEAS(AB1L18, S1__clk0, KEY[0], , , , , , ); --BB1L32 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REF_REQ~22 BB1L32 = BB1L7 # BB1_REF_REQ & !BB1_INIT_REQ & !AB1_REF_ACK; --BB1L8 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|Equal~881 BB1L8 = Z1_CMD[0] & !Z1_CMD[1]; --BB1_init_timer[0] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[0] BB1_init_timer[0] = DFFEAS(BB1L65, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[1] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[1] BB1_init_timer[1] = DFFEAS(BB1L68, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L11 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~85 BB1L11 = BB1_init_timer[14] & !BB1_init_timer[13] & !BB1_init_timer[0] & !BB1_init_timer[1]; --BB1L12 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~86 BB1L12 = BB1L17 & BB1L11 & !BB1_init_timer[15]; --BB1_init_timer[4] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[4] BB1_init_timer[4] = DFFEAS(BB1L77, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[5] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[5] BB1_init_timer[5] = DFFEAS(BB1L80, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L13 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~87 BB1L13 = !BB1_init_timer[6] & !BB1_init_timer[4] & !BB1_init_timer[5]; --BB1_init_timer[3] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] BB1_init_timer[3] = DFFEAS(BB1L74, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1_init_timer[2] is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[2] BB1_init_timer[2] = DFFEAS(BB1L71, S1__clk0, KEY[0], , BB1L23, , , , ); --BB1L14 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~88 BB1L14 = BB1_init_timer[9] & BB1_init_timer[3] & !BB1_init_timer[8] & !BB1_init_timer[2]; --BB1L15 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~89 BB1L15 = BB1_init_timer[7] & BB1L13 & BB1L14; --BB1L59 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|always3~646 BB1L59 = BB1_init_timer[3] & (BB1_init_timer[5] & !BB1_init_timer[2] & BB1_init_timer[4] # !BB1_init_timer[5] & BB1_init_timer[2] & !BB1_init_timer[4]) # !BB1_init_timer[3] & (BB1_init_timer[5] $ (!BB1_init_timer[2] & BB1_init_timer[4])); --BB1L60 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|always3~647 BB1L60 = BB1_init_timer[5] & (BB1_init_timer[3] $ (BB1_init_timer[2] & !BB1_init_timer[4])) # !BB1_init_timer[5] & !BB1_init_timer[3] & !BB1_init_timer[2] & BB1_init_timer[4]; --BB1L61 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|always3~648 BB1L61 = BB1_init_timer[7] & BB1_init_timer[8] & BB1_init_timer[6] & BB1L60 # !BB1_init_timer[7] & !BB1_init_timer[8] & (BB1_init_timer[6] $ BB1L60); --BB1L62 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|always3~649 BB1L62 = BB1L61 & (BB1_init_timer[9] & BB1L59 & !BB1_init_timer[7] # !BB1_init_timer[9] & !BB1L59 & BB1_init_timer[7]); --BB1L16 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE~90 BB1L16 = BB1L12 & BB1L15 & !BB1L19 & !BB1L62; --Z1_mDONE is Multi_Sdram:u3|Sdram_Controller:u1|mDONE Z1_mDONE = DFFEAS(Z1L148, S1__clk0, KEY[0], , , , , , ); --Z1_Pre_DONE is Multi_Sdram:u3|Sdram_Controller:u1|Pre_DONE Z1_Pre_DONE = DFFEAS(Z1_mDONE, CLOCK_50, KEY[0], , , , , , ); --Z1L30 is Multi_Sdram:u3|Sdram_Controller:u1|DONE~98 Z1L30 = Z1L31 & (Z1_DONE # Z1_mDONE & !Z1_Pre_DONE); --Y1L6 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~142 Y1L6 = Z1_DONE & Y1_ST.01 & (K1_oSDR_Select[1] # K1_oSDR_Select[0]); --Y1L7 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~143 Y1L7 = Y1_ST.10 & (K1_oSDR_Select[1] # K1_oSDR_Select[0]); --Y1_ST.00 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.00 Y1_ST.00 = DFFEAS(Y1L9, CLOCK_50, KEY[0], , , , , , ); --Y1L8 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~144 Y1L8 = Y1L1 & (Y1_ST.01 & !Z1_DONE # !Y1_ST.00); --AB1L60 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always3~4 AB1L60 = AB1_do_reada # !AB1L116; --AB1L9 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CM_ACK~102 AB1L9 = AB1_do_refresh & (BB1_REF_REQ & AB1_CM_ACK # !BB1_REF_REQ & (AB1L60)) # !AB1_do_refresh & (AB1L60); --BB1L26 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|PRECHARGE~37 BB1L26 = BB1_init_timer[2] & BB1_init_timer[4] & !BB1_init_timer[3] & !BB1_init_timer[5]; --BB1L27 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|PRECHARGE~38 BB1L27 = BB1L25 & BB1L12 & BB1L26 & !BB1_init_timer[9]; --AB1_rw_shift[1] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_shift[1] AB1_rw_shift[1] = DFFEAS(AB1L61, S1__clk0, KEY[0], , , , , , ); --AB1L121 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_shift~15 AB1L121 = AB1_rw_shift[1] & !AB1_do_writea & !AB1_do_reada; --BB1L30 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REFRESH~81 BB1L30 = BB1L12 & BB1L62 & !BB1L19; --Q1L169 is AUDIO_DAC:u11|LRCK_4X_DIV[0]~111 Q1L169 = Q1_LRCK_4X_DIV[0] $ VCC; --Q1L170 is AUDIO_DAC:u11|LRCK_4X_DIV[0]~112 Q1L170 = CARRY(Q1_LRCK_4X_DIV[0]); --Q1L172 is AUDIO_DAC:u11|LRCK_4X_DIV[1]~113 Q1L172 = Q1_LRCK_4X_DIV[1] & !Q1L170 # !Q1_LRCK_4X_DIV[1] & (Q1L170 # GND); --Q1L173 is AUDIO_DAC:u11|LRCK_4X_DIV[1]~114 Q1L173 = CARRY(!Q1L170 # !Q1_LRCK_4X_DIV[1]); --Q1L175 is AUDIO_DAC:u11|LRCK_4X_DIV[2]~115 Q1L175 = Q1_LRCK_4X_DIV[2] & (Q1L173 $ GND) # !Q1_LRCK_4X_DIV[2] & !Q1L173 & VCC; --Q1L176 is AUDIO_DAC:u11|LRCK_4X_DIV[2]~116 Q1L176 = CARRY(Q1_LRCK_4X_DIV[2] & !Q1L173); --Q1L178 is AUDIO_DAC:u11|LRCK_4X_DIV[3]~117 Q1L178 = Q1_LRCK_4X_DIV[3] & !Q1L176 # !Q1_LRCK_4X_DIV[3] & (Q1L176 # GND); --Q1L179 is AUDIO_DAC:u11|LRCK_4X_DIV[3]~118 Q1L179 = CARRY(!Q1L176 # !Q1_LRCK_4X_DIV[3]); --Q1L181 is AUDIO_DAC:u11|LRCK_4X_DIV[4]~119 Q1L181 = Q1_LRCK_4X_DIV[4] & (Q1L179 $ GND) # !Q1_LRCK_4X_DIV[4] & !Q1L179 & VCC; --Q1L182 is AUDIO_DAC:u11|LRCK_4X_DIV[4]~120 Q1L182 = CARRY(Q1_LRCK_4X_DIV[4] & !Q1L179); --Q1L184 is AUDIO_DAC:u11|LRCK_4X_DIV[5]~121 Q1L184 = Q1_LRCK_4X_DIV[5] & !Q1L182 # !Q1_LRCK_4X_DIV[5] & (Q1L182 # GND); --Q1L185 is AUDIO_DAC:u11|LRCK_4X_DIV[5]~122 Q1L185 = CARRY(!Q1L182 # !Q1_LRCK_4X_DIV[5]); --Q1L187 is AUDIO_DAC:u11|LRCK_4X_DIV[6]~123 Q1L187 = Q1_LRCK_4X_DIV[6] $ !Q1L185; --W1L9 is Multi_Flash:u2|Flash_Multiplexer:u0|ST~167 W1L9 = !W1_ST.11 & (K1_oFL_Select[0] # K1_oFL_Select[1]); --X1L17 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[0]~1076 X1L17 = X1L125 & (X1_Cont_Finish[0] $ VCC) # !X1L125 & X1_Cont_Finish[0] & VCC; --X1L18 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[0]~1077 X1L18 = CARRY(X1L125 & X1_Cont_Finish[0]); --X1L20 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[1]~1078 X1L20 = X1_Cont_Finish[1] & !X1L18 # !X1_Cont_Finish[1] & (X1L18 # GND); --X1L21 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[1]~1079 X1L21 = CARRY(!X1L18 # !X1_Cont_Finish[1]); --X1L23 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[2]~1080 X1L23 = X1_Cont_Finish[2] & (X1L21 $ GND) # !X1_Cont_Finish[2] & !X1L21 & VCC; --X1L24 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[2]~1081 X1L24 = CARRY(X1_Cont_Finish[2] & !X1L21); --X1L26 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[3]~1082 X1L26 = X1_Cont_Finish[3] & !X1L24 # !X1_Cont_Finish[3] & (X1L24 # GND); --X1L27 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[3]~1083 X1L27 = CARRY(!X1L24 # !X1_Cont_Finish[3]); --X1L29 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[4]~1084 X1L29 = X1_Cont_Finish[4] & (X1L27 $ GND) # !X1_Cont_Finish[4] & !X1L27 & VCC; --X1L30 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[4]~1085 X1L30 = CARRY(X1_Cont_Finish[4] & !X1L27); --X1L32 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[5]~1086 X1L32 = X1_Cont_Finish[5] & !X1L30 # !X1_Cont_Finish[5] & (X1L30 # GND); --X1L33 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[5]~1087 X1L33 = CARRY(!X1L30 # !X1_Cont_Finish[5]); --X1L35 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[6]~1088 X1L35 = X1_Cont_Finish[6] & (X1L33 $ GND) # !X1_Cont_Finish[6] & !X1L33 & VCC; --X1L36 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[6]~1089 X1L36 = CARRY(X1_Cont_Finish[6] & !X1L33); --X1L38 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[7]~1090 X1L38 = X1_Cont_Finish[7] & !X1L36 # !X1_Cont_Finish[7] & (X1L36 # GND); --X1L39 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[7]~1091 X1L39 = CARRY(!X1L36 # !X1_Cont_Finish[7]); --X1L41 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[8]~1092 X1L41 = X1_Cont_Finish[8] & (X1L39 $ GND) # !X1_Cont_Finish[8] & !X1L39 & VCC; --X1L42 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[8]~1093 X1L42 = CARRY(X1_Cont_Finish[8] & !X1L39); --X1L44 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[9]~1094 X1L44 = X1_Cont_Finish[9] & !X1L42 # !X1_Cont_Finish[9] & (X1L42 # GND); --X1L45 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[9]~1095 X1L45 = CARRY(!X1L42 # !X1_Cont_Finish[9]); --X1L47 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[10]~1096 X1L47 = X1_Cont_Finish[10] & (X1L45 $ GND) # !X1_Cont_Finish[10] & !X1L45 & VCC; --X1L48 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[10]~1097 X1L48 = CARRY(X1_Cont_Finish[10] & !X1L45); --X1L50 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[11]~1098 X1L50 = X1_Cont_Finish[11] & !X1L48 # !X1_Cont_Finish[11] & (X1L48 # GND); --X1L51 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[11]~1099 X1L51 = CARRY(!X1L48 # !X1_Cont_Finish[11]); --X1L53 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[12]~1100 X1L53 = X1_Cont_Finish[12] & (X1L51 $ GND) # !X1_Cont_Finish[12] & !X1L51 & VCC; --X1L54 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[12]~1101 X1L54 = CARRY(X1_Cont_Finish[12] & !X1L51); --X1L56 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[13]~1102 X1L56 = X1_Cont_Finish[13] & !X1L54 # !X1_Cont_Finish[13] & (X1L54 # GND); --X1L57 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[13]~1103 X1L57 = CARRY(!X1L54 # !X1_Cont_Finish[13]); --X1L59 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[14]~1104 X1L59 = X1_Cont_Finish[14] & (X1L57 $ GND) # !X1_Cont_Finish[14] & !X1L57 & VCC; --X1L60 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[14]~1105 X1L60 = CARRY(X1_Cont_Finish[14] & !X1L57); --X1L62 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[15]~1106 X1L62 = X1_Cont_Finish[15] & !X1L60 # !X1_Cont_Finish[15] & (X1L60 # GND); --X1L63 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[15]~1107 X1L63 = CARRY(!X1L60 # !X1_Cont_Finish[15]); --X1L65 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[16]~1108 X1L65 = X1_Cont_Finish[16] & (X1L63 $ GND) # !X1_Cont_Finish[16] & !X1L63 & VCC; --X1L66 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[16]~1109 X1L66 = CARRY(X1_Cont_Finish[16] & !X1L63); --X1L68 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[17]~1110 X1L68 = X1_Cont_Finish[17] & !X1L66 # !X1_Cont_Finish[17] & (X1L66 # GND); --X1L69 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[17]~1111 X1L69 = CARRY(!X1L66 # !X1_Cont_Finish[17]); --X1L71 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[18]~1112 X1L71 = X1_Cont_Finish[18] & (X1L69 $ GND) # !X1_Cont_Finish[18] & !X1L69 & VCC; --X1L72 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[18]~1113 X1L72 = CARRY(X1_Cont_Finish[18] & !X1L69); --X1L74 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[19]~1114 X1L74 = X1_Cont_Finish[19] & !X1L72 # !X1_Cont_Finish[19] & (X1L72 # GND); --X1L75 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[19]~1115 X1L75 = CARRY(!X1L72 # !X1_Cont_Finish[19]); --X1L254 is Multi_Flash:u2|Flash_Controller:u1|reduce_or~111 X1L254 = X1_r_CMD[0] $ X1_r_CMD[2]; --X1L77 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[20]~1116 X1L77 = X1_Cont_Finish[20] & (X1L75 $ GND) # !X1_Cont_Finish[20] & !X1L75 & VCC; --X1L78 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[20]~1117 X1L78 = CARRY(X1_Cont_Finish[20] & !X1L75); --X1L80 is Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[21]~1118 X1L80 = X1_Cont_Finish[21] $ X1L78; --K1L135 is CMD_Decode:u5|Select~2960 K1L135 = W1L72 & K1_mFL_ST.011; --K1L136 is CMD_Decode:u5|Select~2961 K1L136 = W1L72 & K1_mFL_ST.001; --X1_Cont_DIV[1] is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[1] X1_Cont_DIV[1] = DFFEAS(X1L10, CLOCK_50, KEY[0], , , , , , ); --X1_Cont_DIV[0] is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[0] X1_Cont_DIV[0] = DFFEAS(X1L7, CLOCK_50, KEY[0], , , , , , ); --X1L7 is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[0]~80 X1L7 = X1_Cont_DIV[0] $ VCC; --X1L8 is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[0]~81 X1L8 = CARRY(X1_Cont_DIV[0]); --X1L10 is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[1]~82 X1L10 = X1_Cont_DIV[1] & !X1L8 # !X1_Cont_DIV[1] & (X1L8 # GND); --X1L11 is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[1]~83 X1L11 = CARRY(!X1L8 # !X1_Cont_DIV[1]); --X1L13 is Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[2]~84 X1L13 = X1_Cont_DIV[2] $ !X1L11; --J1L131 is ps2_keyboard:u4|q~1254 J1L131 = KEY[0] & J1_q[8]; --J1_m1_state.m1_tx_rising_edge_marker is ps2_keyboard:u4|m1_state.m1_tx_rising_edge_marker J1_m1_state.m1_tx_rising_edge_marker = DFFEAS(J1L109, CLOCK_50, , , , , , , ); --J1_m1_state.m1_rx_falling_edge_marker is ps2_keyboard:u4|m1_state.m1_rx_falling_edge_marker J1_m1_state.m1_rx_falling_edge_marker = DFFEAS(J1L110, CLOCK_50, , , , , , , ); --J1L124 is ps2_keyboard:u4|q[4]~1255 J1L124 = J1_m1_state.m1_tx_rising_edge_marker # J1_m1_state.m1_rx_falling_edge_marker # !KEY[0]; --J1L132 is ps2_keyboard:u4|q~1256 J1L132 = KEY[0] & J1_q[7]; --J1L133 is ps2_keyboard:u4|q~1257 J1L133 = KEY[0] & J1_q[6]; --J1_q[9] is ps2_keyboard:u4|q[9] J1_q[9] = DFFEAS(J1L139, CLOCK_50, , , J1L124, , , , ); --J1L134 is ps2_keyboard:u4|q~1258 J1L134 = KEY[0] & J1_q[9]; --J1L135 is ps2_keyboard:u4|q~1259 J1L135 = KEY[0] & J1_q[4]; --J1L136 is ps2_keyboard:u4|q~1260 J1L136 = KEY[0] & J1_q[2]; --J1L91 is ps2_keyboard:u4|left_shift_key~23 J1L91 = J1_left_shift_key # J1L19 & J1L21 & !J1L257; --J1L246 is ps2_keyboard:u4|right_shift_key~23 J1L246 = J1_right_shift_key # J1L10 & J1L38 & !J1L257; --J1L137 is ps2_keyboard:u4|q~1261 J1L137 = KEY[0] & J1_q[3]; --J1L138 is ps2_keyboard:u4|q~1262 J1L138 = KEY[0] & J1_q[5]; --J1L74 is ps2_keyboard:u4|always5~4 J1L74 = J1_m1_state.m1_tx_rising_edge_marker # J1_m1_state.m1_rx_falling_edge_marker; --J1L77 is ps2_keyboard:u4|bit_count[0]~142 J1L77 = J1_bit_count[0] & (J1L74 $ VCC) # !J1_bit_count[0] & J1L74 & VCC; --J1L78 is ps2_keyboard:u4|bit_count[0]~143 J1L78 = CARRY(J1_bit_count[0] & J1L74); --J1L80 is ps2_keyboard:u4|bit_count[1]~144 J1L80 = J1_bit_count[1] & !J1L78 # !J1_bit_count[1] & (J1L78 # GND); --J1L81 is ps2_keyboard:u4|bit_count[1]~145 J1L81 = CARRY(!J1L78 # !J1_bit_count[1]); --J1L83 is ps2_keyboard:u4|bit_count[2]~146 J1L83 = J1_bit_count[2] & (J1L81 $ GND) # !J1_bit_count[2] & !J1L81 & VCC; --J1L84 is ps2_keyboard:u4|bit_count[2]~147 J1L84 = CARRY(J1_bit_count[2] & !J1L81); --J1_m1_state.m1_rx_clk_h is ps2_keyboard:u4|m1_state.m1_rx_clk_h J1_m1_state.m1_rx_clk_h = DFFEAS(J1L112, CLOCK_50, , , , , , , ); --J1_ps2_clk_s is ps2_keyboard:u4|ps2_clk_s J1_ps2_clk_s = DFFEAS(PS2_CLK, CLOCK_50, , , , , , , ); --J1L86 is ps2_keyboard:u4|bit_count[3]~148 J1L86 = J1_m1_state.m1_rx_clk_h # !J1_ps2_clk_s; --J1_timer_60usec_count[0] is ps2_keyboard:u4|timer_60usec_count[0] J1_timer_60usec_count[0] = DFFEAS(J1L288, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[2] is ps2_keyboard:u4|timer_60usec_count[2] J1_timer_60usec_count[2] = DFFEAS(J1L294, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[1] is ps2_keyboard:u4|timer_60usec_count[1] J1_timer_60usec_count[1] = DFFEAS(J1L291, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[3] is ps2_keyboard:u4|timer_60usec_count[3] J1_timer_60usec_count[3] = DFFEAS(J1L297, CLOCK_50, , , , , , J1L183, ); --J1L323 is ps2_keyboard:u4|timer_60usec_done~152 J1L323 = J1_timer_60usec_count[0] & J1_timer_60usec_count[2] & !J1_timer_60usec_count[1] & !J1_timer_60usec_count[3]; --J1_timer_60usec_count[7] is ps2_keyboard:u4|timer_60usec_count[7] J1_timer_60usec_count[7] = DFFEAS(J1L309, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[4] is ps2_keyboard:u4|timer_60usec_count[4] J1_timer_60usec_count[4] = DFFEAS(J1L300, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[5] is ps2_keyboard:u4|timer_60usec_count[5] J1_timer_60usec_count[5] = DFFEAS(J1L303, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[6] is ps2_keyboard:u4|timer_60usec_count[6] J1_timer_60usec_count[6] = DFFEAS(J1L306, CLOCK_50, , , , , , J1L183, ); --J1L324 is ps2_keyboard:u4|timer_60usec_done~153 J1L324 = J1_timer_60usec_count[7] & !J1_timer_60usec_count[4] & !J1_timer_60usec_count[5] & !J1_timer_60usec_count[6]; --J1_timer_60usec_count[8] is ps2_keyboard:u4|timer_60usec_count[8] J1_timer_60usec_count[8] = DFFEAS(J1L312, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[9] is ps2_keyboard:u4|timer_60usec_count[9] J1_timer_60usec_count[9] = DFFEAS(J1L315, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[11] is ps2_keyboard:u4|timer_60usec_count[11] J1_timer_60usec_count[11] = DFFEAS(J1L321, CLOCK_50, , , , , , J1L183, ); --J1_timer_60usec_count[10] is ps2_keyboard:u4|timer_60usec_count[10] J1_timer_60usec_count[10] = DFFEAS(J1L318, CLOCK_50, , , , , , J1L183, ); --J1L325 is ps2_keyboard:u4|timer_60usec_done~154 J1L325 = J1_timer_60usec_count[8] & J1_timer_60usec_count[9] & J1_timer_60usec_count[11] & !J1_timer_60usec_count[10]; --J1L326 is ps2_keyboard:u4|timer_60usec_done~155 J1L326 = J1L323 & J1L324 & J1L325; --J1_m1_state.m1_tx_wait_keyboard_ack is ps2_keyboard:u4|m1_state.m1_tx_wait_keyboard_ack J1_m1_state.m1_tx_wait_keyboard_ack = DFFEAS(J1L113, CLOCK_50, , , , , , !KEY[0], ); --J1L87 is ps2_keyboard:u4|bit_count[3]~149 J1L87 = J1L249 # J1_m1_state.m1_tx_wait_keyboard_ack # !J1L86 & J1L326; --J1L88 is ps2_keyboard:u4|bit_count[3]~150 J1L88 = J1_bit_count[3] $ J1L84; --MB1L10 is I2C_AV_Config:u10|I2C_Controller:u0|ACK3~215 MB1L10 = MB1L40Q & MB1L55Q & (MB1L37 # MB1L56); --MB1L71 is I2C_AV_Config:u10|I2C_Controller:u0|Select~1118 MB1L71 = MB1L40Q & (A1L223 & !MB1L46Q) # !MB1L40Q & MB1_ACK1; --MB1L2 is I2C_AV_Config:u10|I2C_Controller:u0|ACK1~170 MB1L2 = MB1L52Q & MB1L55Q & (MB1L46Q $ !MB1L49Q); --MB1L3 is I2C_AV_Config:u10|I2C_Controller:u0|ACK1~171 MB1L3 = MB1L43Q & (MB1L2 & MB1L71 # !MB1L2 & (MB1_ACK1)) # !MB1L43Q & (MB1_ACK1); --MB1L6 is I2C_AV_Config:u10|I2C_Controller:u0|ACK2~251 MB1L6 = MB1L52Q & (!MB1L46Q # !MB1L40Q) # !MB1L52Q & (MB1L40Q # MB1L46Q) # !MB1L55Q; --P1L21 is I2C_AV_Config:u10|Select~137 P1L21 = !P1_mSetup_ST.10 & (MB1_END # P1L89 # !P1_mSetup_ST.01); --K1_oSDR_DATA[0] is CMD_Decode:u5|oSDR_DATA[0] K1_oSDR_DATA[0] = DFFEAS(K1_CMD_Tmp[8], CLOCK_50, , , K1L351, , , , ); --Y1L35 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[0]~240 Y1L35 = K1_oSDR_DATA[0] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[1] is CMD_Decode:u5|oSDR_DATA[1] K1_oSDR_DATA[1] = DFFEAS(K1_CMD_Tmp[9], CLOCK_50, , , K1L351, , , , ); --Y1L36 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[1]~241 Y1L36 = K1_oSDR_DATA[1] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[2] is CMD_Decode:u5|oSDR_DATA[2] K1_oSDR_DATA[2] = DFFEAS(K1_CMD_Tmp[10], CLOCK_50, , , K1L351, , , , ); --Y1L37 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[2]~242 Y1L37 = K1_oSDR_DATA[2] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[3] is CMD_Decode:u5|oSDR_DATA[3] K1_oSDR_DATA[3] = DFFEAS(K1_CMD_Tmp[11], CLOCK_50, , , K1L351, , , , ); --Y1L38 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[3]~243 Y1L38 = K1_oSDR_DATA[3] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[4] is CMD_Decode:u5|oSDR_DATA[4] K1_oSDR_DATA[4] = DFFEAS(K1_CMD_Tmp[12], CLOCK_50, , , K1L351, , , , ); --Y1L39 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[4]~244 Y1L39 = K1_oSDR_DATA[4] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[5] is CMD_Decode:u5|oSDR_DATA[5] K1_oSDR_DATA[5] = DFFEAS(K1_CMD_Tmp[13], CLOCK_50, , , K1L351, , , , ); --Y1L40 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[5]~245 Y1L40 = K1_oSDR_DATA[5] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[6] is CMD_Decode:u5|oSDR_DATA[6] K1_oSDR_DATA[6] = DFFEAS(K1_CMD_Tmp[14], CLOCK_50, , , K1L351, , , , ); --Y1L41 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[6]~246 Y1L41 = K1_oSDR_DATA[6] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[7] is CMD_Decode:u5|oSDR_DATA[7] K1_oSDR_DATA[7] = DFFEAS(K1_CMD_Tmp[15], CLOCK_50, , , K1L351, , , , ); --Y1L42 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[7]~247 Y1L42 = K1_oSDR_DATA[7] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[8] is CMD_Decode:u5|oSDR_DATA[8] K1_oSDR_DATA[8] = DFFEAS(K1_CMD_Tmp[16], CLOCK_50, , , K1L351, , , , ); --Y1L43 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[8]~248 Y1L43 = K1_oSDR_DATA[8] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[9] is CMD_Decode:u5|oSDR_DATA[9] K1_oSDR_DATA[9] = DFFEAS(K1_CMD_Tmp[17], CLOCK_50, , , K1L351, , , , ); --Y1L44 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[9]~249 Y1L44 = K1_oSDR_DATA[9] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[10] is CMD_Decode:u5|oSDR_DATA[10] K1_oSDR_DATA[10] = DFFEAS(K1_CMD_Tmp[18], CLOCK_50, , , K1L351, , , , ); --Y1L45 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[10]~250 Y1L45 = K1_oSDR_DATA[10] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[11] is CMD_Decode:u5|oSDR_DATA[11] K1_oSDR_DATA[11] = DFFEAS(K1_CMD_Tmp[19], CLOCK_50, , , K1L351, , , , ); --Y1L46 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[11]~251 Y1L46 = K1_oSDR_DATA[11] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[12] is CMD_Decode:u5|oSDR_DATA[12] K1_oSDR_DATA[12] = DFFEAS(K1_CMD_Tmp[20], CLOCK_50, , , K1L351, , , , ); --Y1L47 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[12]~252 Y1L47 = K1_oSDR_DATA[12] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[13] is CMD_Decode:u5|oSDR_DATA[13] K1_oSDR_DATA[13] = DFFEAS(K1_CMD_Tmp[21], CLOCK_50, , , K1L351, , , , ); --Y1L48 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[13]~253 Y1L48 = K1_oSDR_DATA[13] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[14] is CMD_Decode:u5|oSDR_DATA[14] K1_oSDR_DATA[14] = DFFEAS(K1_CMD_Tmp[22], CLOCK_50, , , K1L351, , , , ); --Y1L49 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[14]~254 Y1L49 = K1_oSDR_DATA[14] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --K1_oSDR_DATA[15] is CMD_Decode:u5|oSDR_DATA[15] K1_oSDR_DATA[15] = DFFEAS(K1_CMD_Tmp[23], CLOCK_50, , , K1L351, , , , ); --Y1L50 is Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_DATA[15]~255 Y1L50 = K1_oSDR_DATA[15] & !K1_oSDR_Select[1] & !K1_oSDR_Select[0]; --P1_mI2C_DATA[9] is I2C_AV_Config:u10|mI2C_DATA[9] P1_mI2C_DATA[9] = DFFEAS(P1L91, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[2] is I2C_AV_Config:u10|mI2C_DATA[2] P1_mI2C_DATA[2] = DFFEAS(P1L1, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[1] is I2C_AV_Config:u10|mI2C_DATA[1] P1_mI2C_DATA[1] = DFFEAS(P1L92, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[7] is I2C_AV_Config:u10|mI2C_DATA[7] P1_mI2C_DATA[7] = DFFEAS(P1L2, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[0] is I2C_AV_Config:u10|mI2C_DATA[0] P1_mI2C_DATA[0] = DFFEAS(P1L93, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[11] is I2C_AV_Config:u10|mI2C_DATA[11] P1_mI2C_DATA[11] = DFFEAS(P1L94, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[10] is I2C_AV_Config:u10|mI2C_DATA[10] P1_mI2C_DATA[10] = DFFEAS(P1L95, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[4] is I2C_AV_Config:u10|mI2C_DATA[4] P1_mI2C_DATA[4] = DFFEAS(P1L96, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[6] is I2C_AV_Config:u10|mI2C_DATA[6] P1_mI2C_DATA[6] = DFFEAS(P1L97, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --P1_mI2C_DATA[12] is I2C_AV_Config:u10|mI2C_DATA[12] P1_mI2C_DATA[12] = DFFEAS(P1L3, P1_mI2C_CTRL_CLK, , , P1L84, , , , ); --U1L19 is USB_JTAG:u1|JTAG_REC:u0|rCont[2]~10 U1L19 = U1_rCont[2] $ (U1_rCont[1] & U1_rCont[0]); --U1L17 is USB_JTAG:u1|JTAG_REC:u0|rCont[1]~11 U1L17 = U1_rCont[1] $ U1_rCont[0]; --Z1L102 is Multi_Sdram:u3|Sdram_Controller:u1|ST[8]~1538 Z1L102 = !Z1_ST[0] & (Z1_Pre_RD # !Y1L51); --Z1L9 is Multi_Sdram:u3|Sdram_Controller:u1|CMD[1]~763 Z1L9 = !Z1_ST[1] & !Z1L99 & Z1L36; --Z1L103 is Multi_Sdram:u3|Sdram_Controller:u1|Select~129 Z1L103 = Y1L51 & !Z1_ST[0] & !Z1_Pre_RD; --AB1_rp_shift[1] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[1] AB1_rp_shift[1] = DFFEAS(AB1L111, S1__clk0, KEY[0], , AB1L107, , , , ); --AB1L110 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift~914 AB1L110 = !BB1_INIT_REQ & (AB1_rp_shift[1] # AB1_command_done & !AB1_command_delay[0]); --AB1_command_delay[1] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[1] AB1_command_delay[1] = DFFEAS(AB1L73, S1__clk0, KEY[0], , , , , , ); --AB1L72 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~332 AB1L72 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[1] # !AB1L116); --AB1L93 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_read~107 AB1L93 = AB1L64 # !AB1_ex_read & !AB1_ex_write # !Z1_PM_STOP; --AB1L94 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_read~108 AB1L94 = AB1L93 & (AB1_ex_read # BB1_READA & AB1L56); --AB1L54 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|always0~13 AB1L54 = BB1_WRITEA & AB1L55 & !BB1_REF_REQ; --AB1L96 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_write~107 AB1L96 = AB1L93 & (AB1L54 # AB1_ex_write); --BB1L65 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[0]~1071 BB1L65 = BB1_init_timer[0] $ VCC; --BB1L66 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[0]~1072 BB1L66 = CARRY(BB1_init_timer[0]); --BB1L68 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[1]~1073 BB1L68 = BB1_init_timer[1] & !BB1L66 # !BB1_init_timer[1] & (BB1L66 # GND); --BB1L69 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[1]~1074 BB1L69 = CARRY(!BB1L66 # !BB1_init_timer[1]); --BB1L71 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[2]~1075 BB1L71 = BB1_init_timer[2] & (BB1L69 $ GND) # !BB1_init_timer[2] & !BB1L69 & VCC; --BB1L72 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[2]~1076 BB1L72 = CARRY(BB1_init_timer[2] & !BB1L69); --BB1L74 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3]~1077 BB1L74 = BB1_init_timer[3] & !BB1L72 # !BB1_init_timer[3] & (BB1L72 # GND); --BB1L75 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3]~1078 BB1L75 = CARRY(!BB1L72 # !BB1_init_timer[3]); --BB1L77 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[4]~1079 BB1L77 = BB1_init_timer[4] & (BB1L75 $ GND) # !BB1_init_timer[4] & !BB1L75 & VCC; --BB1L78 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[4]~1080 BB1L78 = CARRY(BB1_init_timer[4] & !BB1L75); --BB1L80 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[5]~1081 BB1L80 = BB1_init_timer[5] & !BB1L78 # !BB1_init_timer[5] & (BB1L78 # GND); --BB1L81 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[5]~1082 BB1L81 = CARRY(!BB1L78 # !BB1_init_timer[5]); --BB1L83 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[6]~1083 BB1L83 = BB1_init_timer[6] & (BB1L81 $ GND) # !BB1_init_timer[6] & !BB1L81 & VCC; --BB1L84 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[6]~1084 BB1L84 = CARRY(BB1_init_timer[6] & !BB1L81); --BB1L86 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[7]~1085 BB1L86 = BB1_init_timer[7] & !BB1L84 # !BB1_init_timer[7] & (BB1L84 # GND); --BB1L87 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[7]~1086 BB1L87 = CARRY(!BB1L84 # !BB1_init_timer[7]); --BB1L89 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[8]~1087 BB1L89 = BB1_init_timer[8] & (BB1L87 $ GND) # !BB1_init_timer[8] & !BB1L87 & VCC; --BB1L90 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[8]~1088 BB1L90 = CARRY(BB1_init_timer[8] & !BB1L87); --BB1L92 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[9]~1089 BB1L92 = BB1_init_timer[9] & !BB1L90 # !BB1_init_timer[9] & (BB1L90 # GND); --BB1L93 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[9]~1090 BB1L93 = CARRY(!BB1L90 # !BB1_init_timer[9]); --BB1L20 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~424 BB1L20 = !BB1_init_timer[0] & !BB1_init_timer[1] & !BB1_init_timer[2]; --BB1L21 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~425 BB1L21 = BB1L13 & (BB1L20 # !BB1_init_timer[3]) # !BB1_init_timer[7]; --BB1L22 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~426 BB1L22 = BB1L21 & !BB1_init_timer[8] # !BB1L17 # !BB1_init_timer[9]; --BB1L23 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan~427 BB1L23 = !BB1_init_timer[15] & (BB1L22 & !BB1_init_timer[13] # !BB1_init_timer[14]); --BB1L95 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[10]~1091 BB1L95 = BB1_init_timer[10] & (BB1L93 $ GND) # !BB1_init_timer[10] & !BB1L93 & VCC; --BB1L96 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[10]~1092 BB1L96 = CARRY(BB1_init_timer[10] & !BB1L93); --BB1L98 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[11]~1093 BB1L98 = BB1_init_timer[11] & !BB1L96 # !BB1_init_timer[11] & (BB1L96 # GND); --BB1L99 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[11]~1094 BB1L99 = CARRY(!BB1L96 # !BB1_init_timer[11]); --BB1L101 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[12]~1095 BB1L101 = BB1_init_timer[12] & (BB1L99 $ GND) # !BB1_init_timer[12] & !BB1L99 & VCC; --BB1L102 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[12]~1096 BB1L102 = CARRY(BB1_init_timer[12] & !BB1L99); --BB1L104 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[13]~1097 BB1L104 = BB1_init_timer[13] & !BB1L102 # !BB1_init_timer[13] & (BB1L102 # GND); --BB1L105 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[13]~1098 BB1L105 = CARRY(!BB1L102 # !BB1_init_timer[13]); --BB1L107 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[14]~1099 BB1L107 = BB1_init_timer[14] & (BB1L105 $ GND) # !BB1_init_timer[14] & !BB1L105 & VCC; --BB1L108 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[14]~1100 BB1L108 = CARRY(BB1_init_timer[14] & !BB1L105); --BB1L110 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[15]~1101 BB1L110 = BB1_init_timer[15] $ BB1L108; --BB1L114 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[0]~251 BB1L114 = BB1_timer[0] $ VCC; --BB1L115 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[0]~252 BB1L115 = CARRY(BB1_timer[0]); --BB1L33 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REF_REQ~23 BB1L33 = BB1_INIT_REQ # AB1_REF_ACK; --BB1L117 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[1]~253 BB1L117 = BB1_timer[1] & BB1L115 & VCC # !BB1_timer[1] & !BB1L115; --BB1L118 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[1]~254 BB1L118 = CARRY(!BB1_timer[1] & !BB1L115); --BB1L120 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[2]~255 BB1L120 = BB1_timer[2] & (GND # !BB1L118) # !BB1_timer[2] & (BB1L118 $ GND); --BB1L121 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[2]~256 BB1L121 = CARRY(BB1_timer[2] # !BB1L118); --BB1L123 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[3]~257 BB1L123 = BB1_timer[3] & BB1L121 & VCC # !BB1_timer[3] & !BB1L121; --BB1L124 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[3]~258 BB1L124 = CARRY(!BB1_timer[3] & !BB1L121); --BB1L126 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[4]~259 BB1L126 = BB1_timer[4] & (GND # !BB1L124) # !BB1_timer[4] & (BB1L124 $ GND); --BB1L127 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[4]~260 BB1L127 = CARRY(BB1_timer[4] # !BB1L124); --BB1L129 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[5]~261 BB1L129 = BB1_timer[5] & BB1L127 & VCC # !BB1_timer[5] & !BB1L127; --BB1L130 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[5]~262 BB1L130 = CARRY(!BB1_timer[5] & !BB1L127); --BB1L132 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[6]~263 BB1L132 = BB1_timer[6] & (GND # !BB1L130) # !BB1_timer[6] & (BB1L130 $ GND); --BB1L133 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[6]~264 BB1L133 = CARRY(BB1_timer[6] # !BB1L130); --BB1L135 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[7]~265 BB1L135 = BB1_timer[7] & BB1L133 & VCC # !BB1_timer[7] & !BB1L133; --BB1L136 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[7]~266 BB1L136 = CARRY(!BB1_timer[7] & !BB1L133); --BB1L138 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[8]~267 BB1L138 = BB1_timer[8] & (GND # !BB1L136) # !BB1_timer[8] & (BB1L136 $ GND); --BB1L139 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[8]~268 BB1L139 = CARRY(BB1_timer[8] # !BB1L136); --BB1L141 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[9]~269 BB1L141 = BB1_timer[9] & BB1L139 & VCC # !BB1_timer[9] & !BB1L139; --BB1L142 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[9]~270 BB1L142 = CARRY(!BB1_timer[9] & !BB1L139); --BB1L144 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[10]~271 BB1L144 = BB1_timer[10] & (GND # !BB1L142) # !BB1_timer[10] & (BB1L142 $ GND); --BB1L145 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[10]~272 BB1L145 = CARRY(BB1_timer[10] # !BB1L142); --BB1L147 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[11]~273 BB1L147 = BB1_timer[11] & BB1L145 & VCC # !BB1_timer[11] & !BB1L145; --BB1L148 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[11]~274 BB1L148 = CARRY(!BB1_timer[11] & !BB1L145); --BB1L150 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[12]~275 BB1L150 = BB1_timer[12] & (GND # !BB1L148) # !BB1_timer[12] & (BB1L148 $ GND); --BB1L151 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[12]~276 BB1L151 = CARRY(BB1_timer[12] # !BB1L148); --BB1L153 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[13]~277 BB1L153 = BB1_timer[13] & BB1L151 & VCC # !BB1_timer[13] & !BB1L151; --BB1L154 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[13]~278 BB1L154 = CARRY(!BB1_timer[13] & !BB1L151); --BB1L156 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[14]~279 BB1L156 = BB1_timer[14] & (GND # !BB1L154) # !BB1_timer[14] & (BB1L154 $ GND); --BB1L157 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[14]~280 BB1L157 = CARRY(BB1_timer[14] # !BB1L154); --BB1L159 is Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[15]~281 BB1L159 = BB1_timer[15] $ !BB1L157; --AB1L18 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|REF_ACK~55 AB1L18 = AB1_do_refresh & (BB1_REF_REQ # AB1_REF_ACK & AB1L60) # !AB1_do_refresh & AB1_REF_ACK & AB1L60; --Z1L148 is Multi_Sdram:u3|Sdram_Controller:u1|mDONE~69 Z1L148 = Z1L31 & (Z1_mDONE # Z1L41 & !Z1_ST[0]); --Y1L9 is Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~145 Y1L9 = !Y1_ST.11 & (K1_oSDR_Select[1] # K1_oSDR_Select[0]); --J1_timer_5usec_count[0] is ps2_keyboard:u4|timer_5usec_count[0] J1_timer_5usec_count[0] = DFFEAS(J1L260, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1_timer_5usec_count[1] is ps2_keyboard:u4|timer_5usec_count[1] J1_timer_5usec_count[1] = DFFEAS(J1L263, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1L283 is ps2_keyboard:u4|timer_5usec_done~117 J1L283 = J1_timer_5usec_count[0] & !J1_timer_5usec_count[1]; --J1_timer_5usec_count[3] is ps2_keyboard:u4|timer_5usec_count[3] J1_timer_5usec_count[3] = DFFEAS(J1L269, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1_timer_5usec_count[4] is ps2_keyboard:u4|timer_5usec_count[4] J1_timer_5usec_count[4] = DFFEAS(J1L272, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1_timer_5usec_count[5] is ps2_keyboard:u4|timer_5usec_count[5] J1_timer_5usec_count[5] = DFFEAS(J1L275, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1_timer_5usec_count[7] is ps2_keyboard:u4|timer_5usec_count[7] J1_timer_5usec_count[7] = DFFEAS(J1L281, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1_timer_5usec_count[6] is ps2_keyboard:u4|timer_5usec_count[6] J1_timer_5usec_count[6] = DFFEAS(J1L278, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1L284 is ps2_keyboard:u4|timer_5usec_done~118 J1L284 = J1_timer_5usec_count[4] & J1_timer_5usec_count[5] & J1_timer_5usec_count[7] & !J1_timer_5usec_count[6]; --J1_timer_5usec_count[2] is ps2_keyboard:u4|timer_5usec_count[2] J1_timer_5usec_count[2] = DFFEAS(J1L266, CLOCK_50, , , , , , !J1_m1_state.m1_tx_wait_clk_h, ); --J1L285 is ps2_keyboard:u4|timer_5usec_done~119 J1L285 = J1L283 & J1_timer_5usec_count[3] & J1L284 & !J1_timer_5usec_count[2]; --J1_m1_state.m1_tx_wait_clk_h is ps2_keyboard:u4|m1_state.m1_tx_wait_clk_h J1_m1_state.m1_tx_wait_clk_h = DFFEAS(J1L97, CLOCK_50, , , , , , !KEY[0], ); --J1L109 is ps2_keyboard:u4|m1_state~204 J1L109 = KEY[0] & J1_ps2_clk_s & J1L285 & J1_m1_state.m1_tx_wait_clk_h; --J1L110 is ps2_keyboard:u4|m1_state~205 J1L110 = !J1_ps2_clk_s & !J1_m1_state.m1_rx_clk_h & KEY[0]; --J1_q[10] is ps2_keyboard:u4|q[10] J1_q[10] = DFFEAS(J1L140, CLOCK_50, , , J1L124, , , , ); --J1L139 is ps2_keyboard:u4|q~1263 J1L139 = KEY[0] & J1_q[10]; --J1_m1_state.m1_rx_rising_edge_marker is ps2_keyboard:u4|m1_state.m1_rx_rising_edge_marker J1_m1_state.m1_rx_rising_edge_marker = DFFEAS(J1L114, CLOCK_50, , , , , , , ); --J1_ps2_data_s is ps2_keyboard:u4|ps2_data_s J1_ps2_data_s = DFFEAS(PS2_DAT, CLOCK_50, , , , , , , ); --J1_m1_state.m1_tx_error_no_keyboard_ack is ps2_keyboard:u4|m1_state.m1_tx_error_no_keyboard_ack J1_m1_state.m1_tx_error_no_keyboard_ack = DFFEAS(J1L96, CLOCK_50, , , , , , !KEY[0], ); --J1_m1_state.m1_tx_done_recovery is ps2_keyboard:u4|m1_state.m1_tx_done_recovery J1_m1_state.m1_tx_done_recovery = DFFEAS(J1L95, CLOCK_50, , , , , , !KEY[0], ); --J1L111 is ps2_keyboard:u4|m1_state~206 J1L111 = J1_ps2_data_s & (J1_m1_state.m1_tx_error_no_keyboard_ack # J1_m1_state.m1_tx_done_recovery) # !J1_m1_state.m1_rx_clk_h; --J1L112 is ps2_keyboard:u4|m1_state~207 J1L112 = !J1_m1_state.m1_rx_rising_edge_marker & KEY[0] & (!J1L111 # !J1_ps2_clk_s); --J1L288 is ps2_keyboard:u4|timer_60usec_count[0]~158 J1L288 = J1L326 & J1_timer_60usec_count[0] & VCC # !J1L326 & (J1_timer_60usec_count[0] $ VCC); --J1L289 is ps2_keyboard:u4|timer_60usec_count[0]~159 J1L289 = CARRY(!J1L326 & J1_timer_60usec_count[0]); --J1_m1_state.m1_rx_clk_l is ps2_keyboard:u4|m1_state.m1_rx_clk_l J1_m1_state.m1_rx_clk_l = DFFEAS(J1L92, CLOCK_50, , , , , , !KEY[0], ); --J1L183 is ps2_keyboard:u4|reduce_or~0 J1L183 = !J1_m1_state.m1_rx_clk_l & J1_m1_state.m1_rx_clk_h; --J1L291 is ps2_keyboard:u4|timer_60usec_count[1]~160 J1L291 = J1_timer_60usec_count[1] & !J1L289 # !J1_timer_60usec_count[1] & (J1L289 # GND); --J1L292 is ps2_keyboard:u4|timer_60usec_count[1]~161 J1L292 = CARRY(!J1L289 # !J1_timer_60usec_count[1]); --J1L294 is ps2_keyboard:u4|timer_60usec_count[2]~162 J1L294 = J1_timer_60usec_count[2] & (J1L292 $ GND) # !J1_timer_60usec_count[2] & !J1L292 & VCC; --J1L295 is ps2_keyboard:u4|timer_60usec_count[2]~163 J1L295 = CARRY(J1_timer_60usec_count[2] & !J1L292); --J1L297 is ps2_keyboard:u4|timer_60usec_count[3]~164 J1L297 = J1_timer_60usec_count[3] & !J1L295 # !J1_timer_60usec_count[3] & (J1L295 # GND); --J1L298 is ps2_keyboard:u4|timer_60usec_count[3]~165 J1L298 = CARRY(!J1L295 # !J1_timer_60usec_count[3]); --J1L300 is ps2_keyboard:u4|timer_60usec_count[4]~166 J1L300 = J1_timer_60usec_count[4] & (J1L298 $ GND) # !J1_timer_60usec_count[4] & !J1L298 & VCC; --J1L301 is ps2_keyboard:u4|timer_60usec_count[4]~167 J1L301 = CARRY(J1_timer_60usec_count[4] & !J1L298); --J1L303 is ps2_keyboard:u4|timer_60usec_count[5]~168 J1L303 = J1_timer_60usec_count[5] & !J1L301 # !J1_timer_60usec_count[5] & (J1L301 # GND); --J1L304 is ps2_keyboard:u4|timer_60usec_count[5]~169 J1L304 = CARRY(!J1L301 # !J1_timer_60usec_count[5]); --J1L306 is ps2_keyboard:u4|timer_60usec_count[6]~170 J1L306 = J1_timer_60usec_count[6] & (J1L304 $ GND) # !J1_timer_60usec_count[6] & !J1L304 & VCC; --J1L307 is ps2_keyboard:u4|timer_60usec_count[6]~171 J1L307 = CARRY(J1_timer_60usec_count[6] & !J1L304); --J1L309 is ps2_keyboard:u4|timer_60usec_count[7]~172 J1L309 = J1_timer_60usec_count[7] & !J1L307 # !J1_timer_60usec_count[7] & (J1L307 # GND); --J1L310 is ps2_keyboard:u4|timer_60usec_count[7]~173 J1L310 = CARRY(!J1L307 # !J1_timer_60usec_count[7]); --J1L312 is ps2_keyboard:u4|timer_60usec_count[8]~174 J1L312 = J1_timer_60usec_count[8] & (J1L310 $ GND) # !J1_timer_60usec_count[8] & !J1L310 & VCC; --J1L313 is ps2_keyboard:u4|timer_60usec_count[8]~175 J1L313 = CARRY(J1_timer_60usec_count[8] & !J1L310); --J1L315 is ps2_keyboard:u4|timer_60usec_count[9]~176 J1L315 = J1_timer_60usec_count[9] & !J1L313 # !J1_timer_60usec_count[9] & (J1L313 # GND); --J1L316 is ps2_keyboard:u4|timer_60usec_count[9]~177 J1L316 = CARRY(!J1L313 # !J1_timer_60usec_count[9]); --J1L318 is ps2_keyboard:u4|timer_60usec_count[10]~178 J1L318 = J1_timer_60usec_count[10] & (J1L316 $ GND) # !J1_timer_60usec_count[10] & !J1L316 & VCC; --J1L319 is ps2_keyboard:u4|timer_60usec_count[10]~179 J1L319 = CARRY(J1_timer_60usec_count[10] & !J1L316); --J1L321 is ps2_keyboard:u4|timer_60usec_count[11]~180 J1L321 = J1_timer_60usec_count[11] $ J1L319; --J1_m1_state.m1_tx_clk_h is ps2_keyboard:u4|m1_state.m1_tx_clk_h J1_m1_state.m1_tx_clk_h = DFFEAS(J1L93, CLOCK_50, , , , , , !KEY[0], ); --J1L327 is ps2_keyboard:u4|tx_shifting_done~88 J1L327 = J1_bit_count[1] & J1_bit_count[3] & !J1_bit_count[0] & !J1_bit_count[2]; --J1L113 is ps2_keyboard:u4|m1_state~208 J1L113 = J1_ps2_clk_s & (J1_m1_state.m1_tx_wait_keyboard_ack # J1_m1_state.m1_tx_clk_h & J1L327) # !J1_ps2_clk_s & J1_m1_state.m1_tx_clk_h & J1L327; --P1_LUT_INDEX[0] is I2C_AV_Config:u10|LUT_INDEX[0] P1_LUT_INDEX[0] = DFFEAS(P1L6, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1_LUT_INDEX[1] is I2C_AV_Config:u10|LUT_INDEX[1] P1_LUT_INDEX[1] = DFFEAS(P1L8, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1_LUT_INDEX[2] is I2C_AV_Config:u10|LUT_INDEX[2] P1_LUT_INDEX[2] = DFFEAS(P1L11, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1_LUT_INDEX[3] is I2C_AV_Config:u10|LUT_INDEX[3] P1_LUT_INDEX[3] = DFFEAS(P1L13, P1_mI2C_CTRL_CLK, KEY[0], , , , , , ); --P1L91 is I2C_AV_Config:u10|reduce_or~73 P1L91 = !P1_LUT_INDEX[0] & (P1_LUT_INDEX[2] & (!P1_LUT_INDEX[3]) # !P1_LUT_INDEX[2] & (P1_LUT_INDEX[1] # P1_LUT_INDEX[3])); --P1L84 is I2C_AV_Config:u10|mI2C_DATA[12]~887 P1L84 = KEY[0] & !P1_mSetup_ST.00; --P1L1 is I2C_AV_Config:u10|Decoder~138 P1L1 = P1_LUT_INDEX[1] & P1_LUT_INDEX[2] & !P1_LUT_INDEX[0] & !P1_LUT_INDEX[3]; --P1L92 is I2C_AV_Config:u10|reduce_or~74 P1L92 = P1_LUT_INDEX[2] & !P1_LUT_INDEX[0] & (!P1_LUT_INDEX[3]) # !P1_LUT_INDEX[2] & (P1_LUT_INDEX[1] & (!P1_LUT_INDEX[3]) # !P1_LUT_INDEX[1] & P1_LUT_INDEX[0]); --P1L2 is I2C_AV_Config:u10|Decoder~139 P1L2 = P1_LUT_INDEX[0] & P1_LUT_INDEX[2] & !P1_LUT_INDEX[1] & !P1_LUT_INDEX[3]; --P1L93 is I2C_AV_Config:u10|reduce_or~75 P1L93 = P1_LUT_INDEX[1] & !P1_LUT_INDEX[2] & (P1_LUT_INDEX[0] $ P1_LUT_INDEX[3]) # !P1_LUT_INDEX[1] & !P1_LUT_INDEX[0] & (P1_LUT_INDEX[2] $ P1_LUT_INDEX[3]); --P1L94 is I2C_AV_Config:u10|reduce_or~76 P1L94 = P1_LUT_INDEX[2] & !P1_LUT_INDEX[3] & (P1_LUT_INDEX[0] # P1_LUT_INDEX[1]) # !P1_LUT_INDEX[2] & !P1_LUT_INDEX[0] & !P1_LUT_INDEX[1] & P1_LUT_INDEX[3]; --P1L95 is I2C_AV_Config:u10|reduce_or~77 P1L95 = P1_LUT_INDEX[0] & P1_LUT_INDEX[1] & (!P1_LUT_INDEX[3]) # !P1_LUT_INDEX[0] & !P1_LUT_INDEX[1] & (P1_LUT_INDEX[2] $ P1_LUT_INDEX[3]); --P1L96 is I2C_AV_Config:u10|reduce_or~78 P1L96 = !P1_LUT_INDEX[3] & (P1_LUT_INDEX[1] & (!P1_LUT_INDEX[2]) # !P1_LUT_INDEX[1] & (P1_LUT_INDEX[0] # P1_LUT_INDEX[2])); --P1L97 is I2C_AV_Config:u10|reduce_or~79 P1L97 = !P1_LUT_INDEX[3] & (P1_LUT_INDEX[1] & P1_LUT_INDEX[0] & !P1_LUT_INDEX[2] # !P1_LUT_INDEX[1] & (P1_LUT_INDEX[2])); --P1L3 is I2C_AV_Config:u10|LUT_DATA~8 P1L3 = !P1_LUT_INDEX[2] & P1_LUT_INDEX[3] & (P1_LUT_INDEX[0] $ P1_LUT_INDEX[1]); --AB1_rp_shift[2] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[2] AB1_rp_shift[2] = DFFEAS(AB1L112, S1__clk0, KEY[0], , AB1L107, , , , ); --AB1L111 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift~915 AB1L111 = !BB1_INIT_REQ & (AB1_rp_shift[2] # AB1_command_done & !AB1_command_delay[0]); --AB1_command_delay[2] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[2] AB1_command_delay[2] = DFFEAS(AB1L74, S1__clk0, KEY[0], , , , , , ); --AB1L73 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~333 AB1L73 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[2] # !AB1L116); --J1L260 is ps2_keyboard:u4|timer_5usec_count[0]~106 J1L260 = J1L285 & J1_timer_5usec_count[0] & VCC # !J1L285 & (J1_timer_5usec_count[0] $ VCC); --J1L261 is ps2_keyboard:u4|timer_5usec_count[0]~107 J1L261 = CARRY(!J1L285 & J1_timer_5usec_count[0]); --J1L263 is ps2_keyboard:u4|timer_5usec_count[1]~108 J1L263 = J1_timer_5usec_count[1] & !J1L261 # !J1_timer_5usec_count[1] & (J1L261 # GND); --J1L264 is ps2_keyboard:u4|timer_5usec_count[1]~109 J1L264 = CARRY(!J1L261 # !J1_timer_5usec_count[1]); --J1L266 is ps2_keyboard:u4|timer_5usec_count[2]~110 J1L266 = J1_timer_5usec_count[2] & (J1L264 $ GND) # !J1_timer_5usec_count[2] & !J1L264 & VCC; --J1L267 is ps2_keyboard:u4|timer_5usec_count[2]~111 J1L267 = CARRY(J1_timer_5usec_count[2] & !J1L264); --J1L269 is ps2_keyboard:u4|timer_5usec_count[3]~112 J1L269 = J1_timer_5usec_count[3] & !J1L267 # !J1_timer_5usec_count[3] & (J1L267 # GND); --J1L270 is ps2_keyboard:u4|timer_5usec_count[3]~113 J1L270 = CARRY(!J1L267 # !J1_timer_5usec_count[3]); --J1L272 is ps2_keyboard:u4|timer_5usec_count[4]~114 J1L272 = J1_timer_5usec_count[4] & (J1L270 $ GND) # !J1_timer_5usec_count[4] & !J1L270 & VCC; --J1L273 is ps2_keyboard:u4|timer_5usec_count[4]~115 J1L273 = CARRY(J1_timer_5usec_count[4] & !J1L270); --J1L275 is ps2_keyboard:u4|timer_5usec_count[5]~116 J1L275 = J1_timer_5usec_count[5] & !J1L273 # !J1_timer_5usec_count[5] & (J1L273 # GND); --J1L276 is ps2_keyboard:u4|timer_5usec_count[5]~117 J1L276 = CARRY(!J1L273 # !J1_timer_5usec_count[5]); --J1L278 is ps2_keyboard:u4|timer_5usec_count[6]~118 J1L278 = J1_timer_5usec_count[6] & (J1L276 $ GND) # !J1_timer_5usec_count[6] & !J1L276 & VCC; --J1L279 is ps2_keyboard:u4|timer_5usec_count[6]~119 J1L279 = CARRY(J1_timer_5usec_count[6] & !J1L276); --J1L281 is ps2_keyboard:u4|timer_5usec_count[7]~120 J1L281 = J1_timer_5usec_count[7] $ J1L279; --J1_m1_state.m1_tx_clk_l is ps2_keyboard:u4|m1_state.m1_tx_clk_l J1_m1_state.m1_tx_clk_l = DFFEAS(J1L94, CLOCK_50, , , , , , !KEY[0], ); --J1L97 is ps2_keyboard:u4|m1_next_state.m1_tx_wait_clk_h~119 J1L97 = J1_ps2_clk_s & (J1_m1_state.m1_tx_clk_l # J1_m1_state.m1_tx_wait_clk_h & !J1L285) # !J1_ps2_clk_s & (J1_m1_state.m1_tx_wait_clk_h); --J1L140 is ps2_keyboard:u4|q~1264 J1L140 = KEY[0] & J1_ps2_data_s; --J1L114 is ps2_keyboard:u4|m1_state~209 J1L114 = KEY[0] & J1_ps2_clk_s & J1_m1_state.m1_rx_clk_l; --J1L96 is ps2_keyboard:u4|m1_next_state.m1_tx_error_no_keyboard_ack~52 J1L96 = J1_ps2_data_s & !J1_ps2_clk_s & (J1_m1_state.m1_tx_error_no_keyboard_ack # J1_m1_state.m1_tx_wait_keyboard_ack) # !J1_ps2_data_s & J1_m1_state.m1_tx_error_no_keyboard_ack; --J1L95 is ps2_keyboard:u4|m1_next_state.m1_tx_done_recovery~62 J1L95 = J1_m1_state.m1_tx_done_recovery & (!J1_ps2_data_s # !J1_ps2_clk_s) # !J1_m1_state.m1_tx_done_recovery & J1_m1_state.m1_tx_wait_keyboard_ack & !J1_ps2_clk_s & !J1_ps2_data_s; --J1L92 is ps2_keyboard:u4|m1_next_state.m1_rx_clk_l~8 J1L92 = J1_m1_state.m1_rx_falling_edge_marker # J1_m1_state.m1_rx_clk_l & !J1_ps2_clk_s; --J1L93 is ps2_keyboard:u4|m1_next_state.m1_tx_clk_h~47 J1L93 = J1_m1_state.m1_tx_rising_edge_marker # J1_ps2_clk_s & J1_m1_state.m1_tx_clk_h & !J1L327; --P1L6 is I2C_AV_Config:u10|LUT_INDEX[0]~696 P1L6 = P1_mSetup_ST.10 $ P1_LUT_INDEX[0]; --P1L8 is I2C_AV_Config:u10|LUT_INDEX[1]~697 P1L8 = P1_LUT_INDEX[1] $ (P1_mSetup_ST.10 & P1_LUT_INDEX[0]); --P1L11 is I2C_AV_Config:u10|LUT_INDEX[2]~698 P1L11 = P1_LUT_INDEX[2] $ (P1_mSetup_ST.10 & P1_LUT_INDEX[0] & P1_LUT_INDEX[1]); --P1L9 is I2C_AV_Config:u10|LUT_INDEX[1]~699 P1L9 = P1_mSetup_ST.10 & P1_LUT_INDEX[0]; --P1L13 is I2C_AV_Config:u10|LUT_INDEX[3]~700 P1L13 = P1_LUT_INDEX[3] $ (P1_LUT_INDEX[1] & P1_LUT_INDEX[2] & P1L9); --AB1_rp_shift[3] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[3] AB1_rp_shift[3] = DFFEAS(AB1L113, S1__clk0, KEY[0], , , , , BB1_INIT_REQ, ); --AB1L112 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift~916 AB1L112 = !BB1_INIT_REQ & (AB1_rp_shift[3] # AB1_command_done & !AB1_command_delay[0]); --AB1_command_delay[3] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[3] AB1_command_delay[3] = DFFEAS(AB1L75, S1__clk0, KEY[0], , , , , , ); --AB1L74 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~334 AB1L74 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[3] # !AB1L116); --J1L94 is ps2_keyboard:u4|m1_next_state.m1_tx_clk_l~94 J1L94 = !J1_ps2_clk_s & (J1_m1_state.m1_tx_clk_l # J1_m1_state.m1_tx_clk_h & !J1L327); --AB1L113 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift~917 AB1L113 = AB1L64 # AB1L106 & AB1_rp_shift[3] & !Z1_PM_STOP; --AB1_command_delay[4] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[4] AB1_command_delay[4] = DFFEAS(AB1L76, S1__clk0, KEY[0], , , , , , ); --AB1L75 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~335 AB1L75 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[4] # !AB1L116); --AB1_command_delay[5] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[5] AB1_command_delay[5] = DFFEAS(AB1L77, S1__clk0, KEY[0], , , , , , ); --AB1L76 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~336 AB1L76 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[5] # !AB1L116); --AB1_command_delay[6] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[6] AB1_command_delay[6] = DFFEAS(AB1L78, S1__clk0, KEY[0], , , , , , ); --AB1L77 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~337 AB1L77 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[6] # !AB1L116); --AB1_command_delay[7] is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[7] AB1_command_delay[7] = DFFEAS(AB1L79, S1__clk0, KEY[0], , , , , , ); --AB1L78 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~338 AB1L78 = !BB1_INIT_REQ & (AB1_do_reada # AB1_command_delay[7] # !AB1L116); --AB1L79 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay~339 AB1L79 = !BB1_INIT_REQ & (AB1_do_reada # !AB1L116); --X1L85 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[0]~1116 X1L85 = X1_r_ADDR[0] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --X1L87 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[2]~1117 X1L87 = X1_r_ADDR[2] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --X1L89 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[4]~1118 X1L89 = X1_r_ADDR[4] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --X1L91 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[6]~1119 X1L91 = X1_r_ADDR[6] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --X1L93 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[8]~1120 X1L93 = X1_r_ADDR[8] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --X1L95 is Multi_Flash:u2|Flash_Controller:u1|FL_ADDR[10]~1121 X1L95 = X1_r_ADDR[10] & (X1_ST.P4_PRG # X1_ST.READ) # !X1L137; --M1L122 is VGA_Controller:u8|LessThan~1423 M1L122 = !M1_H_Cont[8] & !M1_H_Cont[9] & (M1L111 # !M1_H_Cont[7]); --X1L149 is Multi_Flash:u2|Flash_Controller:u1|ST~422 X1L149 = X1_ST.P2 # X1_ST.P5 # X1_mStart # !X1L138; --M1L123 is VGA_Controller:u8|LessThan~1424 M1L123 = !M1_H_Cont[5] & !M1_H_Cont[6] & (M1L36 # !M1_H_Cont[4]); --K1L181 is CMD_Decode:u5|f_SEG7~24 K1L181 = K1_CMD_Tmp[46] & !K1_CMD_Tmp[42] & K1L180 & !K1_f_SEG7; --K1L166 is CMD_Decode:u5|f_LED~33 K1L166 = K1_CMD_Tmp[46] & !K1_CMD_Tmp[42] & K1L165 & !K1_f_LED; --Z1L129 is Multi_Sdram:u3|Sdram_Controller:u1|add~755 Z1L129 = Z1L128 & (Z1_ST[1] # !Z1L99 # !Z1L36); --AB1L48 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~789 AB1L48 = !AB1L43 & BB1_SADDR[16] & (AB1_do_writea # AB1_do_reada); --AB1L49 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~790 AB1L49 = !AB1L43 & BB1_SADDR[17] & (AB1_do_writea # AB1_do_reada); --AB1L50 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA~791 AB1L50 = !AB1L43 & BB1_SADDR[19] & (AB1_do_writea # AB1_do_reada); --Z1L109 is Multi_Sdram:u3|Sdram_Controller:u1|Write~353 Z1L109 = !Z1_ST[1] & !Z1_ST[0] & Z1L36 & Z1L98; --Z1L53 is Multi_Sdram:u3|Sdram_Controller:u1|Read~350 Z1L53 = !Z1_ST[1] & !Z1_ST[0] & Z1L36 & Z1L42; --K1L190 is CMD_Decode:u5|f_SR_SEL~23 K1L190 = K1_CMD_Tmp[46] & !K1_CMD_Tmp[42] & K1L177 & !K1_f_SR_SEL; --W1L10 is Multi_Flash:u2|Flash_Multiplexer:u0|ST~168 W1L10 = W1L6 & (K1_oFL_Select[0] # K1_oFL_Select[1]); --J1L51 is ps2_keyboard:u4|Equal~8702 J1L51 = J1_q[3] & !J1_q[1] & J1L4 & !J1_q[4]; --J1L52 is ps2_keyboard:u4|Equal~8703 J1L52 = J1L73 & !J1_q[3] & (J1_left_shift_key # J1_right_shift_key); --J1L53 is ps2_keyboard:u4|Equal~8704 J1L53 = !J1_left_shift_key & !J1_right_shift_key & J1_q[4] & J1L5; --J1L179 is ps2_keyboard:u4|reduce_nor~877 J1L179 = J1_q[8] # J1_q[7] # !J1L144 # !J1L5; --J1L242 is ps2_keyboard:u4|reduce_or~1291 J1L242 = J1_q[8] # !J1L13 # !J1_q[6] # !J1_q[7]; --J1L54 is ps2_keyboard:u4|Equal~8705 J1L54 = J1L19 & J1L14 & (J1_left_shift_key # J1_right_shift_key); --J1L55 is ps2_keyboard:u4|Equal~8706 J1L55 = J1L8 & J1L21 & (J1_left_shift_key # J1_right_shift_key); --J1L56 is ps2_keyboard:u4|Equal~8707 J1L56 = J1L31 & !J1_q[3] & (J1_left_shift_key # J1_right_shift_key); --J1L57 is ps2_keyboard:u4|Equal~8708 J1L57 = J1L24 & J1L16 & (J1_left_shift_key # J1_right_shift_key); --J1L58 is ps2_keyboard:u4|Equal~8709 J1L58 = J1L5 & !J1_q[4] & (J1_left_shift_key # J1_right_shift_key); --J1L59 is ps2_keyboard:u4|Equal~8710 J1L59 = !J1_left_shift_key & !J1_right_shift_key & J1L5 & !J1_q[4]; --J1L60 is ps2_keyboard:u4|Equal~8711 J1L60 = !J1_left_shift_key & !J1_right_shift_key & J1L24 & J1L16; --J1L180 is ps2_keyboard:u4|reduce_nor~878 J1L180 = J1_q[7] & !J1_q[8] & J1_q[6] & J1L13; --J1L181 is ps2_keyboard:u4|reduce_nor~879 J1L181 = !J1L28 & (J1_q[4] # !J1L5 # !J1L8); --J1L61 is ps2_keyboard:u4|Equal~8712 J1L61 = !J1_left_shift_key & !J1_right_shift_key & J1L2; --J1L62 is ps2_keyboard:u4|Equal~8713 J1L62 = !J1_left_shift_key & !J1_right_shift_key & J1L19; --J1L63 is ps2_keyboard:u4|Equal~8714 J1L63 = !J1_left_shift_key & !J1_right_shift_key & J1L31 & !J1_q[3]; --J1L64 is ps2_keyboard:u4|Equal~8715 J1L64 = J1L2 & J1L38 & (J1_left_shift_key # J1_right_shift_key); --J1L65 is ps2_keyboard:u4|Equal~8716 J1L65 = J1_q[4] & J1L5 & (J1_left_shift_key # J1_right_shift_key); --J1L66 is ps2_keyboard:u4|Equal~8717 J1L66 = !J1_left_shift_key & !J1_right_shift_key & J1_q[3] & J1L31; --J1L67 is ps2_keyboard:u4|Equal~8718 J1L67 = !J1_left_shift_key & !J1_right_shift_key & J1L21 & J1L10; --J1L68 is ps2_keyboard:u4|Equal~8719 J1L68 = J1_q[3] & J1L31 & (J1_left_shift_key # J1_right_shift_key); --J1L69 is ps2_keyboard:u4|Equal~8720 J1L69 = !J1_left_shift_key & !J1_right_shift_key & J1L22; --J1L70 is ps2_keyboard:u4|Equal~8721 J1L70 = !J1_left_shift_key & !J1_right_shift_key & J1L8; --J1L71 is ps2_keyboard:u4|Equal~8722 J1L71 = J1L21 & J1L10 & (J1_left_shift_key # J1_right_shift_key); --J1L182 is ps2_keyboard:u4|reduce_nor~880 J1L182 = J1_left_shift_key & (J1L18) # !J1_left_shift_key & (J1_right_shift_key & (J1L18) # !J1_right_shift_key & J1L21); --J1L72 is ps2_keyboard:u4|Equal~8723 J1L72 = !J1_left_shift_key & !J1_right_shift_key & J1L43; --JB3_w_anode3056w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3056w[3] JB3_w_anode3056w[3] = N1L130 & !N1L132 & JB3L23 & !N1L128; --JB3_w_anode3066w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3066w[3] JB3_w_anode3066w[3] = N1L130 & !N1L132 & JB3L93 & !N1L128; --JB3_w_anode3045w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3045w[3] JB3_w_anode3045w[3] = N1L130 & !N1L132 & JB3L88 & !N1L128; --JB3_w_anode3159w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3159w[3] JB3_w_anode3159w[3] = N1L130 & !N1L132 & N1L128 & JB3L93; --JB3_w_anode3149w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3149w[3] JB3_w_anode3149w[3] = N1L130 & !N1L132 & N1L128 & JB3L23; --JB3_w_anode3138w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3138w[3] JB3_w_anode3138w[3] = N1L130 & !N1L132 & N1L128 & JB3L88; --JB3_w_anode3242w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3242w[3] JB3_w_anode3242w[3] = !N1L128 & !N1L130 & N1L132 & JB3L23; --JB3_w_anode3252w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3252w[3] JB3_w_anode3252w[3] = !N1L128 & !N1L130 & N1L132 & JB3L93; --JB3_w_anode3231w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3231w[3] JB3_w_anode3231w[3] = !N1L128 & !N1L130 & N1L132 & JB3L88; --JB3L6 is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2879w[3]~12 JB3L6 = !N1L128 & !N1L130 & JB3L93 & !N1L132; --JB3_w_anode2852w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2852w[3] JB3_w_anode2852w[3] = !N1L128 & !N1L130 & !N1L132 & JB3L88; --JB3_w_anode3335w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3335w[3] JB3_w_anode3335w[3] = N1L128 & !N1L130 & N1L132 & JB3L23; --JB3_w_anode3324w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3] JB3_w_anode3324w[3] = N1L128 & !N1L130 & N1L132 & JB3L88; --JB3_w_anode3345w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3] JB3_w_anode3345w[3] = N1L128 & !N1L130 & N1L132 & JB3L93; --JB3_w_anode2973w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2973w[3] JB3_w_anode2973w[3] = N1L128 & !N1L130 & JB3L93 & !N1L132; --JB3_w_anode2952w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2952w[3] JB3_w_anode2952w[3] = N1L128 & !N1L130 & JB3L88 & !N1L132; --JB3_w_anode2963w[3] is VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3] JB3_w_anode2963w[3] = N1L128 & !N1L130 & JB3L23 & !N1L132; --K1L196 is CMD_Decode:u5|f_VGA~57 K1L196 = K1_CMD_Tmp[42] & !K1_CMD_Tmp[46] & K1L195 & !K1_f_VGA; --Z1L31 is Multi_Sdram:u3|Sdram_Controller:u1|DONE~99 Z1L31 = K1_oSDR_Select[1] & (Y1_mSDR_RD) # !K1_oSDR_Select[1] & (K1_oSDR_Select[0] & Y1_mSDR_RD # !K1_oSDR_Select[0] & (K1_mSDR_Start)); --K1L178 is CMD_Decode:u5|f_SDR_SEL~56 K1L178 = K1_CMD_Tmp[42] & !K1_CMD_Tmp[46] & K1L177 & !K1_f_SDR_SEL; --MB1L11 is I2C_AV_Config:u10|I2C_Controller:u0|ACK3~216 MB1L11 = MB1L10 & A1L223 & !MB1L52Q # !MB1L10 & (MB1_ACK3); --MB1L36 is I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~11 MB1L36 = MB1L55Q & !MB1L40Q & KEY[0] & MB1L37; --MB1L5 is I2C_AV_Config:u10|I2C_Controller:u0|ACK2~237 MB1L5 = !MB1L46Q & !MB1L40Q & MB1L55Q & !MB1L52Q; --J1L73 is ps2_keyboard:u4|Equal~8724 J1L73 = J1L1 & J1_q[2] & !J1_q[7] & !J1_q[8]; --J1L1 is ps2_keyboard:u4|Equal~8641 J1L1 = !J1_q[4] & !J1_q[5] & J1_q[6] & !J1_q[1]; --MB1L7 is I2C_AV_Config:u10|I2C_Controller:u0|ACK2~252 MB1L7 = MB1_ACK2 & (MB1L6 # A1L223 & MB1L5) # !MB1_ACK2 & A1L223 & MB1L5; --MB1L8 is I2C_AV_Config:u10|I2C_Controller:u0|ACK2~253 MB1L8 = MB1L49Q & (MB1L43Q & (MB1L7) # !MB1L43Q & MB1_ACK2) # !MB1L49Q & MB1_ACK2; --J1L243 is ps2_keyboard:u4|reduce_or~1292 J1L243 = !J1L15 & (J1L256 # J1_q[4] # !J1L5); --J1L244 is ps2_keyboard:u4|reduce_or~1293 J1L244 = !J1L66 & J1L215 & (J1L243 # !J1L10); --Q1L320 is AUDIO_DAC:u11|rom~2380 Q1L320 = Q1L242Q & (Q1L241Q & !Q1L243Q # !Q1L241Q & (Q1L240Q)) # !Q1L242Q & Q1L243Q & (Q1L241Q $ Q1L240Q); --Q1L321 is AUDIO_DAC:u11|rom~2381 Q1L321 = Q1L241Q & (Q1L320 # Q1L243Q $ !Q1L239Q) # !Q1L241Q & (Q1L239Q & (!Q1L243Q) # !Q1L239Q & Q1L320); --Q1L322 is AUDIO_DAC:u11|rom~2382 Q1L322 = Q1L299 & (!Q1L298) # !Q1L299 & (Q1L239Q & (Q1L298 $ !Q1L241Q) # !Q1L239Q & (Q1L298 # Q1L241Q)); --Q1L323 is AUDIO_DAC:u11|rom~2383 Q1L323 = Q1L322 & (Q1L239Q # Q1L299 $ !Q1L240Q); --Q1L324 is AUDIO_DAC:u11|rom~2384 Q1L324 = Q1L243Q & (Q1L240Q & (!Q1L241Q) # !Q1L240Q & !Q1L242Q) # !Q1L243Q & (Q1L241Q $ (Q1L242Q & Q1L240Q)); --Q1L325 is AUDIO_DAC:u11|rom~2385 Q1L325 = Q1L243Q & (Q1L239Q & !Q1L242Q # !Q1L239Q & (Q1L324)) # !Q1L243Q & (Q1L324 # Q1L242Q $ Q1L239Q); --Q1L326 is AUDIO_DAC:u11|rom~2386 Q1L326 = Q1L242Q & (Q1L240Q & !Q1L239Q) # !Q1L242Q & (Q1L241Q & !Q1L240Q # !Q1L241Q & (Q1L239Q)); --Q1L327 is AUDIO_DAC:u11|rom~2387 Q1L327 = Q1L241Q & (Q1L326 # Q1L240Q $ !Q1L243Q) # !Q1L241Q & (Q1L326 & (Q1L240Q # !Q1L243Q) # !Q1L326 & Q1L240Q & !Q1L243Q); --Q1L229 is AUDIO_DAC:u11|SEL_Cont[0]~51 Q1L229 = !Q1_SEL_Cont[0]; --AB1L12 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CS_N[0]~6 AB1L12 = !KEY[0]; --N1L7 is VGA_OSD_RAM:u9|ADDR_dd[0]~6 N1L7 = !N1_ADDR_d[0]; --N1L9 is VGA_OSD_RAM:u9|ADDR_dd[1]~7 N1L9 = !N1_ADDR_d[1]; --N1L11 is VGA_OSD_RAM:u9|ADDR_dd[2]~8 N1L11 = !N1_ADDR_d[2]; --U1L15 is USB_JTAG:u1|JTAG_REC:u0|rCont[0]~12 U1L15 = !U1_rCont[0]; --~GND is ~GND ~GND = GND; --CLOCK_24[0] is CLOCK_24[0] --operation mode is input CLOCK_24[0] = INPUT(); --CLOCK_24[1] is CLOCK_24[1] --operation mode is input CLOCK_24[1] = INPUT(); --CLOCK_27[1] is CLOCK_27[1] --operation mode is input CLOCK_27[1] = INPUT(); --EXT_CLOCK is EXT_CLOCK --operation mode is input EXT_CLOCK = INPUT(); --KEY[1] is KEY[1] --operation mode is input KEY[1] = INPUT(); --KEY[2] is KEY[2] --operation mode is input KEY[2] = INPUT(); --KEY[3] is KEY[3] --operation mode is input KEY[3] = INPUT(); --SW[2] is SW[2] --operation mode is input SW[2] = INPUT(); --SW[3] is SW[3] --operation mode is input SW[3] = INPUT(); --SW[4] is SW[4] --operation mode is input SW[4] = INPUT(); --SW[5] is SW[5] --operation mode is input SW[5] = INPUT(); --SW[6] is SW[6] --operation mode is input SW[6] = INPUT(); --SW[7] is SW[7] --operation mode is input SW[7] = INPUT(); --SW[8] is SW[8] --operation mode is input SW[8] = INPUT(); --SW[9] is SW[9] --operation mode is input SW[9] = INPUT(); --UART_RXD is UART_RXD --operation mode is input UART_RXD = INPUT(); --AUD_ADCDAT is AUD_ADCDAT --operation mode is input AUD_ADCDAT = INPUT(); --SW[0] is SW[0] --operation mode is input SW[0] = INPUT(); --SW[1] is SW[1] --operation mode is input SW[1] = INPUT(); --CLOCK_50 is CLOCK_50 --operation mode is input CLOCK_50 = INPUT(); --KEY[0] is KEY[0] --operation mode is input KEY[0] = INPUT(); --TCS is TCS --operation mode is input TCS = INPUT(); --CLOCK_27[0] is CLOCK_27[0] --operation mode is input CLOCK_27[0] = INPUT(); --TCK is TCK --operation mode is input TCK = INPUT(); --TDI is TDI --operation mode is input TDI = INPUT(); --PS2_CLK is PS2_CLK --operation mode is input PS2_CLK = INPUT(); --PS2_DAT is PS2_DAT --operation mode is input PS2_DAT = INPUT(); --HEX0[0] is HEX0[0] --operation mode is output HEX0[0] = OUTPUT(T1L1); --HEX0[1] is HEX0[1] --operation mode is output HEX0[1] = OUTPUT(T1L2); --HEX0[2] is HEX0[2] --operation mode is output HEX0[2] = OUTPUT(T1L3); --HEX0[3] is HEX0[3] --operation mode is output HEX0[3] = OUTPUT(T1L4); --HEX0[4] is HEX0[4] --operation mode is output HEX0[4] = OUTPUT(T1L5); --HEX0[5] is HEX0[5] --operation mode is output HEX0[5] = OUTPUT(T1L6); --HEX0[6] is HEX0[6] --operation mode is output HEX0[6] = OUTPUT(!T1L7); --HEX1[0] is HEX1[0] --operation mode is output HEX1[0] = OUTPUT(T2L1); --HEX1[1] is HEX1[1] --operation mode is output HEX1[1] = OUTPUT(T2L2); --HEX1[2] is HEX1[2] --operation mode is output HEX1[2] = OUTPUT(T2L3); --HEX1[3] is HEX1[3] --operation mode is output HEX1[3] = OUTPUT(T2L4); --HEX1[4] is HEX1[4] --operation mode is output HEX1[4] = OUTPUT(T2L5); --HEX1[5] is HEX1[5] --operation mode is output HEX1[5] = OUTPUT(T2L6); --HEX1[6] is HEX1[6] --operation mode is output HEX1[6] = OUTPUT(!T2L7); --HEX2[0] is HEX2[0] --operation mode is output HEX2[0] = OUTPUT(T3L1); --HEX2[1] is HEX2[1] --operation mode is output HEX2[1] = OUTPUT(T3L2); --HEX2[2] is HEX2[2] --operation mode is output HEX2[2] = OUTPUT(T3L3); --HEX2[3] is HEX2[3] --operation mode is output HEX2[3] = OUTPUT(T3L4); --HEX2[4] is HEX2[4] --operation mode is output HEX2[4] = OUTPUT(T3L5); --HEX2[5] is HEX2[5] --operation mode is output HEX2[5] = OUTPUT(T3L6); --HEX2[6] is HEX2[6] --operation mode is output HEX2[6] = OUTPUT(!T3L7); --HEX3[0] is HEX3[0] --operation mode is output HEX3[0] = OUTPUT(T4L1); --HEX3[1] is HEX3[1] --operation mode is output HEX3[1] = OUTPUT(T4L2); --HEX3[2] is HEX3[2] --operation mode is output HEX3[2] = OUTPUT(T4L3); --HEX3[3] is HEX3[3] --operation mode is output HEX3[3] = OUTPUT(T4L4); --HEX3[4] is HEX3[4] --operation mode is output HEX3[4] = OUTPUT(T4L5); --HEX3[5] is HEX3[5] --operation mode is output HEX3[5] = OUTPUT(T4L6); --HEX3[6] is HEX3[6] --operation mode is output HEX3[6] = OUTPUT(!T4L7); --LEDG[0] is LEDG[0] --operation mode is output LEDG[0] = OUTPUT(K1_oLED_GREEN[0]); --LEDG[1] is LEDG[1] --operation mode is output LEDG[1] = OUTPUT(K1_oLED_GREEN[1]); --LEDG[2] is LEDG[2] --operation mode is output LEDG[2] = OUTPUT(K1_oLED_GREEN[2]); --LEDG[3] is LEDG[3] --operation mode is output LEDG[3] = OUTPUT(K1_oLED_GREEN[3]); --LEDG[4] is LEDG[4] --operation mode is output LEDG[4] = OUTPUT(K1_oLED_GREEN[4]); --LEDG[5] is LEDG[5] --operation mode is output LEDG[5] = OUTPUT(K1_oLED_GREEN[5]); --LEDG[6] is LEDG[6] --operation mode is output LEDG[6] = OUTPUT(K1_oLED_GREEN[6]); --LEDG[7] is LEDG[7] --operation mode is output LEDG[7] = OUTPUT(K1_oLED_GREEN[7]); --LEDR[0] is LEDR[0] --operation mode is output LEDR[0] = OUTPUT(K1_oLED_RED[0]); --LEDR[1] is LEDR[1] --operation mode is output LEDR[1] = OUTPUT(K1_oLED_RED[1]); --LEDR[2] is LEDR[2] --operation mode is output LEDR[2] = OUTPUT(K1_oLED_RED[2]); --LEDR[3] is LEDR[3] --operation mode is output LEDR[3] = OUTPUT(K1_oLED_RED[3]); --LEDR[4] is LEDR[4] --operation mode is output LEDR[4] = OUTPUT(K1_oLED_RED[4]); --LEDR[5] is LEDR[5] --operation mode is output LEDR[5] = OUTPUT(K1_oLED_RED[5]); --LEDR[6] is LEDR[6] --operation mode is output LEDR[6] = OUTPUT(K1_oLED_RED[6]); --LEDR[7] is LEDR[7] --operation mode is output LEDR[7] = OUTPUT(K1_oLED_RED[7]); --LEDR[8] is LEDR[8] --operation mode is output LEDR[8] = OUTPUT(K1_oLED_RED[8]); --LEDR[9] is LEDR[9] --operation mode is output LEDR[9] = OUTPUT(K1_oLED_RED[9]); --UART_TXD is UART_TXD --operation mode is output UART_TXD = OUTPUT(GND); --DRAM_ADDR[0] is DRAM_ADDR[0] --operation mode is output DRAM_ADDR[0] = OUTPUT(Z1_SA[0]); --DRAM_ADDR[1] is DRAM_ADDR[1] --operation mode is output DRAM_ADDR[1] = OUTPUT(Z1_SA[1]); --DRAM_ADDR[2] is DRAM_ADDR[2] --operation mode is output DRAM_ADDR[2] = OUTPUT(Z1_SA[2]); --DRAM_ADDR[3] is DRAM_ADDR[3] --operation mode is output DRAM_ADDR[3] = OUTPUT(Z1_SA[3]); --DRAM_ADDR[4] is DRAM_ADDR[4] --operation mode is output DRAM_ADDR[4] = OUTPUT(Z1_SA[4]); --DRAM_ADDR[5] is DRAM_ADDR[5] --operation mode is output DRAM_ADDR[5] = OUTPUT(Z1_SA[5]); --DRAM_ADDR[6] is DRAM_ADDR[6] --operation mode is output DRAM_ADDR[6] = OUTPUT(Z1_SA[6]); --DRAM_ADDR[7] is DRAM_ADDR[7] --operation mode is output DRAM_ADDR[7] = OUTPUT(Z1_SA[7]); --DRAM_ADDR[8] is DRAM_ADDR[8] --operation mode is output DRAM_ADDR[8] = OUTPUT(Z1_SA[8]); --DRAM_ADDR[9] is DRAM_ADDR[9] --operation mode is output DRAM_ADDR[9] = OUTPUT(Z1_SA[9]); --DRAM_ADDR[10] is DRAM_ADDR[10] --operation mode is output DRAM_ADDR[10] = OUTPUT(Z1_SA[10]); --DRAM_ADDR[11] is DRAM_ADDR[11] --operation mode is output DRAM_ADDR[11] = OUTPUT(Z1_SA[11]); --DRAM_LDQM is DRAM_LDQM --operation mode is output DRAM_LDQM = OUTPUT(Z1_DQM[1]); --DRAM_UDQM is DRAM_UDQM --operation mode is output DRAM_UDQM = OUTPUT(Z1_DQM[1]); --DRAM_WE_N is DRAM_WE_N --operation mode is output DRAM_WE_N = OUTPUT(Z1_WE_N); --DRAM_CAS_N is DRAM_CAS_N --operation mode is output DRAM_CAS_N = OUTPUT(Z1_CAS_N); --DRAM_RAS_N is DRAM_RAS_N --operation mode is output DRAM_RAS_N = OUTPUT(Z1_RAS_N); --DRAM_CS_N is DRAM_CS_N --operation mode is output DRAM_CS_N = OUTPUT(Z1_CS_N[0]); --DRAM_BA_0 is DRAM_BA_0 --operation mode is output DRAM_BA_0 = OUTPUT(Z1_BA[0]); --DRAM_BA_1 is DRAM_BA_1 --operation mode is output DRAM_BA_1 = OUTPUT(Z1_BA[1]); --DRAM_CLK is DRAM_CLK --operation mode is output DRAM_CLK = OUTPUT(S1__clk2); --DRAM_CKE is DRAM_CKE --operation mode is output DRAM_CKE = OUTPUT(!Z1_CS_N[0]); --FL_ADDR[0] is FL_ADDR[0] --operation mode is output FL_ADDR[0] = OUTPUT(X1L85); --FL_ADDR[1] is FL_ADDR[1] --operation mode is output FL_ADDR[1] = OUTPUT(X1L86); --FL_ADDR[2] is FL_ADDR[2] --operation mode is output FL_ADDR[2] = OUTPUT(X1L87); --FL_ADDR[3] is FL_ADDR[3] --operation mode is output FL_ADDR[3] = OUTPUT(X1L88); --FL_ADDR[4] is FL_ADDR[4] --operation mode is output FL_ADDR[4] = OUTPUT(X1L89); --FL_ADDR[5] is FL_ADDR[5] --operation mode is output FL_ADDR[5] = OUTPUT(X1L90); --FL_ADDR[6] is FL_ADDR[6] --operation mode is output FL_ADDR[6] = OUTPUT(X1L91); --FL_ADDR[7] is FL_ADDR[7] --operation mode is output FL_ADDR[7] = OUTPUT(X1L92); --FL_ADDR[8] is FL_ADDR[8] --operation mode is output FL_ADDR[8] = OUTPUT(X1L93); --FL_ADDR[9] is FL_ADDR[9] --operation mode is output FL_ADDR[9] = OUTPUT(X1L94); --FL_ADDR[10] is FL_ADDR[10] --operation mode is output FL_ADDR[10] = OUTPUT(X1L95); --FL_ADDR[11] is FL_ADDR[11] --operation mode is output FL_ADDR[11] = OUTPUT(X1L96); --FL_ADDR[12] is FL_ADDR[12] --operation mode is output FL_ADDR[12] = OUTPUT(X1L97); --FL_ADDR[13] is FL_ADDR[13] --operation mode is output FL_ADDR[13] = OUTPUT(X1L98); --FL_ADDR[14] is FL_ADDR[14] --operation mode is output FL_ADDR[14] = OUTPUT(X1L99); --FL_ADDR[15] is FL_ADDR[15] --operation mode is output FL_ADDR[15] = OUTPUT(X1L100); --FL_ADDR[16] is FL_ADDR[16] --operation mode is output FL_ADDR[16] = OUTPUT(X1L101); --FL_ADDR[17] is FL_ADDR[17] --operation mode is output FL_ADDR[17] = OUTPUT(X1L102); --FL_ADDR[18] is FL_ADDR[18] --operation mode is output FL_ADDR[18] = OUTPUT(X1L103); --FL_ADDR[19] is FL_ADDR[19] --operation mode is output FL_ADDR[19] = OUTPUT(X1L104); --FL_ADDR[20] is FL_ADDR[20] --operation mode is output FL_ADDR[20] = OUTPUT(X1L105); --FL_ADDR[21] is FL_ADDR[21] --operation mode is output FL_ADDR[21] = OUTPUT(X1L106); --FL_WE_N is FL_WE_N --operation mode is output FL_WE_N = OUTPUT(X1L108); --FL_RST_N is FL_RST_N --operation mode is output FL_RST_N = OUTPUT(VCC); --FL_OE_N is FL_OE_N --operation mode is output FL_OE_N = OUTPUT(!X1_ST.READ); --FL_CE_N is FL_CE_N --operation mode is output FL_CE_N = OUTPUT(!X1_ST.IDEL); --SRAM_ADDR[0] is SRAM_ADDR[0] --operation mode is output SRAM_ADDR[0] = OUTPUT(L1L3); --SRAM_ADDR[1] is SRAM_ADDR[1] --operation mode is output SRAM_ADDR[1] = OUTPUT(L1L4); --SRAM_ADDR[2] is SRAM_ADDR[2] --operation mode is output SRAM_ADDR[2] = OUTPUT(L1L5); --SRAM_ADDR[3] is SRAM_ADDR[3] --operation mode is output SRAM_ADDR[3] = OUTPUT(L1L6); --SRAM_ADDR[4] is SRAM_ADDR[4] --operation mode is output SRAM_ADDR[4] = OUTPUT(L1L7); --SRAM_ADDR[5] is SRAM_ADDR[5] --operation mode is output SRAM_ADDR[5] = OUTPUT(L1L8); --SRAM_ADDR[6] is SRAM_ADDR[6] --operation mode is output SRAM_ADDR[6] = OUTPUT(L1L9); --SRAM_ADDR[7] is SRAM_ADDR[7] --operation mode is output SRAM_ADDR[7] = OUTPUT(L1L10); --SRAM_ADDR[8] is SRAM_ADDR[8] --operation mode is output SRAM_ADDR[8] = OUTPUT(L1L11); --SRAM_ADDR[9] is SRAM_ADDR[9] --operation mode is output SRAM_ADDR[9] = OUTPUT(L1L12); --SRAM_ADDR[10] is SRAM_ADDR[10] --operation mode is output SRAM_ADDR[10] = OUTPUT(L1L13); --SRAM_ADDR[11] is SRAM_ADDR[11] --operation mode is output SRAM_ADDR[11] = OUTPUT(L1L14); --SRAM_ADDR[12] is SRAM_ADDR[12] --operation mode is output SRAM_ADDR[12] = OUTPUT(L1L15); --SRAM_ADDR[13] is SRAM_ADDR[13] --operation mode is output SRAM_ADDR[13] = OUTPUT(L1L16); --SRAM_ADDR[14] is SRAM_ADDR[14] --operation mode is output SRAM_ADDR[14] = OUTPUT(L1L17); --SRAM_ADDR[15] is SRAM_ADDR[15] --operation mode is output SRAM_ADDR[15] = OUTPUT(L1L18); --SRAM_ADDR[16] is SRAM_ADDR[16] --operation mode is output SRAM_ADDR[16] = OUTPUT(L1L19); --SRAM_ADDR[17] is SRAM_ADDR[17] --operation mode is output SRAM_ADDR[17] = OUTPUT(L1L20); --SRAM_UB_N is SRAM_UB_N --operation mode is output SRAM_UB_N = OUTPUT(GND); --SRAM_LB_N is SRAM_LB_N --operation mode is output SRAM_LB_N = OUTPUT(GND); --SRAM_WE_N is SRAM_WE_N --operation mode is output SRAM_WE_N = OUTPUT(!L1L38); --SRAM_CE_N is SRAM_CE_N --operation mode is output SRAM_CE_N = OUTPUT(GND); --SRAM_OE_N is SRAM_OE_N --operation mode is output SRAM_OE_N = OUTPUT(L1L37); --SD_CLK is SD_CLK --operation mode is output SD_CLK = OUTPUT(GND); --TDO is TDO --operation mode is output TDO = OUTPUT(V1_TDO); --I2C_SCLK is I2C_SCLK --operation mode is output I2C_SCLK = OUTPUT(MB1L17); --VGA_HS is VGA_HS --operation mode is output VGA_HS = OUTPUT(M1_oVGA_H_SYNC); --VGA_VS is VGA_VS --operation mode is output VGA_VS = OUTPUT(M1_oVGA_V_SYNC); --VGA_R[0] is VGA_R[0] --operation mode is output VGA_R[0] = OUTPUT(M1L458); --VGA_R[1] is VGA_R[1] --operation mode is output VGA_R[1] = OUTPUT(M1L459); --VGA_R[2] is VGA_R[2] --operation mode is output VGA_R[2] = OUTPUT(M1L460); --VGA_R[3] is VGA_R[3] --operation mode is output VGA_R[3] = OUTPUT(M1L461); --VGA_G[0] is VGA_G[0] --operation mode is output VGA_G[0] = OUTPUT(M1L453); --VGA_G[1] is VGA_G[1] --operation mode is output VGA_G[1] = OUTPUT(M1L454); --VGA_G[2] is VGA_G[2] --operation mode is output VGA_G[2] = OUTPUT(M1L455); --VGA_G[3] is VGA_G[3] --operation mode is output VGA_G[3] = OUTPUT(M1L456); --VGA_B[0] is VGA_B[0] --operation mode is output VGA_B[0] = OUTPUT(M1L449); --VGA_B[1] is VGA_B[1] --operation mode is output VGA_B[1] = OUTPUT(M1L450); --VGA_B[2] is VGA_B[2] --operation mode is output VGA_B[2] = OUTPUT(M1L451); --VGA_B[3] is VGA_B[3] --operation mode is output VGA_B[3] = OUTPUT(M1L452); --AUD_ADCLRCK is AUD_ADCLRCK --operation mode is output AUD_ADCLRCK = OUTPUT(Q1_LRCK_1X); --AUD_DACLRCK is AUD_DACLRCK --operation mode is output AUD_DACLRCK = OUTPUT(Q1_LRCK_1X); --AUD_DACDAT is AUD_DACDAT --operation mode is output AUD_DACDAT = OUTPUT(Q1L238); --AUD_XCK is AUD_XCK --operation mode is output AUD_XCK = OUTPUT(S2__clk1); --SD_DAT3 is SD_DAT3 --operation mode is bidir SD_DAT3 = BIDIR(OPNDRN(VCC)); --SD_CMD is SD_CMD --operation mode is bidir SD_CMD = BIDIR(OPNDRN(VCC)); --A1L35 is DRAM_DQ[0]~15 --operation mode is bidir A1L35 = DRAM_DQ[0]; --DRAM_DQ[0] is DRAM_DQ[0] --operation mode is bidir DRAM_DQ[0]_tri_out = TRI(CB1_DIN2[0], AB1_OE); DRAM_DQ[0] = BIDIR(DRAM_DQ[0]_tri_out); --A1L37 is DRAM_DQ[1]~14 --operation mode is bidir A1L37 = DRAM_DQ[1]; --DRAM_DQ[1] is DRAM_DQ[1] --operation mode is bidir DRAM_DQ[1]_tri_out = TRI(CB1_DIN2[1], AB1_OE); DRAM_DQ[1] = BIDIR(DRAM_DQ[1]_tri_out); --A1L39 is DRAM_DQ[2]~13 --operation mode is bidir A1L39 = DRAM_DQ[2]; --DRAM_DQ[2] is DRAM_DQ[2] --operation mode is bidir DRAM_DQ[2]_tri_out = TRI(CB1_DIN2[2], AB1_OE); DRAM_DQ[2] = BIDIR(DRAM_DQ[2]_tri_out); --A1L41 is DRAM_DQ[3]~12 --operation mode is bidir A1L41 = DRAM_DQ[3]; --DRAM_DQ[3] is DRAM_DQ[3] --operation mode is bidir DRAM_DQ[3]_tri_out = TRI(CB1_DIN2[3], AB1_OE); DRAM_DQ[3] = BIDIR(DRAM_DQ[3]_tri_out); --A1L43 is DRAM_DQ[4]~11 --operation mode is bidir A1L43 = DRAM_DQ[4]; --DRAM_DQ[4] is DRAM_DQ[4] --operation mode is bidir DRAM_DQ[4]_tri_out = TRI(CB1_DIN2[4], AB1_OE); DRAM_DQ[4] = BIDIR(DRAM_DQ[4]_tri_out); --A1L45 is DRAM_DQ[5]~10 --operation mode is bidir A1L45 = DRAM_DQ[5]; --DRAM_DQ[5] is DRAM_DQ[5] --operation mode is bidir DRAM_DQ[5]_tri_out = TRI(CB1_DIN2[5], AB1_OE); DRAM_DQ[5] = BIDIR(DRAM_DQ[5]_tri_out); --A1L47 is DRAM_DQ[6]~9 --operation mode is bidir A1L47 = DRAM_DQ[6]; --DRAM_DQ[6] is DRAM_DQ[6] --operation mode is bidir DRAM_DQ[6]_tri_out = TRI(CB1_DIN2[6], AB1_OE); DRAM_DQ[6] = BIDIR(DRAM_DQ[6]_tri_out); --A1L49 is DRAM_DQ[7]~8 --operation mode is bidir A1L49 = DRAM_DQ[7]; --DRAM_DQ[7] is DRAM_DQ[7] --operation mode is bidir DRAM_DQ[7]_tri_out = TRI(CB1_DIN2[7], AB1_OE); DRAM_DQ[7] = BIDIR(DRAM_DQ[7]_tri_out); --A1L51 is DRAM_DQ[8]~7 --operation mode is bidir A1L51 = DRAM_DQ[8]; --DRAM_DQ[8] is DRAM_DQ[8] --operation mode is bidir DRAM_DQ[8]_tri_out = TRI(CB1_DIN2[8], AB1_OE); DRAM_DQ[8] = BIDIR(DRAM_DQ[8]_tri_out); --A1L53 is DRAM_DQ[9]~6 --operation mode is bidir A1L53 = DRAM_DQ[9]; --DRAM_DQ[9] is DRAM_DQ[9] --operation mode is bidir DRAM_DQ[9]_tri_out = TRI(CB1_DIN2[9], AB1_OE); DRAM_DQ[9] = BIDIR(DRAM_DQ[9]_tri_out); --A1L55 is DRAM_DQ[10]~5 --operation mode is bidir A1L55 = DRAM_DQ[10]; --DRAM_DQ[10] is DRAM_DQ[10] --operation mode is bidir DRAM_DQ[10]_tri_out = TRI(CB1_DIN2[10], AB1_OE); DRAM_DQ[10] = BIDIR(DRAM_DQ[10]_tri_out); --A1L57 is DRAM_DQ[11]~4 --operation mode is bidir A1L57 = DRAM_DQ[11]; --DRAM_DQ[11] is DRAM_DQ[11] --operation mode is bidir DRAM_DQ[11]_tri_out = TRI(CB1_DIN2[11], AB1_OE); DRAM_DQ[11] = BIDIR(DRAM_DQ[11]_tri_out); --A1L59 is DRAM_DQ[12]~3 --operation mode is bidir A1L59 = DRAM_DQ[12]; --DRAM_DQ[12] is DRAM_DQ[12] --operation mode is bidir DRAM_DQ[12]_tri_out = TRI(CB1_DIN2[12], AB1_OE); DRAM_DQ[12] = BIDIR(DRAM_DQ[12]_tri_out); --A1L61 is DRAM_DQ[13]~2 --operation mode is bidir A1L61 = DRAM_DQ[13]; --DRAM_DQ[13] is DRAM_DQ[13] --operation mode is bidir DRAM_DQ[13]_tri_out = TRI(CB1_DIN2[13], AB1_OE); DRAM_DQ[13] = BIDIR(DRAM_DQ[13]_tri_out); --A1L63 is DRAM_DQ[14]~1 --operation mode is bidir A1L63 = DRAM_DQ[14]; --DRAM_DQ[14] is DRAM_DQ[14] --operation mode is bidir DRAM_DQ[14]_tri_out = TRI(CB1_DIN2[14], AB1_OE); DRAM_DQ[14] = BIDIR(DRAM_DQ[14]_tri_out); --A1L65 is DRAM_DQ[15]~0 --operation mode is bidir A1L65 = DRAM_DQ[15]; --DRAM_DQ[15] is DRAM_DQ[15] --operation mode is bidir DRAM_DQ[15]_tri_out = TRI(CB1_DIN2[15], AB1_OE); DRAM_DQ[15] = BIDIR(DRAM_DQ[15]_tri_out); --A1L97 is FL_DQ[0]~7 --operation mode is bidir A1L97 = FL_DQ[0]; --FL_DQ[0] is FL_DQ[0] --operation mode is bidir FL_DQ[0]_tri_out = TRI(X1L193, !X1_ST.READ); FL_DQ[0] = BIDIR(FL_DQ[0]_tri_out); --A1L99 is FL_DQ[1]~6 --operation mode is bidir A1L99 = FL_DQ[1]; --FL_DQ[1] is FL_DQ[1] --operation mode is bidir FL_DQ[1]_tri_out = TRI(X1L194, !X1_ST.READ); FL_DQ[1] = BIDIR(FL_DQ[1]_tri_out); --A1L101 is FL_DQ[2]~5 --operation mode is bidir A1L101 = FL_DQ[2]; --FL_DQ[2] is FL_DQ[2] --operation mode is bidir FL_DQ[2]_tri_out = TRI(X1L195, !X1_ST.READ); FL_DQ[2] = BIDIR(FL_DQ[2]_tri_out); --A1L103 is FL_DQ[3]~4 --operation mode is bidir A1L103 = FL_DQ[3]; --FL_DQ[3] is FL_DQ[3] --operation mode is bidir FL_DQ[3]_tri_out = TRI(X1L196, !X1_ST.READ); FL_DQ[3] = BIDIR(FL_DQ[3]_tri_out); --A1L105 is FL_DQ[4]~3 --operation mode is bidir A1L105 = FL_DQ[4]; --FL_DQ[4] is FL_DQ[4] --operation mode is bidir FL_DQ[4]_tri_out = TRI(X1L197, !X1_ST.READ); FL_DQ[4] = BIDIR(FL_DQ[4]_tri_out); --A1L107 is FL_DQ[5]~2 --operation mode is bidir A1L107 = FL_DQ[5]; --FL_DQ[5] is FL_DQ[5] --operation mode is bidir FL_DQ[5]_tri_out = TRI(X1L199, !X1_ST.READ); FL_DQ[5] = BIDIR(FL_DQ[5]_tri_out); --A1L109 is FL_DQ[6]~1 --operation mode is bidir A1L109 = FL_DQ[6]; --FL_DQ[6] is FL_DQ[6] --operation mode is bidir FL_DQ[6]_tri_out = TRI(X1L200, !X1_ST.READ); FL_DQ[6] = BIDIR(FL_DQ[6]_tri_out); --A1L111 is FL_DQ[7]~0 --operation mode is bidir A1L111 = FL_DQ[7]; --FL_DQ[7] is FL_DQ[7] --operation mode is bidir FL_DQ[7]_tri_out = TRI(X1L201, !X1_ST.READ); FL_DQ[7] = BIDIR(FL_DQ[7]_tri_out); --A1L277 is SRAM_DQ[0]~15 --operation mode is bidir A1L277 = SRAM_DQ[0]; --SRAM_DQ[0] is SRAM_DQ[0] --operation mode is bidir SRAM_DQ[0]_tri_out = TRI(L1L21, L1L38); SRAM_DQ[0] = BIDIR(SRAM_DQ[0]_tri_out); --A1L279 is SRAM_DQ[1]~14 --operation mode is bidir A1L279 = SRAM_DQ[1]; --SRAM_DQ[1] is SRAM_DQ[1] --operation mode is bidir SRAM_DQ[1]_tri_out = TRI(L1L22, L1L38); SRAM_DQ[1] = BIDIR(SRAM_DQ[1]_tri_out); --A1L281 is SRAM_DQ[2]~13 --operation mode is bidir A1L281 = SRAM_DQ[2]; --SRAM_DQ[2] is SRAM_DQ[2] --operation mode is bidir SRAM_DQ[2]_tri_out = TRI(L1L23, L1L38); SRAM_DQ[2] = BIDIR(SRAM_DQ[2]_tri_out); --A1L283 is SRAM_DQ[3]~12 --operation mode is bidir A1L283 = SRAM_DQ[3]; --SRAM_DQ[3] is SRAM_DQ[3] --operation mode is bidir SRAM_DQ[3]_tri_out = TRI(L1L24, L1L38); SRAM_DQ[3] = BIDIR(SRAM_DQ[3]_tri_out); --A1L285 is SRAM_DQ[4]~11 --operation mode is bidir A1L285 = SRAM_DQ[4]; --SRAM_DQ[4] is SRAM_DQ[4] --operation mode is bidir SRAM_DQ[4]_tri_out = TRI(L1L25, L1L38); SRAM_DQ[4] = BIDIR(SRAM_DQ[4]_tri_out); --A1L287 is SRAM_DQ[5]~10 --operation mode is bidir A1L287 = SRAM_DQ[5]; --SRAM_DQ[5] is SRAM_DQ[5] --operation mode is bidir SRAM_DQ[5]_tri_out = TRI(L1L26, L1L38); SRAM_DQ[5] = BIDIR(SRAM_DQ[5]_tri_out); --A1L289 is SRAM_DQ[6]~9 --operation mode is bidir A1L289 = SRAM_DQ[6]; --SRAM_DQ[6] is SRAM_DQ[6] --operation mode is bidir SRAM_DQ[6]_tri_out = TRI(L1L27, L1L38); SRAM_DQ[6] = BIDIR(SRAM_DQ[6]_tri_out); --A1L291 is SRAM_DQ[7]~8 --operation mode is bidir A1L291 = SRAM_DQ[7]; --SRAM_DQ[7] is SRAM_DQ[7] --operation mode is bidir SRAM_DQ[7]_tri_out = TRI(L1L28, L1L38); SRAM_DQ[7] = BIDIR(SRAM_DQ[7]_tri_out); --A1L293 is SRAM_DQ[8]~7 --operation mode is bidir A1L293 = SRAM_DQ[8]; --SRAM_DQ[8] is SRAM_DQ[8] --operation mode is bidir SRAM_DQ[8]_tri_out = TRI(L1L29, L1L38); SRAM_DQ[8] = BIDIR(SRAM_DQ[8]_tri_out); --A1L295 is SRAM_DQ[9]~6 --operation mode is bidir A1L295 = SRAM_DQ[9]; --SRAM_DQ[9] is SRAM_DQ[9] --operation mode is bidir SRAM_DQ[9]_tri_out = TRI(L1L30, L1L38); SRAM_DQ[9] = BIDIR(SRAM_DQ[9]_tri_out); --A1L297 is SRAM_DQ[10]~5 --operation mode is bidir A1L297 = SRAM_DQ[10]; --SRAM_DQ[10] is SRAM_DQ[10] --operation mode is bidir SRAM_DQ[10]_tri_out = TRI(L1L31, L1L38); SRAM_DQ[10] = BIDIR(SRAM_DQ[10]_tri_out); --A1L299 is SRAM_DQ[11]~4 --operation mode is bidir A1L299 = SRAM_DQ[11]; --SRAM_DQ[11] is SRAM_DQ[11] --operation mode is bidir SRAM_DQ[11]_tri_out = TRI(L1L32, L1L38); SRAM_DQ[11] = BIDIR(SRAM_DQ[11]_tri_out); --A1L301 is SRAM_DQ[12]~3 --operation mode is bidir A1L301 = SRAM_DQ[12]; --SRAM_DQ[12] is SRAM_DQ[12] --operation mode is bidir SRAM_DQ[12]_tri_out = TRI(L1L33, L1L38); SRAM_DQ[12] = BIDIR(SRAM_DQ[12]_tri_out); --A1L303 is SRAM_DQ[13]~2 --operation mode is bidir A1L303 = SRAM_DQ[13]; --SRAM_DQ[13] is SRAM_DQ[13] --operation mode is bidir SRAM_DQ[13]_tri_out = TRI(L1L34, L1L38); SRAM_DQ[13] = BIDIR(SRAM_DQ[13]_tri_out); --A1L305 is SRAM_DQ[14]~1 --operation mode is bidir A1L305 = SRAM_DQ[14]; --SRAM_DQ[14] is SRAM_DQ[14] --operation mode is bidir SRAM_DQ[14]_tri_out = TRI(L1L35, L1L38); SRAM_DQ[14] = BIDIR(SRAM_DQ[14]_tri_out); --A1L307 is SRAM_DQ[15]~0 --operation mode is bidir A1L307 = SRAM_DQ[15]; --SRAM_DQ[15] is SRAM_DQ[15] --operation mode is bidir SRAM_DQ[15]_tri_out = TRI(L1L36, L1L38); SRAM_DQ[15] = BIDIR(SRAM_DQ[15]_tri_out); --SD_DAT is SD_DAT --operation mode is bidir SD_DAT = BIDIR(OPNDRN(VCC)); --A1L223 is I2C_SDAT~0 --operation mode is bidir A1L223 = I2C_SDAT; --I2C_SDAT is I2C_SDAT --operation mode is bidir I2C_SDAT = BIDIR(OPNDRN(!MB1L25Q)); --AUD_BCLK is AUD_BCLK --operation mode is bidir AUD_BCLK_tri_out = TRI(Q1_oAUD_BCK, VCC); AUD_BCLK = BIDIR(AUD_BCLK_tri_out); --GPIO_0[0] is GPIO_0[0] --operation mode is bidir GPIO_0[0] = BIDIR(OPNDRN(VCC)); --GPIO_0[1] is GPIO_0[1] --operation mode is bidir GPIO_0[1] = BIDIR(OPNDRN(VCC)); --GPIO_0[2] is GPIO_0[2] --operation mode is bidir GPIO_0[2] = BIDIR(OPNDRN(VCC)); --GPIO_0[3] is GPIO_0[3] --operation mode is bidir GPIO_0[3] = BIDIR(OPNDRN(VCC)); --GPIO_0[4] is GPIO_0[4] --operation mode is bidir GPIO_0[4] = BIDIR(OPNDRN(VCC)); --GPIO_0[5] is GPIO_0[5] --operation mode is bidir GPIO_0[5] = BIDIR(OPNDRN(VCC)); --GPIO_0[6] is GPIO_0[6] --operation mode is bidir GPIO_0[6] = BIDIR(OPNDRN(VCC)); --GPIO_0[7] is GPIO_0[7] --operation mode is bidir GPIO_0[7] = BIDIR(OPNDRN(VCC)); --GPIO_0[8] is GPIO_0[8] --operation mode is bidir GPIO_0[8] = BIDIR(OPNDRN(VCC)); --GPIO_0[9] is GPIO_0[9] --operation mode is bidir GPIO_0[9] = BIDIR(OPNDRN(VCC)); --GPIO_0[10] is GPIO_0[10] --operation mode is bidir GPIO_0[10] = BIDIR(OPNDRN(VCC)); --GPIO_0[11] is GPIO_0[11] --operation mode is bidir GPIO_0[11] = BIDIR(OPNDRN(VCC)); --GPIO_0[12] is GPIO_0[12] --operation mode is bidir GPIO_0[12] = BIDIR(OPNDRN(VCC)); --GPIO_0[13] is GPIO_0[13] --operation mode is bidir GPIO_0[13] = BIDIR(OPNDRN(VCC)); --GPIO_0[14] is GPIO_0[14] --operation mode is bidir GPIO_0[14] = BIDIR(OPNDRN(VCC)); --GPIO_0[15] is GPIO_0[15] --operation mode is bidir GPIO_0[15] = BIDIR(OPNDRN(VCC)); --GPIO_0[16] is GPIO_0[16] --operation mode is bidir GPIO_0[16] = BIDIR(OPNDRN(VCC)); --GPIO_0[17] is GPIO_0[17] --operation mode is bidir GPIO_0[17] = BIDIR(OPNDRN(VCC)); --GPIO_0[18] is GPIO_0[18] --operation mode is bidir GPIO_0[18] = BIDIR(OPNDRN(VCC)); --GPIO_0[19] is GPIO_0[19] --operation mode is bidir GPIO_0[19] = BIDIR(OPNDRN(VCC)); --GPIO_0[20] is GPIO_0[20] --operation mode is bidir GPIO_0[20] = BIDIR(OPNDRN(VCC)); --GPIO_0[21] is GPIO_0[21] --operation mode is bidir GPIO_0[21] = BIDIR(OPNDRN(VCC)); --GPIO_0[22] is GPIO_0[22] --operation mode is bidir GPIO_0[22] = BIDIR(OPNDRN(VCC)); --GPIO_0[23] is GPIO_0[23] --operation mode is bidir GPIO_0[23] = BIDIR(OPNDRN(VCC)); --GPIO_0[24] is GPIO_0[24] --operation mode is bidir GPIO_0[24] = BIDIR(OPNDRN(VCC)); --GPIO_0[25] is GPIO_0[25] --operation mode is bidir GPIO_0[25] = BIDIR(OPNDRN(VCC)); --GPIO_0[26] is GPIO_0[26] --operation mode is bidir GPIO_0[26] = BIDIR(OPNDRN(VCC)); --GPIO_0[27] is GPIO_0[27] --operation mode is bidir GPIO_0[27] = BIDIR(OPNDRN(VCC)); --GPIO_0[28] is GPIO_0[28] --operation mode is bidir GPIO_0[28] = BIDIR(OPNDRN(VCC)); --GPIO_0[29] is GPIO_0[29] --operation mode is bidir GPIO_0[29] = BIDIR(OPNDRN(VCC)); --GPIO_0[30] is GPIO_0[30] --operation mode is bidir GPIO_0[30] = BIDIR(OPNDRN(VCC)); --GPIO_0[31] is GPIO_0[31] --operation mode is bidir GPIO_0[31] = BIDIR(OPNDRN(VCC)); --GPIO_0[32] is GPIO_0[32] --operation mode is bidir GPIO_0[32] = BIDIR(OPNDRN(VCC)); --GPIO_0[33] is GPIO_0[33] --operation mode is bidir GPIO_0[33] = BIDIR(OPNDRN(VCC)); --GPIO_0[34] is GPIO_0[34] --operation mode is bidir GPIO_0[34] = BIDIR(OPNDRN(VCC)); --GPIO_0[35] is GPIO_0[35] --operation mode is bidir GPIO_0[35] = BIDIR(OPNDRN(VCC)); --GPIO_1[0] is GPIO_1[0] --operation mode is bidir GPIO_1[0] = BIDIR(OPNDRN(VCC)); --GPIO_1[1] is GPIO_1[1] --operation mode is bidir GPIO_1[1] = BIDIR(OPNDRN(VCC)); --GPIO_1[2] is GPIO_1[2] --operation mode is bidir GPIO_1[2] = BIDIR(OPNDRN(VCC)); --GPIO_1[3] is GPIO_1[3] --operation mode is bidir GPIO_1[3] = BIDIR(OPNDRN(VCC)); --GPIO_1[4] is GPIO_1[4] --operation mode is bidir GPIO_1[4] = BIDIR(OPNDRN(VCC)); --GPIO_1[5] is GPIO_1[5] --operation mode is bidir GPIO_1[5] = BIDIR(OPNDRN(VCC)); --GPIO_1[6] is GPIO_1[6] --operation mode is bidir GPIO_1[6] = BIDIR(OPNDRN(VCC)); --GPIO_1[7] is GPIO_1[7] --operation mode is bidir GPIO_1[7] = BIDIR(OPNDRN(VCC)); --GPIO_1[8] is GPIO_1[8] --operation mode is bidir GPIO_1[8] = BIDIR(OPNDRN(VCC)); --GPIO_1[9] is GPIO_1[9] --operation mode is bidir GPIO_1[9] = BIDIR(OPNDRN(VCC)); --GPIO_1[10] is GPIO_1[10] --operation mode is bidir GPIO_1[10] = BIDIR(OPNDRN(VCC)); --GPIO_1[11] is GPIO_1[11] --operation mode is bidir GPIO_1[11] = BIDIR(OPNDRN(VCC)); --GPIO_1[12] is GPIO_1[12] --operation mode is bidir GPIO_1[12] = BIDIR(OPNDRN(VCC)); --GPIO_1[13] is GPIO_1[13] --operation mode is bidir GPIO_1[13] = BIDIR(OPNDRN(VCC)); --GPIO_1[14] is GPIO_1[14] --operation mode is bidir GPIO_1[14] = BIDIR(OPNDRN(VCC)); --GPIO_1[15] is GPIO_1[15] --operation mode is bidir GPIO_1[15] = BIDIR(OPNDRN(VCC)); --GPIO_1[16] is GPIO_1[16] --operation mode is bidir GPIO_1[16] = BIDIR(OPNDRN(VCC)); --GPIO_1[17] is GPIO_1[17] --operation mode is bidir GPIO_1[17] = BIDIR(OPNDRN(VCC)); --GPIO_1[18] is GPIO_1[18] --operation mode is bidir GPIO_1[18] = BIDIR(OPNDRN(VCC)); --GPIO_1[19] is GPIO_1[19] --operation mode is bidir GPIO_1[19] = BIDIR(OPNDRN(VCC)); --GPIO_1[20] is GPIO_1[20] --operation mode is bidir GPIO_1[20] = BIDIR(OPNDRN(VCC)); --GPIO_1[21] is GPIO_1[21] --operation mode is bidir GPIO_1[21] = BIDIR(OPNDRN(VCC)); --GPIO_1[22] is GPIO_1[22] --operation mode is bidir GPIO_1[22] = BIDIR(OPNDRN(VCC)); --GPIO_1[23] is GPIO_1[23] --operation mode is bidir GPIO_1[23] = BIDIR(OPNDRN(VCC)); --GPIO_1[24] is GPIO_1[24] --operation mode is bidir GPIO_1[24] = BIDIR(OPNDRN(VCC)); --GPIO_1[25] is GPIO_1[25] --operation mode is bidir GPIO_1[25] = BIDIR(OPNDRN(VCC)); --GPIO_1[26] is GPIO_1[26] --operation mode is bidir GPIO_1[26] = BIDIR(OPNDRN(VCC)); --GPIO_1[27] is GPIO_1[27] --operation mode is bidir GPIO_1[27] = BIDIR(OPNDRN(VCC)); --GPIO_1[28] is GPIO_1[28] --operation mode is bidir GPIO_1[28] = BIDIR(OPNDRN(VCC)); --GPIO_1[29] is GPIO_1[29] --operation mode is bidir GPIO_1[29] = BIDIR(OPNDRN(VCC)); --GPIO_1[30] is GPIO_1[30] --operation mode is bidir GPIO_1[30] = BIDIR(OPNDRN(VCC)); --GPIO_1[31] is GPIO_1[31] --operation mode is bidir GPIO_1[31] = BIDIR(OPNDRN(VCC)); --GPIO_1[32] is GPIO_1[32] --operation mode is bidir GPIO_1[32] = BIDIR(OPNDRN(VCC)); --GPIO_1[33] is GPIO_1[33] --operation mode is bidir GPIO_1[33] = BIDIR(OPNDRN(VCC)); --GPIO_1[34] is GPIO_1[34] --operation mode is bidir GPIO_1[34] = BIDIR(OPNDRN(VCC)); --GPIO_1[35] is GPIO_1[35] --operation mode is bidir GPIO_1[35] = BIDIR(OPNDRN(VCC)); --AB1L19 is Multi_Sdram:u3|Sdram_Controller:u1|command:command1|REF_ACK~56 AB1L19 = !AB1_REF_ACK; --B1L69 is Reset_Delay:d0|Equal~199 B1L69 = !B1L68;